1 /* 2 * Copyright (C) 1995 Linus Torvalds 3 * Adapted from 'alpha' version by Gary Thomas 4 * Modified by Cort Dougan (cort@cs.nmt.edu) 5 */ 6 7 /* 8 * bootup setup stuff.. 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/sched.h> 13 #include <linux/kernel.h> 14 #include <linux/mm.h> 15 #include <linux/stddef.h> 16 #include <linux/unistd.h> 17 #include <linux/ptrace.h> 18 #include <linux/slab.h> 19 #include <linux/user.h> 20 #include <linux/a.out.h> 21 #include <linux/tty.h> 22 #include <linux/major.h> 23 #include <linux/interrupt.h> 24 #include <linux/reboot.h> 25 #include <linux/init.h> 26 #include <linux/pci.h> 27 #include <linux/utsrelease.h> 28 #include <linux/adb.h> 29 #include <linux/module.h> 30 #include <linux/delay.h> 31 #include <linux/console.h> 32 #include <linux/seq_file.h> 33 #include <linux/root_dev.h> 34 #include <linux/initrd.h> 35 #include <linux/timer.h> 36 37 #include <asm/io.h> 38 #include <asm/pgtable.h> 39 #include <asm/prom.h> 40 #include <asm/pci-bridge.h> 41 #include <asm/dma.h> 42 #include <asm/machdep.h> 43 #include <asm/irq.h> 44 #include <asm/hydra.h> 45 #include <asm/sections.h> 46 #include <asm/time.h> 47 #include <asm/i8259.h> 48 #include <asm/mpic.h> 49 #include <asm/rtas.h> 50 #include <asm/xmon.h> 51 52 #include "chrp.h" 53 #include "gg2.h" 54 55 void rtas_indicator_progress(char *, unsigned short); 56 57 int _chrp_type; 58 EXPORT_SYMBOL(_chrp_type); 59 60 static struct mpic *chrp_mpic; 61 62 /* Used for doing CHRP event-scans */ 63 DEFINE_PER_CPU(struct timer_list, heartbeat_timer); 64 unsigned long event_scan_interval; 65 66 /* 67 * XXX this should be in xmon.h, but putting it there means xmon.h 68 * has to include <linux/interrupt.h> (to get irqreturn_t), which 69 * causes all sorts of problems. -- paulus 70 */ 71 extern irqreturn_t xmon_irq(int, void *); 72 73 extern unsigned long loops_per_jiffy; 74 75 /* To be replaced by RTAS when available */ 76 static unsigned int __iomem *briq_SPOR; 77 78 #ifdef CONFIG_SMP 79 extern struct smp_ops_t chrp_smp_ops; 80 #endif 81 82 static const char *gg2_memtypes[4] = { 83 "FPM", "SDRAM", "EDO", "BEDO" 84 }; 85 static const char *gg2_cachesizes[4] = { 86 "256 KB", "512 KB", "1 MB", "Reserved" 87 }; 88 static const char *gg2_cachetypes[4] = { 89 "Asynchronous", "Reserved", "Flow-Through Synchronous", 90 "Pipelined Synchronous" 91 }; 92 static const char *gg2_cachemodes[4] = { 93 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" 94 }; 95 96 static const char *chrp_names[] = { 97 "Unknown", 98 "","","", 99 "Motorola", 100 "IBM or Longtrail", 101 "Genesi Pegasos", 102 "Total Impact Briq" 103 }; 104 105 void chrp_show_cpuinfo(struct seq_file *m) 106 { 107 int i, sdramen; 108 unsigned int t; 109 struct device_node *root; 110 const char *model = ""; 111 112 root = of_find_node_by_path("/"); 113 if (root) 114 model = of_get_property(root, "model", NULL); 115 seq_printf(m, "machine\t\t: CHRP %s\n", model); 116 117 /* longtrail (goldengate) stuff */ 118 if (!strncmp(model, "IBM,LongTrail", 13)) { 119 /* VLSI VAS96011/12 `Golden Gate 2' */ 120 /* Memory banks */ 121 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) 122 >>31) & 1; 123 for (i = 0; i < (sdramen ? 4 : 6); i++) { 124 t = in_le32(gg2_pci_config_base+ 125 GG2_PCI_DRAM_BANK0+ 126 i*4); 127 if (!(t & 1)) 128 continue; 129 switch ((t>>8) & 0x1f) { 130 case 0x1f: 131 model = "4 MB"; 132 break; 133 case 0x1e: 134 model = "8 MB"; 135 break; 136 case 0x1c: 137 model = "16 MB"; 138 break; 139 case 0x18: 140 model = "32 MB"; 141 break; 142 case 0x10: 143 model = "64 MB"; 144 break; 145 case 0x00: 146 model = "128 MB"; 147 break; 148 default: 149 model = "Reserved"; 150 break; 151 } 152 seq_printf(m, "memory bank %d\t: %s %s\n", i, model, 153 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); 154 } 155 /* L2 cache */ 156 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); 157 seq_printf(m, "board l2\t: %s %s (%s)\n", 158 gg2_cachesizes[(t>>7) & 3], 159 gg2_cachetypes[(t>>2) & 3], 160 gg2_cachemodes[t & 3]); 161 } 162 of_node_put(root); 163 } 164 165 /* 166 * Fixes for the National Semiconductor PC78308VUL SuperI/O 167 * 168 * Some versions of Open Firmware incorrectly initialize the IRQ settings 169 * for keyboard and mouse 170 */ 171 static inline void __init sio_write(u8 val, u8 index) 172 { 173 outb(index, 0x15c); 174 outb(val, 0x15d); 175 } 176 177 static inline u8 __init sio_read(u8 index) 178 { 179 outb(index, 0x15c); 180 return inb(0x15d); 181 } 182 183 static void __init sio_fixup_irq(const char *name, u8 device, u8 level, 184 u8 type) 185 { 186 u8 level0, type0, active; 187 188 /* select logical device */ 189 sio_write(device, 0x07); 190 active = sio_read(0x30); 191 level0 = sio_read(0x70); 192 type0 = sio_read(0x71); 193 if (level0 != level || type0 != type || !active) { 194 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " 195 "remapping to level %d, type %d, active\n", 196 name, level0, type0, !active ? "in" : "", level, type); 197 sio_write(0x01, 0x30); 198 sio_write(level, 0x70); 199 sio_write(type, 0x71); 200 } 201 } 202 203 static void __init sio_init(void) 204 { 205 struct device_node *root; 206 207 if ((root = of_find_node_by_path("/")) && 208 !strncmp(of_get_property(root, "model", NULL), 209 "IBM,LongTrail", 13)) { 210 /* logical device 0 (KBC/Keyboard) */ 211 sio_fixup_irq("keyboard", 0, 1, 2); 212 /* select logical device 1 (KBC/Mouse) */ 213 sio_fixup_irq("mouse", 1, 12, 2); 214 } 215 of_node_put(root); 216 } 217 218 219 static void __init pegasos_set_l2cr(void) 220 { 221 struct device_node *np; 222 223 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ 224 if (_chrp_type != _CHRP_Pegasos) 225 return; 226 227 /* Enable L2 cache if needed */ 228 np = of_find_node_by_type(NULL, "cpu"); 229 if (np != NULL) { 230 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL); 231 if (l2cr == NULL) { 232 printk ("Pegasos l2cr : no cpu l2cr property found\n"); 233 goto out; 234 } 235 if (!((*l2cr) & 0x80000000)) { 236 printk ("Pegasos l2cr : L2 cache was not active, " 237 "activating\n"); 238 _set_L2CR(0); 239 _set_L2CR((*l2cr) | 0x80000000); 240 } 241 } 242 out: 243 of_node_put(np); 244 } 245 246 static void briq_restart(char *cmd) 247 { 248 local_irq_disable(); 249 if (briq_SPOR) 250 out_be32(briq_SPOR, 0); 251 for(;;); 252 } 253 254 void __init chrp_setup_arch(void) 255 { 256 struct device_node *root = of_find_node_by_path("/"); 257 const char *machine = NULL; 258 259 /* init to some ~sane value until calibrate_delay() runs */ 260 loops_per_jiffy = 50000000/HZ; 261 262 if (root) 263 machine = of_get_property(root, "model", NULL); 264 if (machine && strncmp(machine, "Pegasos", 7) == 0) { 265 _chrp_type = _CHRP_Pegasos; 266 } else if (machine && strncmp(machine, "IBM", 3) == 0) { 267 _chrp_type = _CHRP_IBM; 268 } else if (machine && strncmp(machine, "MOT", 3) == 0) { 269 _chrp_type = _CHRP_Motorola; 270 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { 271 _chrp_type = _CHRP_briq; 272 /* Map the SPOR register on briq and change the restart hook */ 273 briq_SPOR = ioremap(0xff0000e8, 4); 274 ppc_md.restart = briq_restart; 275 } else { 276 /* Let's assume it is an IBM chrp if all else fails */ 277 _chrp_type = _CHRP_IBM; 278 } 279 of_node_put(root); 280 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); 281 282 rtas_initialize(); 283 if (rtas_token("display-character") >= 0) 284 ppc_md.progress = rtas_progress; 285 286 /* use RTAS time-of-day routines if available */ 287 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { 288 ppc_md.get_boot_time = rtas_get_boot_time; 289 ppc_md.get_rtc_time = rtas_get_rtc_time; 290 ppc_md.set_rtc_time = rtas_set_rtc_time; 291 } 292 293 /* On pegasos, enable the L2 cache if not already done by OF */ 294 pegasos_set_l2cr(); 295 296 /* Lookup PCI host bridges */ 297 chrp_find_bridges(); 298 299 /* 300 * Temporary fixes for PCI devices. 301 * -- Geert 302 */ 303 hydra_init(); /* Mac I/O */ 304 305 /* 306 * Fix the Super I/O configuration 307 */ 308 sio_init(); 309 310 pci_create_OF_bus_map(); 311 312 /* 313 * Print the banner, then scroll down so boot progress 314 * can be printed. -- Cort 315 */ 316 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); 317 } 318 319 void 320 chrp_event_scan(unsigned long unused) 321 { 322 unsigned char log[1024]; 323 int ret = 0; 324 325 /* XXX: we should loop until the hardware says no more error logs -- Cort */ 326 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, 327 __pa(log), 1024); 328 mod_timer(&__get_cpu_var(heartbeat_timer), 329 jiffies + event_scan_interval); 330 } 331 332 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) 333 { 334 unsigned int cascade_irq = i8259_irq(); 335 if (cascade_irq != NO_IRQ) 336 generic_handle_irq(cascade_irq); 337 desc->chip->eoi(irq); 338 } 339 340 /* 341 * Finds the open-pic node and sets up the mpic driver. 342 */ 343 static void __init chrp_find_openpic(void) 344 { 345 struct device_node *np, *root; 346 int len, i, j; 347 int isu_size, idu_size; 348 const unsigned int *iranges, *opprop = NULL; 349 int oplen = 0; 350 unsigned long opaddr; 351 int na = 1; 352 353 np = of_find_node_by_type(NULL, "open-pic"); 354 if (np == NULL) 355 return; 356 root = of_find_node_by_path("/"); 357 if (root) { 358 opprop = of_get_property(root, "platform-open-pic", &oplen); 359 na = of_n_addr_cells(root); 360 } 361 if (opprop && oplen >= na * sizeof(unsigned int)) { 362 opaddr = opprop[na-1]; /* assume 32-bit */ 363 oplen /= na * sizeof(unsigned int); 364 } else { 365 struct resource r; 366 if (of_address_to_resource(np, 0, &r)) { 367 goto bail; 368 } 369 opaddr = r.start; 370 oplen = 0; 371 } 372 373 printk(KERN_INFO "OpenPIC at %lx\n", opaddr); 374 375 iranges = of_get_property(np, "interrupt-ranges", &len); 376 if (iranges == NULL) 377 len = 0; /* non-distributed mpic */ 378 else 379 len /= 2 * sizeof(unsigned int); 380 381 /* 382 * The first pair of cells in interrupt-ranges refers to the 383 * IDU; subsequent pairs refer to the ISUs. 384 */ 385 if (oplen < len) { 386 printk(KERN_ERR "Insufficient addresses for distributed" 387 " OpenPIC (%d < %d)\n", oplen, len); 388 len = oplen; 389 } 390 391 isu_size = 0; 392 idu_size = 0; 393 if (len > 0 && iranges[1] != 0) { 394 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", 395 iranges[0], iranges[0] + iranges[1] - 1); 396 idu_size = iranges[1]; 397 } 398 if (len > 1) 399 isu_size = iranges[3]; 400 401 chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, 402 isu_size, 0, " MPIC "); 403 if (chrp_mpic == NULL) { 404 printk(KERN_ERR "Failed to allocate MPIC structure\n"); 405 goto bail; 406 } 407 j = na - 1; 408 for (i = 1; i < len; ++i) { 409 iranges += 2; 410 j += na; 411 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", 412 iranges[0], iranges[0] + iranges[1] - 1, 413 opprop[j]); 414 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); 415 } 416 417 mpic_init(chrp_mpic); 418 ppc_md.get_irq = mpic_get_irq; 419 bail: 420 of_node_put(root); 421 of_node_put(np); 422 } 423 424 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 425 static struct irqaction xmon_irqaction = { 426 .handler = xmon_irq, 427 .mask = CPU_MASK_NONE, 428 .name = "XMON break", 429 }; 430 #endif 431 432 static void __init chrp_find_8259(void) 433 { 434 struct device_node *np, *pic = NULL; 435 unsigned long chrp_int_ack = 0; 436 unsigned int cascade_irq; 437 438 /* Look for cascade */ 439 for_each_node_by_type(np, "interrupt-controller") 440 if (of_device_is_compatible(np, "chrp,iic")) { 441 pic = np; 442 break; 443 } 444 /* Ok, 8259 wasn't found. We need to handle the case where 445 * we have a pegasos that claims to be chrp but doesn't have 446 * a proper interrupt tree 447 */ 448 if (pic == NULL && chrp_mpic != NULL) { 449 printk(KERN_ERR "i8259: Not found in device-tree" 450 " assuming no legacy interrupts\n"); 451 return; 452 } 453 454 /* Look for intack. In a perfect world, we would look for it on 455 * the ISA bus that holds the 8259 but heh... Works that way. If 456 * we ever see a problem, we can try to re-use the pSeries code here. 457 * Also, Pegasos-type platforms don't have a proper node to start 458 * from anyway 459 */ 460 for_each_node_by_name(np, "pci") { 461 const unsigned int *addrp = of_get_property(np, 462 "8259-interrupt-acknowledge", NULL); 463 464 if (addrp == NULL) 465 continue; 466 chrp_int_ack = addrp[of_n_addr_cells(np)-1]; 467 break; 468 } 469 of_node_put(np); 470 if (np == NULL) 471 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" 472 " address, polling\n"); 473 474 i8259_init(pic, chrp_int_ack); 475 if (ppc_md.get_irq == NULL) { 476 ppc_md.get_irq = i8259_irq; 477 irq_set_default_host(i8259_get_host()); 478 } 479 if (chrp_mpic != NULL) { 480 cascade_irq = irq_of_parse_and_map(pic, 0); 481 if (cascade_irq == NO_IRQ) 482 printk(KERN_ERR "i8259: failed to map cascade irq\n"); 483 else 484 set_irq_chained_handler(cascade_irq, 485 chrp_8259_cascade); 486 } 487 } 488 489 void __init chrp_init_IRQ(void) 490 { 491 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 492 struct device_node *kbd; 493 #endif 494 chrp_find_openpic(); 495 chrp_find_8259(); 496 497 #ifdef CONFIG_SMP 498 /* Pegasos has no MPIC, those ops would make it crash. It might be an 499 * option to move setting them to after we probe the PIC though 500 */ 501 if (chrp_mpic != NULL) 502 smp_ops = &chrp_smp_ops; 503 #endif /* CONFIG_SMP */ 504 505 if (_chrp_type == _CHRP_Pegasos) 506 ppc_md.get_irq = i8259_irq; 507 508 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 509 /* see if there is a keyboard in the device tree 510 with a parent of type "adb" */ 511 for_each_node_by_name(kbd, "keyboard") 512 if (kbd->parent && kbd->parent->type 513 && strcmp(kbd->parent->type, "adb") == 0) 514 break; 515 of_node_put(kbd); 516 if (kbd) 517 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); 518 #endif 519 } 520 521 void __init 522 chrp_init2(void) 523 { 524 struct device_node *device; 525 const unsigned int *p = NULL; 526 527 #ifdef CONFIG_NVRAM 528 chrp_nvram_init(); 529 #endif 530 531 request_region(0x20,0x20,"pic1"); 532 request_region(0xa0,0x20,"pic2"); 533 request_region(0x00,0x20,"dma1"); 534 request_region(0x40,0x20,"timer"); 535 request_region(0x80,0x10,"dma page reg"); 536 request_region(0xc0,0x20,"dma2"); 537 538 /* Get the event scan rate for the rtas so we know how 539 * often it expects a heartbeat. -- Cort 540 */ 541 device = of_find_node_by_name(NULL, "rtas"); 542 if (device) 543 p = of_get_property(device, "rtas-event-scan-rate", NULL); 544 if (p && *p) { 545 /* 546 * Arrange to call chrp_event_scan at least *p times 547 * per minute. We use 59 rather than 60 here so that 548 * the rate will be slightly higher than the minimum. 549 * This all assumes we don't do hotplug CPU on any 550 * machine that needs the event scans done. 551 */ 552 unsigned long interval, offset; 553 int cpu, ncpus; 554 struct timer_list *timer; 555 556 interval = HZ * 59 / *p; 557 offset = HZ; 558 ncpus = num_online_cpus(); 559 event_scan_interval = ncpus * interval; 560 for (cpu = 0; cpu < ncpus; ++cpu) { 561 timer = &per_cpu(heartbeat_timer, cpu); 562 setup_timer(timer, chrp_event_scan, 0); 563 timer->expires = jiffies + offset; 564 add_timer_on(timer, cpu); 565 offset += interval; 566 } 567 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", 568 *p, interval); 569 } 570 of_node_put(device); 571 572 if (ppc_md.progress) 573 ppc_md.progress(" Have fun! ", 0x7777); 574 } 575 576 static int __init chrp_probe(void) 577 { 578 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), 579 "device_type", NULL); 580 if (dtype == NULL) 581 return 0; 582 if (strcmp(dtype, "chrp")) 583 return 0; 584 585 ISA_DMA_THRESHOLD = ~0L; 586 DMA_MODE_READ = 0x44; 587 DMA_MODE_WRITE = 0x48; 588 589 return 1; 590 } 591 592 define_machine(chrp) { 593 .name = "CHRP", 594 .probe = chrp_probe, 595 .setup_arch = chrp_setup_arch, 596 .init = chrp_init2, 597 .show_cpuinfo = chrp_show_cpuinfo, 598 .init_IRQ = chrp_init_IRQ, 599 .restart = rtas_restart, 600 .power_off = rtas_power_off, 601 .halt = rtas_halt, 602 .time_init = chrp_time_init, 603 .set_rtc_time = chrp_set_rtc_time, 604 .get_rtc_time = chrp_get_rtc_time, 605 .calibrate_decr = generic_calibrate_decr, 606 .phys_mem_access_prot = pci_phys_mem_access_prot, 607 }; 608