1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de> 4 * Thanks to : 5 * Dale Farnsworth <dale@farnsworth.org> 6 * Mark A. Greer <mgreer@mvista.com> 7 * Nicolas DET <nd@bplan-gmbh.de> 8 * Benjamin Herrenschmidt <benh@kernel.crashing.org> 9 * And anyone else who helped me on this. 10 */ 11 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/platform_device.h> 17 #include <linux/mv643xx_eth.h> 18 #include <linux/pci.h> 19 20 #define PEGASOS2_MARVELL_REGBASE (0xf1000000) 21 #define PEGASOS2_MARVELL_REGSIZE (0x00004000) 22 #define PEGASOS2_SRAM_BASE (0xf2000000) 23 #define PEGASOS2_SRAM_SIZE (256*1024) 24 25 #define PEGASOS2_SRAM_BASE_ETH_PORT0 (PEGASOS2_SRAM_BASE) 26 #define PEGASOS2_SRAM_BASE_ETH_PORT1 (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) ) 27 28 #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) 29 #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4) 30 31 #undef BE_VERBOSE 32 33 #define MV64340_BASE_ADDR_ENABLE 0x278 34 #define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268 35 #define MV64340_SRAM_CONFIG 0x380 36 37 static struct resource mv643xx_eth_shared_resources[] = { 38 [0] = { 39 .name = "ethernet shared base", 40 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS, 41 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 42 MV643XX_ETH_SHARED_REGS_SIZE - 1, 43 .flags = IORESOURCE_MEM, 44 }, 45 }; 46 47 static struct platform_device mv643xx_eth_shared_device = { 48 .name = MV643XX_ETH_SHARED_NAME, 49 .id = 0, 50 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources), 51 .resource = mv643xx_eth_shared_resources, 52 }; 53 54 /* 55 * The orion mdio driver only covers shared + 0x4 up to shared + 0x84 - 1 56 */ 57 static struct resource mv643xx_eth_mvmdio_resources[] = { 58 [0] = { 59 .name = "ethernet mdio base", 60 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x4, 61 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x83, 62 .flags = IORESOURCE_MEM, 63 }, 64 }; 65 66 static struct platform_device mv643xx_eth_mvmdio_device = { 67 .name = "orion-mdio", 68 .id = -1, 69 .num_resources = ARRAY_SIZE(mv643xx_eth_mvmdio_resources), 70 .resource = mv643xx_eth_mvmdio_resources, 71 }; 72 73 static struct resource mv643xx_eth_port1_resources[] = { 74 [0] = { 75 .name = "eth port1 irq", 76 .start = 9, 77 .end = 9, 78 .flags = IORESOURCE_IRQ, 79 }, 80 }; 81 82 static struct mv643xx_eth_platform_data eth_port1_pd = { 83 .shared = &mv643xx_eth_shared_device, 84 .port_number = 1, 85 .phy_addr = MV643XX_ETH_PHY_ADDR(7), 86 87 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1, 88 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, 89 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, 90 91 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE, 92 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, 93 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, 94 }; 95 96 static struct platform_device eth_port1_device = { 97 .name = MV643XX_ETH_NAME, 98 .id = 1, 99 .num_resources = ARRAY_SIZE(mv643xx_eth_port1_resources), 100 .resource = mv643xx_eth_port1_resources, 101 .dev = { 102 .platform_data = ð_port1_pd, 103 }, 104 }; 105 106 static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { 107 &mv643xx_eth_shared_device, 108 &mv643xx_eth_mvmdio_device, 109 ð_port1_device, 110 }; 111 112 /***********/ 113 /***********/ 114 #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } 115 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset) 116 117 static void __iomem *mv643xx_reg_base; 118 119 static int __init Enable_SRAM(void) 120 { 121 u32 ALong; 122 123 if (mv643xx_reg_base == NULL) 124 mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, 125 PEGASOS2_MARVELL_REGSIZE); 126 127 if (mv643xx_reg_base == NULL) 128 return -ENOMEM; 129 130 #ifdef BE_VERBOSE 131 printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", 132 (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base); 133 #endif 134 135 MV_WRITE(MV64340_SRAM_CONFIG, 0); 136 137 MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16); 138 139 MV_READ(MV64340_BASE_ADDR_ENABLE, ALong); 140 ALong &= ~(1 << 19); 141 MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong); 142 143 ALong = 0x02; 144 ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; 145 MV_WRITE(MV643XX_ETH_BAR_4, ALong); 146 147 MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000); 148 149 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); 150 ALong &= ~(1 << 4); 151 MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); 152 153 #ifdef BE_VERBOSE 154 printk("Pegasos II/Marvell MV64361: register unmapped\n"); 155 printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE); 156 #endif 157 158 iounmap(mv643xx_reg_base); 159 mv643xx_reg_base = NULL; 160 161 return 1; 162 } 163 164 165 /***********/ 166 /***********/ 167 static int __init mv643xx_eth_add_pds(void) 168 { 169 int ret = 0; 170 static struct pci_device_id pci_marvell_mv64360[] = { 171 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) }, 172 { } 173 }; 174 175 #ifdef BE_VERBOSE 176 printk("Pegasos II/Marvell MV64361: init\n"); 177 #endif 178 179 if (pci_dev_present(pci_marvell_mv64360)) { 180 ret = platform_add_devices(mv643xx_eth_pd_devs, 181 ARRAY_SIZE(mv643xx_eth_pd_devs)); 182 183 if ( Enable_SRAM() < 0) 184 { 185 eth_port1_pd.tx_sram_addr = 0; 186 eth_port1_pd.tx_sram_size = 0; 187 eth_port1_pd.rx_sram_addr = 0; 188 eth_port1_pd.rx_sram_size = 0; 189 190 #ifdef BE_VERBOSE 191 printk("Pegasos II/Marvell MV64361: Can't enable the " 192 "SRAM\n"); 193 #endif 194 } 195 } 196 197 #ifdef BE_VERBOSE 198 printk("Pegasos II/Marvell MV64361: init is over\n"); 199 #endif 200 201 return ret; 202 } 203 204 device_initcall(mv643xx_eth_add_pds); 205