1 /* 2 * CHRP pci routines. 3 */ 4 5 #include <linux/config.h> 6 #include <linux/kernel.h> 7 #include <linux/pci.h> 8 #include <linux/delay.h> 9 #include <linux/string.h> 10 #include <linux/init.h> 11 #include <linux/ide.h> 12 13 #include <asm/io.h> 14 #include <asm/pgtable.h> 15 #include <asm/irq.h> 16 #include <asm/hydra.h> 17 #include <asm/prom.h> 18 #include <asm/gg2.h> 19 #include <asm/machdep.h> 20 #include <asm/sections.h> 21 #include <asm/pci-bridge.h> 22 #include <asm/open_pic.h> 23 #include <asm/grackle.h> 24 #include <asm/rtas.h> 25 26 #include "chrp.h" 27 28 /* LongTrail */ 29 void __iomem *gg2_pci_config_base; 30 31 /* 32 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we 33 * limit the bus number to 3 bits 34 */ 35 36 int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, 37 int len, u32 *val) 38 { 39 volatile void __iomem *cfg_data; 40 struct pci_controller *hose = bus->sysdata; 41 42 if (bus->number > 7) 43 return PCIBIOS_DEVICE_NOT_FOUND; 44 /* 45 * Note: the caller has already checked that off is 46 * suitably aligned and that len is 1, 2 or 4. 47 */ 48 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); 49 switch (len) { 50 case 1: 51 *val = in_8(cfg_data); 52 break; 53 case 2: 54 *val = in_le16(cfg_data); 55 break; 56 default: 57 *val = in_le32(cfg_data); 58 break; 59 } 60 return PCIBIOS_SUCCESSFUL; 61 } 62 63 int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, 64 int len, u32 val) 65 { 66 volatile void __iomem *cfg_data; 67 struct pci_controller *hose = bus->sysdata; 68 69 if (bus->number > 7) 70 return PCIBIOS_DEVICE_NOT_FOUND; 71 /* 72 * Note: the caller has already checked that off is 73 * suitably aligned and that len is 1, 2 or 4. 74 */ 75 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); 76 switch (len) { 77 case 1: 78 out_8(cfg_data, val); 79 break; 80 case 2: 81 out_le16(cfg_data, val); 82 break; 83 default: 84 out_le32(cfg_data, val); 85 break; 86 } 87 return PCIBIOS_SUCCESSFUL; 88 } 89 90 static struct pci_ops gg2_pci_ops = 91 { 92 gg2_read_config, 93 gg2_write_config 94 }; 95 96 /* 97 * Access functions for PCI config space using RTAS calls. 98 */ 99 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 100 int len, u32 *val) 101 { 102 struct pci_controller *hose = bus->sysdata; 103 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) 104 | (((bus->number - hose->first_busno) & 0xff) << 16) 105 | (hose->index << 24); 106 int ret = -1; 107 int rval; 108 109 rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len); 110 *val = ret; 111 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; 112 } 113 114 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 115 int len, u32 val) 116 { 117 struct pci_controller *hose = bus->sysdata; 118 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) 119 | (((bus->number - hose->first_busno) & 0xff) << 16) 120 | (hose->index << 24); 121 int rval; 122 123 rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL, 124 addr, len, val); 125 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; 126 } 127 128 static struct pci_ops rtas_pci_ops = 129 { 130 rtas_read_config, 131 rtas_write_config 132 }; 133 134 volatile struct Hydra __iomem *Hydra = NULL; 135 136 int __init 137 hydra_init(void) 138 { 139 struct device_node *np; 140 struct resource r; 141 142 np = find_devices("mac-io"); 143 if (np == NULL || of_address_to_resource(np, 0, &r)) 144 return 0; 145 Hydra = ioremap(r.start, r.end-r.start); 146 printk("Hydra Mac I/O at %lx\n", r.start); 147 printk("Hydra Feature_Control was %x", 148 in_le32(&Hydra->Feature_Control)); 149 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | 150 HYDRA_FC_SCSI_CELL_EN | 151 HYDRA_FC_SCCA_ENABLE | 152 HYDRA_FC_SCCB_ENABLE | 153 HYDRA_FC_ARB_BYPASS | 154 HYDRA_FC_MPIC_ENABLE | 155 HYDRA_FC_SLOW_SCC_PCLK | 156 HYDRA_FC_MPIC_IS_MASTER)); 157 printk(", now %x\n", in_le32(&Hydra->Feature_Control)); 158 return 1; 159 } 160 161 void __init 162 chrp_pcibios_fixup(void) 163 { 164 struct pci_dev *dev = NULL; 165 struct device_node *np; 166 167 /* PCI interrupts are controlled by the OpenPIC */ 168 for_each_pci_dev(dev) { 169 np = pci_device_to_OF_node(dev); 170 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0)) 171 dev->irq = np->intrs[0].line; 172 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 173 } 174 } 175 176 #define PRG_CL_RESET_VALID 0x00010000 177 178 static void __init 179 setup_python(struct pci_controller *hose, struct device_node *dev) 180 { 181 u32 __iomem *reg; 182 u32 val; 183 struct resource r; 184 185 if (of_address_to_resource(dev, 0, &r)) { 186 printk(KERN_ERR "No address for Python PCI controller\n"); 187 return; 188 } 189 190 /* Clear the magic go-slow bit */ 191 reg = ioremap(r.start + 0xf6000, 0x40); 192 BUG_ON(!reg); 193 val = in_be32(®[12]); 194 if (val & PRG_CL_RESET_VALID) { 195 out_be32(®[12], val & ~PRG_CL_RESET_VALID); 196 in_be32(®[12]); 197 } 198 iounmap(reg); 199 200 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); 201 } 202 203 /* Marvell Discovery II based Pegasos 2 */ 204 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) 205 { 206 struct device_node *root = find_path_device("/"); 207 struct device_node *rtas; 208 209 of_node_get(root); 210 rtas = of_find_node_by_name (root, "rtas"); 211 if (rtas) { 212 hose->ops = &rtas_pci_ops; 213 of_node_put(rtas); 214 } else { 215 printk ("RTAS supporting Pegasos OF not found, please upgrade" 216 " your firmware\n"); 217 } 218 pci_assign_all_buses = 1; 219 } 220 221 void __init 222 chrp_find_bridges(void) 223 { 224 struct device_node *dev; 225 int *bus_range; 226 int len, index = -1; 227 struct pci_controller *hose; 228 unsigned int *dma; 229 char *model, *machine; 230 int is_longtrail = 0, is_mot = 0, is_pegasos = 0; 231 struct device_node *root = find_path_device("/"); 232 struct resource r; 233 /* 234 * The PCI host bridge nodes on some machines don't have 235 * properties to adequately identify them, so we have to 236 * look at what sort of machine this is as well. 237 */ 238 machine = get_property(root, "model", NULL); 239 if (machine != NULL) { 240 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; 241 is_mot = strncmp(machine, "MOT", 3) == 0; 242 if (strncmp(machine, "Pegasos2", 8) == 0) 243 is_pegasos = 2; 244 else if (strncmp(machine, "Pegasos", 7) == 0) 245 is_pegasos = 1; 246 } 247 for (dev = root->child; dev != NULL; dev = dev->sibling) { 248 if (dev->type == NULL || strcmp(dev->type, "pci") != 0) 249 continue; 250 ++index; 251 /* The GG2 bridge on the LongTrail doesn't have an address */ 252 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) { 253 printk(KERN_WARNING "Can't use %s: no address\n", 254 dev->full_name); 255 continue; 256 } 257 bus_range = (int *) get_property(dev, "bus-range", &len); 258 if (bus_range == NULL || len < 2 * sizeof(int)) { 259 printk(KERN_WARNING "Can't get bus-range for %s\n", 260 dev->full_name); 261 continue; 262 } 263 if (bus_range[1] == bus_range[0]) 264 printk(KERN_INFO "PCI bus %d", bus_range[0]); 265 else 266 printk(KERN_INFO "PCI buses %d..%d", 267 bus_range[0], bus_range[1]); 268 printk(" controlled by %s", dev->type); 269 if (!is_longtrail) 270 printk(" at %lx", r.start); 271 printk("\n"); 272 273 hose = pcibios_alloc_controller(); 274 if (!hose) { 275 printk("Can't allocate PCI controller structure for %s\n", 276 dev->full_name); 277 continue; 278 } 279 hose->arch_data = dev; 280 hose->first_busno = bus_range[0]; 281 hose->last_busno = bus_range[1]; 282 283 model = get_property(dev, "model", NULL); 284 if (model == NULL) 285 model = "<none>"; 286 if (device_is_compatible(dev, "IBM,python")) { 287 setup_python(hose, dev); 288 } else if (is_mot 289 || strncmp(model, "Motorola, Grackle", 17) == 0) { 290 setup_grackle(hose); 291 } else if (is_longtrail) { 292 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); 293 hose->ops = &gg2_pci_ops; 294 hose->cfg_data = p; 295 gg2_pci_config_base = p; 296 } else if (is_pegasos == 1) { 297 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); 298 } else if (is_pegasos == 2) { 299 setup_peg2(hose, dev); 300 } else { 301 printk("No methods for %s (model %s), using RTAS\n", 302 dev->full_name, model); 303 hose->ops = &rtas_pci_ops; 304 } 305 306 pci_process_bridge_OF_ranges(hose, dev, index == 0); 307 308 /* check the first bridge for a property that we can 309 use to set pci_dram_offset */ 310 dma = (unsigned int *) 311 get_property(dev, "ibm,dma-ranges", &len); 312 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { 313 pci_dram_offset = dma[2] - dma[3]; 314 printk("pci_dram_offset = %lx\n", pci_dram_offset); 315 } 316 } 317 318 /* Do not fixup interrupts from OF tree on pegasos */ 319 if (is_pegasos) 320 ppc_md.pcibios_fixup = NULL; 321 } 322