1 /* 2 * CHRP pci routines. 3 */ 4 5 #include <linux/config.h> 6 #include <linux/kernel.h> 7 #include <linux/pci.h> 8 #include <linux/delay.h> 9 #include <linux/string.h> 10 #include <linux/init.h> 11 #include <linux/ide.h> 12 13 #include <asm/io.h> 14 #include <asm/pgtable.h> 15 #include <asm/irq.h> 16 #include <asm/hydra.h> 17 #include <asm/prom.h> 18 #include <asm/gg2.h> 19 #include <asm/machdep.h> 20 #include <asm/sections.h> 21 #include <asm/pci-bridge.h> 22 #include <asm/open_pic.h> 23 #include <asm/grackle.h> 24 #include <asm/rtas.h> 25 26 /* LongTrail */ 27 void __iomem *gg2_pci_config_base; 28 29 /* 30 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we 31 * limit the bus number to 3 bits 32 */ 33 34 int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, 35 int len, u32 *val) 36 { 37 volatile void __iomem *cfg_data; 38 struct pci_controller *hose = bus->sysdata; 39 40 if (bus->number > 7) 41 return PCIBIOS_DEVICE_NOT_FOUND; 42 /* 43 * Note: the caller has already checked that off is 44 * suitably aligned and that len is 1, 2 or 4. 45 */ 46 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); 47 switch (len) { 48 case 1: 49 *val = in_8(cfg_data); 50 break; 51 case 2: 52 *val = in_le16(cfg_data); 53 break; 54 default: 55 *val = in_le32(cfg_data); 56 break; 57 } 58 return PCIBIOS_SUCCESSFUL; 59 } 60 61 int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, 62 int len, u32 val) 63 { 64 volatile void __iomem *cfg_data; 65 struct pci_controller *hose = bus->sysdata; 66 67 if (bus->number > 7) 68 return PCIBIOS_DEVICE_NOT_FOUND; 69 /* 70 * Note: the caller has already checked that off is 71 * suitably aligned and that len is 1, 2 or 4. 72 */ 73 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); 74 switch (len) { 75 case 1: 76 out_8(cfg_data, val); 77 break; 78 case 2: 79 out_le16(cfg_data, val); 80 break; 81 default: 82 out_le32(cfg_data, val); 83 break; 84 } 85 return PCIBIOS_SUCCESSFUL; 86 } 87 88 static struct pci_ops gg2_pci_ops = 89 { 90 gg2_read_config, 91 gg2_write_config 92 }; 93 94 /* 95 * Access functions for PCI config space using RTAS calls. 96 */ 97 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 98 int len, u32 *val) 99 { 100 struct pci_controller *hose = bus->sysdata; 101 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) 102 | (((bus->number - hose->first_busno) & 0xff) << 16) 103 | (hose->index << 24); 104 int ret = -1; 105 int rval; 106 107 rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len); 108 *val = ret; 109 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; 110 } 111 112 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 113 int len, u32 val) 114 { 115 struct pci_controller *hose = bus->sysdata; 116 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) 117 | (((bus->number - hose->first_busno) & 0xff) << 16) 118 | (hose->index << 24); 119 int rval; 120 121 rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL, 122 addr, len, val); 123 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; 124 } 125 126 static struct pci_ops rtas_pci_ops = 127 { 128 rtas_read_config, 129 rtas_write_config 130 }; 131 132 volatile struct Hydra __iomem *Hydra = NULL; 133 134 int __init 135 hydra_init(void) 136 { 137 struct device_node *np; 138 139 np = find_devices("mac-io"); 140 if (np == NULL || np->n_addrs == 0) 141 return 0; 142 Hydra = ioremap(np->addrs[0].address, np->addrs[0].size); 143 printk("Hydra Mac I/O at %lx\n", np->addrs[0].address); 144 printk("Hydra Feature_Control was %x", 145 in_le32(&Hydra->Feature_Control)); 146 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | 147 HYDRA_FC_SCSI_CELL_EN | 148 HYDRA_FC_SCCA_ENABLE | 149 HYDRA_FC_SCCB_ENABLE | 150 HYDRA_FC_ARB_BYPASS | 151 HYDRA_FC_MPIC_ENABLE | 152 HYDRA_FC_SLOW_SCC_PCLK | 153 HYDRA_FC_MPIC_IS_MASTER)); 154 printk(", now %x\n", in_le32(&Hydra->Feature_Control)); 155 return 1; 156 } 157 158 void __init 159 chrp_pcibios_fixup(void) 160 { 161 struct pci_dev *dev = NULL; 162 struct device_node *np; 163 164 /* PCI interrupts are controlled by the OpenPIC */ 165 for_each_pci_dev(dev) { 166 np = pci_device_to_OF_node(dev); 167 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0)) 168 dev->irq = np->intrs[0].line; 169 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 170 } 171 } 172 173 #define PRG_CL_RESET_VALID 0x00010000 174 175 static void __init 176 setup_python(struct pci_controller *hose, struct device_node *dev) 177 { 178 u32 __iomem *reg; 179 u32 val; 180 unsigned long addr = dev->addrs[0].address; 181 182 setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010); 183 184 /* Clear the magic go-slow bit */ 185 reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40); 186 val = in_be32(®[12]); 187 if (val & PRG_CL_RESET_VALID) { 188 out_be32(®[12], val & ~PRG_CL_RESET_VALID); 189 in_be32(®[12]); 190 } 191 iounmap(reg); 192 } 193 194 /* Marvell Discovery II based Pegasos 2 */ 195 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) 196 { 197 struct device_node *root = find_path_device("/"); 198 struct device_node *rtas; 199 200 rtas = of_find_node_by_name (root, "rtas"); 201 if (rtas) { 202 hose->ops = &rtas_pci_ops; 203 } else { 204 printk ("RTAS supporting Pegasos OF not found, please upgrade" 205 " your firmware\n"); 206 } 207 pci_assign_all_buses = 1; 208 } 209 210 void __init 211 chrp_find_bridges(void) 212 { 213 struct device_node *dev; 214 int *bus_range; 215 int len, index = -1; 216 struct pci_controller *hose; 217 unsigned int *dma; 218 char *model, *machine; 219 int is_longtrail = 0, is_mot = 0, is_pegasos = 0; 220 struct device_node *root = find_path_device("/"); 221 222 /* 223 * The PCI host bridge nodes on some machines don't have 224 * properties to adequately identify them, so we have to 225 * look at what sort of machine this is as well. 226 */ 227 machine = get_property(root, "model", NULL); 228 if (machine != NULL) { 229 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; 230 is_mot = strncmp(machine, "MOT", 3) == 0; 231 if (strncmp(machine, "Pegasos2", 8) == 0) 232 is_pegasos = 2; 233 else if (strncmp(machine, "Pegasos", 7) == 0) 234 is_pegasos = 1; 235 } 236 for (dev = root->child; dev != NULL; dev = dev->sibling) { 237 if (dev->type == NULL || strcmp(dev->type, "pci") != 0) 238 continue; 239 ++index; 240 /* The GG2 bridge on the LongTrail doesn't have an address */ 241 if (dev->n_addrs < 1 && !is_longtrail) { 242 printk(KERN_WARNING "Can't use %s: no address\n", 243 dev->full_name); 244 continue; 245 } 246 bus_range = (int *) get_property(dev, "bus-range", &len); 247 if (bus_range == NULL || len < 2 * sizeof(int)) { 248 printk(KERN_WARNING "Can't get bus-range for %s\n", 249 dev->full_name); 250 continue; 251 } 252 if (bus_range[1] == bus_range[0]) 253 printk(KERN_INFO "PCI bus %d", bus_range[0]); 254 else 255 printk(KERN_INFO "PCI buses %d..%d", 256 bus_range[0], bus_range[1]); 257 printk(" controlled by %s", dev->type); 258 if (dev->n_addrs > 0) 259 printk(" at %lx", dev->addrs[0].address); 260 printk("\n"); 261 262 hose = pcibios_alloc_controller(); 263 if (!hose) { 264 printk("Can't allocate PCI controller structure for %s\n", 265 dev->full_name); 266 continue; 267 } 268 hose->arch_data = dev; 269 hose->first_busno = bus_range[0]; 270 hose->last_busno = bus_range[1]; 271 272 model = get_property(dev, "model", NULL); 273 if (model == NULL) 274 model = "<none>"; 275 if (device_is_compatible(dev, "IBM,python")) { 276 setup_python(hose, dev); 277 } else if (is_mot 278 || strncmp(model, "Motorola, Grackle", 17) == 0) { 279 setup_grackle(hose); 280 } else if (is_longtrail) { 281 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); 282 hose->ops = &gg2_pci_ops; 283 hose->cfg_data = p; 284 gg2_pci_config_base = p; 285 } else if (is_pegasos == 1) { 286 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); 287 } else if (is_pegasos == 2) { 288 setup_peg2(hose, dev); 289 } else { 290 printk("No methods for %s (model %s), using RTAS\n", 291 dev->full_name, model); 292 hose->ops = &rtas_pci_ops; 293 } 294 295 pci_process_bridge_OF_ranges(hose, dev, index == 0); 296 297 /* check the first bridge for a property that we can 298 use to set pci_dram_offset */ 299 dma = (unsigned int *) 300 get_property(dev, "ibm,dma-ranges", &len); 301 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { 302 pci_dram_offset = dma[2] - dma[3]; 303 printk("pci_dram_offset = %lx\n", pci_dram_offset); 304 } 305 } 306 307 /* Do not fixup interrupts from OF tree on pegasos */ 308 if (is_pegasos == 0) 309 ppc_md.pcibios_fixup = chrp_pcibios_fixup; 310 } 311