1 /* 2 * External Interrupt Controller on Spider South Bridge 3 * 4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 5 * 6 * Author: Arnd Bergmann <arndb@de.ibm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/ioport.h> 26 27 #include <asm/pgtable.h> 28 #include <asm/prom.h> 29 #include <asm/io.h> 30 31 #include "interrupt.h" 32 33 /* register layout taken from Spider spec, table 7.4-4 */ 34 enum { 35 TIR_DEN = 0x004, /* Detection Enable Register */ 36 TIR_MSK = 0x084, /* Mask Level Register */ 37 TIR_EDC = 0x0c0, /* Edge Detection Clear Register */ 38 TIR_PNDA = 0x100, /* Pending Register A */ 39 TIR_PNDB = 0x104, /* Pending Register B */ 40 TIR_CS = 0x144, /* Current Status Register */ 41 TIR_LCSA = 0x150, /* Level Current Status Register A */ 42 TIR_LCSB = 0x154, /* Level Current Status Register B */ 43 TIR_LCSC = 0x158, /* Level Current Status Register C */ 44 TIR_LCSD = 0x15c, /* Level Current Status Register D */ 45 TIR_CFGA = 0x200, /* Setting Register A0 */ 46 TIR_CFGB = 0x204, /* Setting Register B0 */ 47 /* 0x208 ... 0x3ff Setting Register An/Bn */ 48 TIR_PPNDA = 0x400, /* Packet Pending Register A */ 49 TIR_PPNDB = 0x404, /* Packet Pending Register B */ 50 TIR_PIERA = 0x408, /* Packet Output Error Register A */ 51 TIR_PIERB = 0x40c, /* Packet Output Error Register B */ 52 TIR_PIEN = 0x444, /* Packet Output Enable Register */ 53 TIR_PIPND = 0x454, /* Packet Output Pending Register */ 54 TIRDID = 0x484, /* Spider Device ID Register */ 55 REISTIM = 0x500, /* Reissue Command Timeout Time Setting */ 56 REISTIMEN = 0x504, /* Reissue Command Timeout Setting */ 57 REISWAITEN = 0x508, /* Reissue Wait Control*/ 58 }; 59 60 #define SPIDER_CHIP_COUNT 4 61 #define SPIDER_SRC_COUNT 64 62 #define SPIDER_IRQ_INVALID 63 63 64 struct spider_pic { 65 struct irq_domain *host; 66 void __iomem *regs; 67 unsigned int node_id; 68 }; 69 static struct spider_pic spider_pics[SPIDER_CHIP_COUNT]; 70 71 static struct spider_pic *spider_irq_data_to_pic(struct irq_data *d) 72 { 73 return irq_data_get_irq_chip_data(d); 74 } 75 76 static void __iomem *spider_get_irq_config(struct spider_pic *pic, 77 unsigned int src) 78 { 79 return pic->regs + TIR_CFGA + 8 * src; 80 } 81 82 static void spider_unmask_irq(struct irq_data *d) 83 { 84 struct spider_pic *pic = spider_irq_data_to_pic(d); 85 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); 86 87 out_be32(cfg, in_be32(cfg) | 0x30000000u); 88 } 89 90 static void spider_mask_irq(struct irq_data *d) 91 { 92 struct spider_pic *pic = spider_irq_data_to_pic(d); 93 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); 94 95 out_be32(cfg, in_be32(cfg) & ~0x30000000u); 96 } 97 98 static void spider_ack_irq(struct irq_data *d) 99 { 100 struct spider_pic *pic = spider_irq_data_to_pic(d); 101 unsigned int src = irqd_to_hwirq(d); 102 103 /* Reset edge detection logic if necessary 104 */ 105 if (irqd_is_level_type(d)) 106 return; 107 108 /* Only interrupts 47 to 50 can be set to edge */ 109 if (src < 47 || src > 50) 110 return; 111 112 /* Perform the clear of the edge logic */ 113 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); 114 } 115 116 static int spider_set_irq_type(struct irq_data *d, unsigned int type) 117 { 118 unsigned int sense = type & IRQ_TYPE_SENSE_MASK; 119 struct spider_pic *pic = spider_irq_data_to_pic(d); 120 unsigned int hw = irqd_to_hwirq(d); 121 void __iomem *cfg = spider_get_irq_config(pic, hw); 122 u32 old_mask; 123 u32 ic; 124 125 /* Note that only level high is supported for most interrupts */ 126 if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH && 127 (hw < 47 || hw > 50)) 128 return -EINVAL; 129 130 /* Decode sense type */ 131 switch(sense) { 132 case IRQ_TYPE_EDGE_RISING: 133 ic = 0x3; 134 break; 135 case IRQ_TYPE_EDGE_FALLING: 136 ic = 0x2; 137 break; 138 case IRQ_TYPE_LEVEL_LOW: 139 ic = 0x0; 140 break; 141 case IRQ_TYPE_LEVEL_HIGH: 142 case IRQ_TYPE_NONE: 143 ic = 0x1; 144 break; 145 default: 146 return -EINVAL; 147 } 148 149 /* Configure the source. One gross hack that was there before and 150 * that I've kept around is the priority to the BE which I set to 151 * be the same as the interrupt source number. I don't know whether 152 * that's supposed to make any kind of sense however, we'll have to 153 * decide that, but for now, I'm not changing the behaviour. 154 */ 155 old_mask = in_be32(cfg) & 0x30000000u; 156 out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) | 157 (pic->node_id << 4) | 0xe); 158 out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff)); 159 160 return 0; 161 } 162 163 static struct irq_chip spider_pic = { 164 .name = "SPIDER", 165 .irq_unmask = spider_unmask_irq, 166 .irq_mask = spider_mask_irq, 167 .irq_ack = spider_ack_irq, 168 .irq_set_type = spider_set_irq_type, 169 }; 170 171 static int spider_host_map(struct irq_domain *h, unsigned int virq, 172 irq_hw_number_t hw) 173 { 174 irq_set_chip_data(virq, h->host_data); 175 irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq); 176 177 /* Set default irq type */ 178 irq_set_irq_type(virq, IRQ_TYPE_NONE); 179 180 return 0; 181 } 182 183 static int spider_host_xlate(struct irq_domain *h, struct device_node *ct, 184 const u32 *intspec, unsigned int intsize, 185 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 186 187 { 188 /* Spider interrupts have 2 cells, first is the interrupt source, 189 * second, well, I don't know for sure yet ... We mask the top bits 190 * because old device-trees encode a node number in there 191 */ 192 *out_hwirq = intspec[0] & 0x3f; 193 *out_flags = IRQ_TYPE_LEVEL_HIGH; 194 return 0; 195 } 196 197 static const struct irq_domain_ops spider_host_ops = { 198 .map = spider_host_map, 199 .xlate = spider_host_xlate, 200 }; 201 202 static void spider_irq_cascade(struct irq_desc *desc) 203 { 204 struct irq_chip *chip = irq_desc_get_chip(desc); 205 struct spider_pic *pic = irq_desc_get_handler_data(desc); 206 unsigned int cs, virq; 207 208 cs = in_be32(pic->regs + TIR_CS) >> 24; 209 if (cs == SPIDER_IRQ_INVALID) 210 virq = 0; 211 else 212 virq = irq_linear_revmap(pic->host, cs); 213 214 if (virq) 215 generic_handle_irq(virq); 216 217 chip->irq_eoi(&desc->irq_data); 218 } 219 220 /* For hooking up the cascade we have a problem. Our device-tree is 221 * crap and we don't know on which BE iic interrupt we are hooked on at 222 * least not the "standard" way. We can reconstitute it based on two 223 * informations though: which BE node we are connected to and whether 224 * we are connected to IOIF0 or IOIF1. Right now, we really only care 225 * about the IBM cell blade and we know that its firmware gives us an 226 * interrupt-map property which is pretty strange. 227 */ 228 static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic) 229 { 230 unsigned int virq; 231 const u32 *imap, *tmp; 232 int imaplen, intsize, unit; 233 struct device_node *iic; 234 struct device_node *of_node; 235 236 of_node = irq_domain_get_of_node(pic->host); 237 238 /* First, we check whether we have a real "interrupts" in the device 239 * tree in case the device-tree is ever fixed 240 */ 241 virq = irq_of_parse_and_map(of_node, 0); 242 if (virq) 243 return virq; 244 245 /* Now do the horrible hacks */ 246 tmp = of_get_property(of_node, "#interrupt-cells", NULL); 247 if (tmp == NULL) 248 return 0; 249 intsize = *tmp; 250 imap = of_get_property(of_node, "interrupt-map", &imaplen); 251 if (imap == NULL || imaplen < (intsize + 1)) 252 return 0; 253 iic = of_find_node_by_phandle(imap[intsize]); 254 if (iic == NULL) 255 return 0; 256 imap += intsize + 1; 257 tmp = of_get_property(iic, "#interrupt-cells", NULL); 258 if (tmp == NULL) { 259 of_node_put(iic); 260 return 0; 261 } 262 intsize = *tmp; 263 /* Assume unit is last entry of interrupt specifier */ 264 unit = imap[intsize - 1]; 265 /* Ok, we have a unit, now let's try to get the node */ 266 tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL); 267 if (tmp == NULL) { 268 of_node_put(iic); 269 return 0; 270 } 271 /* ugly as hell but works for now */ 272 pic->node_id = (*tmp) >> 1; 273 of_node_put(iic); 274 275 /* Ok, now let's get cracking. You may ask me why I just didn't match 276 * the iic host from the iic OF node, but that way I'm still compatible 277 * with really really old old firmwares for which we don't have a node 278 */ 279 /* Manufacture an IIC interrupt number of class 2 */ 280 virq = irq_create_mapping(NULL, 281 (pic->node_id << IIC_IRQ_NODE_SHIFT) | 282 (2 << IIC_IRQ_CLASS_SHIFT) | 283 unit); 284 if (!virq) 285 printk(KERN_ERR "spider_pic: failed to map cascade !"); 286 return virq; 287 } 288 289 290 static void __init spider_init_one(struct device_node *of_node, int chip, 291 unsigned long addr) 292 { 293 struct spider_pic *pic = &spider_pics[chip]; 294 int i, virq; 295 296 /* Map registers */ 297 pic->regs = ioremap(addr, 0x1000); 298 if (pic->regs == NULL) 299 panic("spider_pic: can't map registers !"); 300 301 /* Allocate a host */ 302 pic->host = irq_domain_add_linear(of_node, SPIDER_SRC_COUNT, 303 &spider_host_ops, pic); 304 if (pic->host == NULL) 305 panic("spider_pic: can't allocate irq host !"); 306 307 /* Go through all sources and disable them */ 308 for (i = 0; i < SPIDER_SRC_COUNT; i++) { 309 void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i; 310 out_be32(cfg, in_be32(cfg) & ~0x30000000u); 311 } 312 313 /* do not mask any interrupts because of level */ 314 out_be32(pic->regs + TIR_MSK, 0x0); 315 316 /* enable interrupt packets to be output */ 317 out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1); 318 319 /* Hook up the cascade interrupt to the iic and nodeid */ 320 virq = spider_find_cascade_and_node(pic); 321 if (!virq) 322 return; 323 irq_set_handler_data(virq, pic); 324 irq_set_chained_handler(virq, spider_irq_cascade); 325 326 printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", 327 pic->node_id, addr, of_node->full_name); 328 329 /* Enable the interrupt detection enable bit. Do this last! */ 330 out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1); 331 } 332 333 void __init spider_init_IRQ(void) 334 { 335 struct resource r; 336 struct device_node *dn; 337 int chip = 0; 338 339 /* XXX node numbers are totally bogus. We _hope_ we get the device 340 * nodes in the right order here but that's definitely not guaranteed, 341 * we need to get the node from the device tree instead. 342 * There is currently no proper property for it (but our whole 343 * device-tree is bogus anyway) so all we can do is pray or maybe test 344 * the address and deduce the node-id 345 */ 346 for (dn = NULL; 347 (dn = of_find_node_by_name(dn, "interrupt-controller"));) { 348 if (of_device_is_compatible(dn, "CBEA,platform-spider-pic")) { 349 if (of_address_to_resource(dn, 0, &r)) { 350 printk(KERN_WARNING "spider-pic: Failed\n"); 351 continue; 352 } 353 } else if (of_device_is_compatible(dn, "sti,platform-spider-pic") 354 && (chip < 2)) { 355 static long hard_coded_pics[] = 356 { 0x24000008000ul, 0x34000008000ul}; 357 r.start = hard_coded_pics[chip]; 358 } else 359 continue; 360 spider_init_one(dn, chip++, r.start); 361 } 362 } 363