1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/arch/powerpc/platforms/cell/cell_setup.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Adapted from 'alpha' version by Gary Thomas 7 * Modified by Cort Dougan (cort@cs.nmt.edu) 8 * Modified by PPC64 Team, IBM Corp 9 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH 10 */ 11 #undef DEBUG 12 13 #include <linux/sched.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/stddef.h> 17 #include <linux/export.h> 18 #include <linux/unistd.h> 19 #include <linux/user.h> 20 #include <linux/reboot.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/irq.h> 24 #include <linux/seq_file.h> 25 #include <linux/root_dev.h> 26 #include <linux/console.h> 27 #include <linux/mutex.h> 28 #include <linux/memory_hotplug.h> 29 #include <linux/of_platform.h> 30 31 #include <asm/mmu.h> 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 #include <asm/rtas.h> 35 #include <asm/pci-bridge.h> 36 #include <asm/iommu.h> 37 #include <asm/dma.h> 38 #include <asm/machdep.h> 39 #include <asm/time.h> 40 #include <asm/nvram.h> 41 #include <asm/cputable.h> 42 #include <asm/ppc-pci.h> 43 #include <asm/irq.h> 44 #include <asm/spu.h> 45 #include <asm/spu_priv1.h> 46 #include <asm/udbg.h> 47 #include <asm/mpic.h> 48 #include <asm/cell-regs.h> 49 #include <asm/io-workarounds.h> 50 51 #include "cell.h" 52 #include "interrupt.h" 53 #include "pervasive.h" 54 #include "ras.h" 55 56 #ifdef DEBUG 57 #define DBG(fmt...) udbg_printf(fmt) 58 #else 59 #define DBG(fmt...) 60 #endif 61 62 static void cell_show_cpuinfo(struct seq_file *m) 63 { 64 struct device_node *root; 65 const char *model = ""; 66 67 root = of_find_node_by_path("/"); 68 if (root) 69 model = of_get_property(root, "model", NULL); 70 seq_printf(m, "machine\t\t: CHRP %s\n", model); 71 of_node_put(root); 72 } 73 74 static void cell_progress(char *s, unsigned short hex) 75 { 76 printk("*** %04x : %s\n", hex, s ? s : ""); 77 } 78 79 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev) 80 { 81 struct pci_controller *hose; 82 const char *s; 83 int i; 84 85 if (!machine_is(cell)) 86 return; 87 88 /* We're searching for a direct child of the PHB */ 89 if (dev->bus->self != NULL || dev->devfn != 0) 90 return; 91 92 hose = pci_bus_to_host(dev->bus); 93 if (hose == NULL) 94 return; 95 96 /* Only on PCIE */ 97 if (!of_device_is_compatible(hose->dn, "pciex")) 98 return; 99 100 /* And only on axon */ 101 s = of_get_property(hose->dn, "model", NULL); 102 if (!s || strcmp(s, "Axon") != 0) 103 return; 104 105 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 106 dev->resource[i].start = dev->resource[i].end = 0; 107 dev->resource[i].flags = 0; 108 } 109 110 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n", 111 pci_name(dev)); 112 } 113 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex); 114 115 static int cell_setup_phb(struct pci_controller *phb) 116 { 117 const char *model; 118 struct device_node *np; 119 120 int rc = rtas_setup_phb(phb); 121 if (rc) 122 return rc; 123 124 phb->controller_ops = cell_pci_controller_ops; 125 126 np = phb->dn; 127 model = of_get_property(np, "model", NULL); 128 if (model == NULL || !of_node_name_eq(np, "pci")) 129 return 0; 130 131 /* Setup workarounds for spider */ 132 if (strcmp(model, "Spider")) 133 return 0; 134 135 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init, 136 (void *)SPIDER_PCI_REG_BASE); 137 return 0; 138 } 139 140 static const struct of_device_id cell_bus_ids[] __initconst = { 141 { .type = "soc", }, 142 { .compatible = "soc", }, 143 { .type = "spider", }, 144 { .type = "axon", }, 145 { .type = "plb5", }, 146 { .type = "plb4", }, 147 { .type = "opb", }, 148 { .type = "ebc", }, 149 {}, 150 }; 151 152 static int __init cell_publish_devices(void) 153 { 154 struct device_node *root = of_find_node_by_path("/"); 155 struct device_node *np; 156 int node; 157 158 /* Publish OF platform devices for southbridge IOs */ 159 of_platform_bus_probe(NULL, cell_bus_ids, NULL); 160 161 /* On spider based blades, we need to manually create the OF 162 * platform devices for the PCI host bridges 163 */ 164 for_each_child_of_node(root, np) { 165 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex")) 166 continue; 167 of_platform_device_create(np, NULL, NULL); 168 } 169 170 /* There is no device for the MIC memory controller, thus we create 171 * a platform device for it to attach the EDAC driver to. 172 */ 173 for_each_online_node(node) { 174 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL) 175 continue; 176 platform_device_register_simple("cbe-mic", node, NULL, 0); 177 } 178 179 return 0; 180 } 181 machine_subsys_initcall(cell, cell_publish_devices); 182 183 static void __init mpic_init_IRQ(void) 184 { 185 struct device_node *dn; 186 struct mpic *mpic; 187 188 for_each_node_by_name(dn, "interrupt-controller") { 189 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic")) 190 continue; 191 192 /* The MPIC driver will get everything it needs from the 193 * device-tree, just pass 0 to all arguments 194 */ 195 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET, 196 0, 0, " MPIC "); 197 if (mpic == NULL) 198 continue; 199 mpic_init(mpic); 200 } 201 } 202 203 204 static void __init cell_init_irq(void) 205 { 206 iic_init_IRQ(); 207 spider_init_IRQ(); 208 mpic_init_IRQ(); 209 } 210 211 static void __init cell_set_dabrx(void) 212 { 213 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); 214 } 215 216 static void __init cell_setup_arch(void) 217 { 218 #ifdef CONFIG_SPU_BASE 219 spu_priv1_ops = &spu_priv1_mmio_ops; 220 spu_management_ops = &spu_management_of_ops; 221 #endif 222 223 cbe_regs_init(); 224 225 cell_set_dabrx(); 226 227 #ifdef CONFIG_CBE_RAS 228 cbe_ras_init(); 229 #endif 230 231 #ifdef CONFIG_SMP 232 smp_init_cell(); 233 #endif 234 /* init to some ~sane value until calibrate_delay() runs */ 235 loops_per_jiffy = 50000000; 236 237 /* Find and initialize PCI host bridges */ 238 init_pci_config_tokens(); 239 240 cbe_pervasive_init(); 241 242 mmio_nvram_init(); 243 } 244 245 static int __init cell_probe(void) 246 { 247 if (!of_machine_is_compatible("IBM,CBEA") && 248 !of_machine_is_compatible("IBM,CPBW-1.0")) 249 return 0; 250 251 pm_power_off = rtas_power_off; 252 253 return 1; 254 } 255 256 define_machine(cell) { 257 .name = "Cell", 258 .probe = cell_probe, 259 .setup_arch = cell_setup_arch, 260 .show_cpuinfo = cell_show_cpuinfo, 261 .restart = rtas_restart, 262 .halt = rtas_halt, 263 .get_boot_time = rtas_get_boot_time, 264 .get_rtc_time = rtas_get_rtc_time, 265 .set_rtc_time = rtas_set_rtc_time, 266 .calibrate_decr = generic_calibrate_decr, 267 .progress = cell_progress, 268 .init_IRQ = cell_init_irq, 269 .pci_setup_phb = cell_setup_phb, 270 }; 271 272 struct pci_controller_ops cell_pci_controller_ops; 273