xref: /linux/arch/powerpc/platforms/cell/pervasive.c (revision 302eca184fb844670fb128c69e22a8a28bbce48a)
1 /*
2  * CBE Pervasive Monitor and Debug
3  *
4  * (C) Copyright IBM Corporation 2005
5  *
6  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
7  *          Michael N. Day (mnday@us.ibm.com)
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2, or (at your option)
12  * any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  */
23 
24 #undef DEBUG
25 
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/percpu.h>
29 #include <linux/types.h>
30 #include <linux/kallsyms.h>
31 
32 #include <asm/io.h>
33 #include <asm/machdep.h>
34 #include <asm/prom.h>
35 #include <asm/pgtable.h>
36 #include <asm/reg.h>
37 
38 #include "pervasive.h"
39 #include "cbe_regs.h"
40 
41 static void cbe_power_save(void)
42 {
43 	unsigned long ctrl, thread_switch_control;
44 	ctrl = mfspr(SPRN_CTRLF);
45 
46 	/* Enable DEC and EE interrupt request */
47 	thread_switch_control  = mfspr(SPRN_TSC_CELL);
48 	thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
49 
50 	switch (ctrl & CTRL_CT) {
51 	case CTRL_CT0:
52 		thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
53 		break;
54 	case CTRL_CT1:
55 		thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
56 		break;
57 	default:
58 		printk(KERN_WARNING "%s: unknown configuration\n",
59 			__FUNCTION__);
60 		break;
61 	}
62 	mtspr(SPRN_TSC_CELL, thread_switch_control);
63 
64 	/*
65 	 * go into low thread priority, medium priority will be
66 	 * restored for us after wake-up.
67 	 */
68 	HMT_low();
69 
70 	/*
71 	 * atomically disable thread execution and runlatch.
72 	 * External and Decrementer exceptions are still handled when the
73 	 * thread is disabled but now enter in cbe_system_reset_exception()
74 	 */
75 	ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
76 	mtspr(SPRN_CTRLT, ctrl);
77 }
78 
79 static int cbe_system_reset_exception(struct pt_regs *regs)
80 {
81 	switch (regs->msr & SRR1_WAKEMASK) {
82 	case SRR1_WAKEEE:
83 		do_IRQ(regs);
84 		break;
85 	case SRR1_WAKEDEC:
86 		timer_interrupt(regs);
87 		break;
88 	case SRR1_WAKEMT:
89 		break;
90 #ifdef CONFIG_CBE_RAS
91 	case SRR1_WAKESYSERR:
92 		cbe_system_error_exception(regs);
93 		break;
94 	case SRR1_WAKETHERM:
95 		cbe_thermal_exception(regs);
96 		break;
97 #endif /* CONFIG_CBE_RAS */
98 	default:
99 		/* do system reset */
100 		return 0;
101 	}
102 	/* everything handled */
103 	return 1;
104 }
105 
106 void __init cbe_pervasive_init(void)
107 {
108 	int cpu;
109 	if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
110 		return;
111 
112 	for_each_possible_cpu(cpu) {
113 		struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
114 		if (!regs)
115 			continue;
116 
117 		 /* Enable Pause(0) control bit */
118 		out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
119 					    CBE_PMD_PAUSE_ZERO_CONTROL);
120 	}
121 
122 	ppc_md.power_save = cbe_power_save;
123 	ppc_md.system_reset_exception = cbe_system_reset_exception;
124 }
125