xref: /linux/arch/powerpc/platforms/cell/iommu.c (revision b60a5b8dcf49af9f2c60ae82e0383ee8e62a9a52)
1 /*
2  * IOMMU implementation for Cell Broadband Processor Architecture
3  *
4  * (C) Copyright IBM Corporation 2006-2008
5  *
6  * Author: Jeremy Kerr <jk@ozlabs.org>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22 
23 #undef DEBUG
24 
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/notifier.h>
29 #include <linux/of.h>
30 #include <linux/of_platform.h>
31 #include <linux/slab.h>
32 #include <linux/memblock.h>
33 
34 #include <asm/prom.h>
35 #include <asm/iommu.h>
36 #include <asm/machdep.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/udbg.h>
39 #include <asm/firmware.h>
40 #include <asm/cell-regs.h>
41 
42 #include "cell.h"
43 #include "interrupt.h"
44 
45 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
46  * instead of leaving them mapped to some dummy page. This can be
47  * enabled once the appropriate workarounds for spider bugs have
48  * been enabled
49  */
50 #define CELL_IOMMU_REAL_UNMAP
51 
52 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of
53  * IO PTEs based on the transfer direction. That can be enabled
54  * once spider-net has been fixed to pass the correct direction
55  * to the DMA mapping functions
56  */
57 #define CELL_IOMMU_STRICT_PROTECTION
58 
59 
60 #define NR_IOMMUS			2
61 
62 /* IOC mmap registers */
63 #define IOC_Reg_Size			0x2000
64 
65 #define IOC_IOPT_CacheInvd		0x908
66 #define IOC_IOPT_CacheInvd_NE_Mask	0xffe0000000000000ul
67 #define IOC_IOPT_CacheInvd_IOPTE_Mask	0x000003fffffffff8ul
68 #define IOC_IOPT_CacheInvd_Busy		0x0000000000000001ul
69 
70 #define IOC_IOST_Origin			0x918
71 #define IOC_IOST_Origin_E		0x8000000000000000ul
72 #define IOC_IOST_Origin_HW		0x0000000000000800ul
73 #define IOC_IOST_Origin_HL		0x0000000000000400ul
74 
75 #define IOC_IO_ExcpStat			0x920
76 #define IOC_IO_ExcpStat_V		0x8000000000000000ul
77 #define IOC_IO_ExcpStat_SPF_Mask	0x6000000000000000ul
78 #define IOC_IO_ExcpStat_SPF_S		0x6000000000000000ul
79 #define IOC_IO_ExcpStat_SPF_P		0x2000000000000000ul
80 #define IOC_IO_ExcpStat_ADDR_Mask	0x00000007fffff000ul
81 #define IOC_IO_ExcpStat_RW_Mask		0x0000000000000800ul
82 #define IOC_IO_ExcpStat_IOID_Mask	0x00000000000007fful
83 
84 #define IOC_IO_ExcpMask			0x928
85 #define IOC_IO_ExcpMask_SFE		0x4000000000000000ul
86 #define IOC_IO_ExcpMask_PFE		0x2000000000000000ul
87 
88 #define IOC_IOCmd_Offset		0x1000
89 
90 #define IOC_IOCmd_Cfg			0xc00
91 #define IOC_IOCmd_Cfg_TE		0x0000800000000000ul
92 
93 
94 /* Segment table entries */
95 #define IOSTE_V			0x8000000000000000ul /* valid */
96 #define IOSTE_H			0x4000000000000000ul /* cache hint */
97 #define IOSTE_PT_Base_RPN_Mask  0x3ffffffffffff000ul /* base RPN of IOPT */
98 #define IOSTE_NPPT_Mask		0x0000000000000fe0ul /* no. pages in IOPT */
99 #define IOSTE_PS_Mask		0x0000000000000007ul /* page size */
100 #define IOSTE_PS_4K		0x0000000000000001ul /*   - 4kB  */
101 #define IOSTE_PS_64K		0x0000000000000003ul /*   - 64kB */
102 #define IOSTE_PS_1M		0x0000000000000005ul /*   - 1MB  */
103 #define IOSTE_PS_16M		0x0000000000000007ul /*   - 16MB */
104 
105 
106 /* IOMMU sizing */
107 #define IO_SEGMENT_SHIFT	28
108 #define IO_PAGENO_BITS(shift)	(IO_SEGMENT_SHIFT - (shift))
109 
110 /* The high bit needs to be set on every DMA address */
111 #define SPIDER_DMA_OFFSET	0x80000000ul
112 
113 struct iommu_window {
114 	struct list_head list;
115 	struct cbe_iommu *iommu;
116 	unsigned long offset;
117 	unsigned long size;
118 	unsigned int ioid;
119 	struct iommu_table table;
120 };
121 
122 #define NAMESIZE 8
123 struct cbe_iommu {
124 	int nid;
125 	char name[NAMESIZE];
126 	void __iomem *xlate_regs;
127 	void __iomem *cmd_regs;
128 	unsigned long *stab;
129 	unsigned long *ptab;
130 	void *pad_page;
131 	struct list_head windows;
132 };
133 
134 /* Static array of iommus, one per node
135  *   each contains a list of windows, keyed from dma_window property
136  *   - on bus setup, look for a matching window, or create one
137  *   - on dev setup, assign iommu_table ptr
138  */
139 static struct cbe_iommu iommus[NR_IOMMUS];
140 static int cbe_nr_iommus;
141 
142 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
143 		long n_ptes)
144 {
145 	u64 __iomem *reg;
146 	u64 val;
147 	long n;
148 
149 	reg = iommu->xlate_regs + IOC_IOPT_CacheInvd;
150 
151 	while (n_ptes > 0) {
152 		/* we can invalidate up to 1 << 11 PTEs at once */
153 		n = min(n_ptes, 1l << 11);
154 		val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask)
155 			| (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask)
156 		        | IOC_IOPT_CacheInvd_Busy;
157 
158 		out_be64(reg, val);
159 		while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
160 			;
161 
162 		n_ptes -= n;
163 		pte += n;
164 	}
165 }
166 
167 static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
168 		unsigned long uaddr, enum dma_data_direction direction,
169 		unsigned long attrs)
170 {
171 	int i;
172 	unsigned long *io_pte, base_pte;
173 	struct iommu_window *window =
174 		container_of(tbl, struct iommu_window, table);
175 
176 	/* implementing proper protection causes problems with the spidernet
177 	 * driver - check mapping directions later, but allow read & write by
178 	 * default for now.*/
179 #ifdef CELL_IOMMU_STRICT_PROTECTION
180 	/* to avoid referencing a global, we use a trick here to setup the
181 	 * protection bit. "prot" is setup to be 3 fields of 4 bits appended
182 	 * together for each of the 3 supported direction values. It is then
183 	 * shifted left so that the fields matching the desired direction
184 	 * lands on the appropriate bits, and other bits are masked out.
185 	 */
186 	const unsigned long prot = 0xc48;
187 	base_pte =
188 		((prot << (52 + 4 * direction)) &
189 		 (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) |
190 		CBE_IOPTE_M | CBE_IOPTE_SO_RW |
191 		(window->ioid & CBE_IOPTE_IOID_Mask);
192 #else
193 	base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
194 		CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask);
195 #endif
196 	if (unlikely(attrs & DMA_ATTR_WEAK_ORDERING))
197 		base_pte &= ~CBE_IOPTE_SO_RW;
198 
199 	io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
200 
201 	for (i = 0; i < npages; i++, uaddr += (1 << tbl->it_page_shift))
202 		io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
203 
204 	mb();
205 
206 	invalidate_tce_cache(window->iommu, io_pte, npages);
207 
208 	pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n",
209 		 index, npages, direction, base_pte);
210 	return 0;
211 }
212 
213 static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
214 {
215 
216 	int i;
217 	unsigned long *io_pte, pte;
218 	struct iommu_window *window =
219 		container_of(tbl, struct iommu_window, table);
220 
221 	pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages);
222 
223 #ifdef CELL_IOMMU_REAL_UNMAP
224 	pte = 0;
225 #else
226 	/* spider bridge does PCI reads after freeing - insert a mapping
227 	 * to a scratch page instead of an invalid entry */
228 	pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW |
229 		__pa(window->iommu->pad_page) |
230 		(window->ioid & CBE_IOPTE_IOID_Mask);
231 #endif
232 
233 	io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
234 
235 	for (i = 0; i < npages; i++)
236 		io_pte[i] = pte;
237 
238 	mb();
239 
240 	invalidate_tce_cache(window->iommu, io_pte, npages);
241 }
242 
243 static irqreturn_t ioc_interrupt(int irq, void *data)
244 {
245 	unsigned long stat, spf;
246 	struct cbe_iommu *iommu = data;
247 
248 	stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
249 	spf = stat & IOC_IO_ExcpStat_SPF_Mask;
250 
251 	/* Might want to rate limit it */
252 	printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat);
253 	printk(KERN_ERR "  V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n",
254 	       !!(stat & IOC_IO_ExcpStat_V),
255 	       (spf == IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ',
256 	       (spf == IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ',
257 	       (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write",
258 	       (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask));
259 	printk(KERN_ERR "  page=0x%016lx\n",
260 	       stat & IOC_IO_ExcpStat_ADDR_Mask);
261 
262 	/* clear interrupt */
263 	stat &= ~IOC_IO_ExcpStat_V;
264 	out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
265 
266 	return IRQ_HANDLED;
267 }
268 
269 static int cell_iommu_find_ioc(int nid, unsigned long *base)
270 {
271 	struct device_node *np;
272 	struct resource r;
273 
274 	*base = 0;
275 
276 	/* First look for new style /be nodes */
277 	for_each_node_by_name(np, "ioc") {
278 		if (of_node_to_nid(np) != nid)
279 			continue;
280 		if (of_address_to_resource(np, 0, &r)) {
281 			printk(KERN_ERR "iommu: can't get address for %pOF\n",
282 			       np);
283 			continue;
284 		}
285 		*base = r.start;
286 		of_node_put(np);
287 		return 0;
288 	}
289 
290 	/* Ok, let's try the old way */
291 	for_each_node_by_type(np, "cpu") {
292 		const unsigned int *nidp;
293 		const unsigned long *tmp;
294 
295 		nidp = of_get_property(np, "node-id", NULL);
296 		if (nidp && *nidp == nid) {
297 			tmp = of_get_property(np, "ioc-translation", NULL);
298 			if (tmp) {
299 				*base = *tmp;
300 				of_node_put(np);
301 				return 0;
302 			}
303 		}
304 	}
305 
306 	return -ENODEV;
307 }
308 
309 static void cell_iommu_setup_stab(struct cbe_iommu *iommu,
310 				unsigned long dbase, unsigned long dsize,
311 				unsigned long fbase, unsigned long fsize)
312 {
313 	struct page *page;
314 	unsigned long segments, stab_size;
315 
316 	segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
317 
318 	pr_debug("%s: iommu[%d]: segments: %lu\n",
319 			__func__, iommu->nid, segments);
320 
321 	/* set up the segment table */
322 	stab_size = segments * sizeof(unsigned long);
323 	page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size));
324 	BUG_ON(!page);
325 	iommu->stab = page_address(page);
326 	memset(iommu->stab, 0, stab_size);
327 }
328 
329 static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
330 		unsigned long base, unsigned long size, unsigned long gap_base,
331 		unsigned long gap_size, unsigned long page_shift)
332 {
333 	struct page *page;
334 	int i;
335 	unsigned long reg, segments, pages_per_segment, ptab_size,
336 		      n_pte_pages, start_seg, *ptab;
337 
338 	start_seg = base >> IO_SEGMENT_SHIFT;
339 	segments  = size >> IO_SEGMENT_SHIFT;
340 	pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift);
341 	/* PTEs for each segment must start on a 4K boundary */
342 	pages_per_segment = max(pages_per_segment,
343 				(1 << 12) / sizeof(unsigned long));
344 
345 	ptab_size = segments * pages_per_segment * sizeof(unsigned long);
346 	pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__,
347 			iommu->nid, ptab_size, get_order(ptab_size));
348 	page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
349 	BUG_ON(!page);
350 
351 	ptab = page_address(page);
352 	memset(ptab, 0, ptab_size);
353 
354 	/* number of 4K pages needed for a page table */
355 	n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
356 
357 	pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
358 			__func__, iommu->nid, iommu->stab, ptab,
359 			n_pte_pages);
360 
361 	/* initialise the STEs */
362 	reg = IOSTE_V | ((n_pte_pages - 1) << 5);
363 
364 	switch (page_shift) {
365 	case 12: reg |= IOSTE_PS_4K;  break;
366 	case 16: reg |= IOSTE_PS_64K; break;
367 	case 20: reg |= IOSTE_PS_1M;  break;
368 	case 24: reg |= IOSTE_PS_16M; break;
369 	default: BUG();
370 	}
371 
372 	gap_base = gap_base >> IO_SEGMENT_SHIFT;
373 	gap_size = gap_size >> IO_SEGMENT_SHIFT;
374 
375 	pr_debug("Setting up IOMMU stab:\n");
376 	for (i = start_seg; i < (start_seg + segments); i++) {
377 		if (i >= gap_base && i < (gap_base + gap_size)) {
378 			pr_debug("\toverlap at %d, skipping\n", i);
379 			continue;
380 		}
381 		iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) *
382 					(i - start_seg));
383 		pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
384 	}
385 
386 	return ptab;
387 }
388 
389 static void cell_iommu_enable_hardware(struct cbe_iommu *iommu)
390 {
391 	int ret;
392 	unsigned long reg, xlate_base;
393 	unsigned int virq;
394 
395 	if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
396 		panic("%s: missing IOC register mappings for node %d\n",
397 		      __func__, iommu->nid);
398 
399 	iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
400 	iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
401 
402 	/* ensure that the STEs have updated */
403 	mb();
404 
405 	/* setup interrupts for the iommu. */
406 	reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
407 	out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
408 			reg & ~IOC_IO_ExcpStat_V);
409 	out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
410 			IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE);
411 
412 	virq = irq_create_mapping(NULL,
413 			IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT));
414 	BUG_ON(!virq);
415 
416 	ret = request_irq(virq, ioc_interrupt, 0, iommu->name, iommu);
417 	BUG_ON(ret);
418 
419 	/* set the IOC segment table origin register (and turn on the iommu) */
420 	reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW;
421 	out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
422 	in_be64(iommu->xlate_regs + IOC_IOST_Origin);
423 
424 	/* turn on IO translation */
425 	reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
426 	out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
427 }
428 
429 static void cell_iommu_setup_hardware(struct cbe_iommu *iommu,
430 	unsigned long base, unsigned long size)
431 {
432 	cell_iommu_setup_stab(iommu, base, size, 0, 0);
433 	iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0,
434 					    IOMMU_PAGE_SHIFT_4K);
435 	cell_iommu_enable_hardware(iommu);
436 }
437 
438 #if 0/* Unused for now */
439 static struct iommu_window *find_window(struct cbe_iommu *iommu,
440 		unsigned long offset, unsigned long size)
441 {
442 	struct iommu_window *window;
443 
444 	/* todo: check for overlapping (but not equal) windows) */
445 
446 	list_for_each_entry(window, &(iommu->windows), list) {
447 		if (window->offset == offset && window->size == size)
448 			return window;
449 	}
450 
451 	return NULL;
452 }
453 #endif
454 
455 static inline u32 cell_iommu_get_ioid(struct device_node *np)
456 {
457 	const u32 *ioid;
458 
459 	ioid = of_get_property(np, "ioid", NULL);
460 	if (ioid == NULL) {
461 		printk(KERN_WARNING "iommu: missing ioid for %pOF using 0\n",
462 		       np);
463 		return 0;
464 	}
465 
466 	return *ioid;
467 }
468 
469 static struct iommu_table_ops cell_iommu_ops = {
470 	.set = tce_build_cell,
471 	.clear = tce_free_cell
472 };
473 
474 static struct iommu_window * __init
475 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
476 			unsigned long offset, unsigned long size,
477 			unsigned long pte_offset)
478 {
479 	struct iommu_window *window;
480 	struct page *page;
481 	u32 ioid;
482 
483 	ioid = cell_iommu_get_ioid(np);
484 
485 	window = kzalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid);
486 	BUG_ON(window == NULL);
487 
488 	window->offset = offset;
489 	window->size = size;
490 	window->ioid = ioid;
491 	window->iommu = iommu;
492 
493 	window->table.it_blocksize = 16;
494 	window->table.it_base = (unsigned long)iommu->ptab;
495 	window->table.it_index = iommu->nid;
496 	window->table.it_page_shift = IOMMU_PAGE_SHIFT_4K;
497 	window->table.it_offset =
498 		(offset >> window->table.it_page_shift) + pte_offset;
499 	window->table.it_size = size >> window->table.it_page_shift;
500 	window->table.it_ops = &cell_iommu_ops;
501 
502 	iommu_init_table(&window->table, iommu->nid);
503 
504 	pr_debug("\tioid      %d\n", window->ioid);
505 	pr_debug("\tblocksize %ld\n", window->table.it_blocksize);
506 	pr_debug("\tbase      0x%016lx\n", window->table.it_base);
507 	pr_debug("\toffset    0x%lx\n", window->table.it_offset);
508 	pr_debug("\tsize      %ld\n", window->table.it_size);
509 
510 	list_add(&window->list, &iommu->windows);
511 
512 	if (offset != 0)
513 		return window;
514 
515 	/* We need to map and reserve the first IOMMU page since it's used
516 	 * by the spider workaround. In theory, we only need to do that when
517 	 * running on spider but it doesn't really matter.
518 	 *
519 	 * This code also assumes that we have a window that starts at 0,
520 	 * which is the case on all spider based blades.
521 	 */
522 	page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
523 	BUG_ON(!page);
524 	iommu->pad_page = page_address(page);
525 	clear_page(iommu->pad_page);
526 
527 	__set_bit(0, window->table.it_map);
528 	tce_build_cell(&window->table, window->table.it_offset, 1,
529 		       (unsigned long)iommu->pad_page, DMA_TO_DEVICE, 0);
530 
531 	return window;
532 }
533 
534 static struct cbe_iommu *cell_iommu_for_node(int nid)
535 {
536 	int i;
537 
538 	for (i = 0; i < cbe_nr_iommus; i++)
539 		if (iommus[i].nid == nid)
540 			return &iommus[i];
541 	return NULL;
542 }
543 
544 static unsigned long cell_dma_nommu_offset;
545 
546 static unsigned long dma_iommu_fixed_base;
547 static bool cell_iommu_enabled;
548 
549 /* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */
550 bool iommu_fixed_is_weak;
551 
552 static struct iommu_table *cell_get_iommu_table(struct device *dev)
553 {
554 	struct iommu_window *window;
555 	struct cbe_iommu *iommu;
556 
557 	/* Current implementation uses the first window available in that
558 	 * node's iommu. We -might- do something smarter later though it may
559 	 * never be necessary
560 	 */
561 	iommu = cell_iommu_for_node(dev_to_node(dev));
562 	if (iommu == NULL || list_empty(&iommu->windows)) {
563 		dev_err(dev, "iommu: missing iommu for %pOF (node %d)\n",
564 		       dev->of_node, dev_to_node(dev));
565 		return NULL;
566 	}
567 	window = list_entry(iommu->windows.next, struct iommu_window, list);
568 
569 	return &window->table;
570 }
571 
572 static u64 cell_iommu_get_fixed_address(struct device *dev);
573 
574 static void cell_dma_dev_setup(struct device *dev)
575 {
576 	if (cell_iommu_enabled) {
577 		u64 addr = cell_iommu_get_fixed_address(dev);
578 
579 		if (addr != OF_BAD_ADDR)
580 			dev->archdata.dma_offset = addr + dma_iommu_fixed_base;
581 		set_iommu_table_base(dev, cell_get_iommu_table(dev));
582 	} else {
583 		dev->archdata.dma_offset = cell_dma_nommu_offset;
584 	}
585 }
586 
587 static void cell_pci_dma_dev_setup(struct pci_dev *dev)
588 {
589 	cell_dma_dev_setup(&dev->dev);
590 }
591 
592 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action,
593 			      void *data)
594 {
595 	struct device *dev = data;
596 
597 	/* We are only intereted in device addition */
598 	if (action != BUS_NOTIFY_ADD_DEVICE)
599 		return 0;
600 
601 	if (cell_iommu_enabled)
602 		dev->dma_ops = &dma_iommu_ops;
603 	cell_dma_dev_setup(dev);
604 	return 0;
605 }
606 
607 static struct notifier_block cell_of_bus_notifier = {
608 	.notifier_call = cell_of_bus_notify
609 };
610 
611 static int __init cell_iommu_get_window(struct device_node *np,
612 					 unsigned long *base,
613 					 unsigned long *size)
614 {
615 	const __be32 *dma_window;
616 	unsigned long index;
617 
618 	/* Use ibm,dma-window if available, else, hard code ! */
619 	dma_window = of_get_property(np, "ibm,dma-window", NULL);
620 	if (dma_window == NULL) {
621 		*base = 0;
622 		*size = 0x80000000u;
623 		return -ENODEV;
624 	}
625 
626 	of_parse_dma_window(np, dma_window, &index, base, size);
627 	return 0;
628 }
629 
630 static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np)
631 {
632 	struct cbe_iommu *iommu;
633 	int nid, i;
634 
635 	/* Get node ID */
636 	nid = of_node_to_nid(np);
637 	if (nid < 0) {
638 		printk(KERN_ERR "iommu: failed to get node for %pOF\n",
639 		       np);
640 		return NULL;
641 	}
642 	pr_debug("iommu: setting up iommu for node %d (%pOF)\n",
643 		 nid, np);
644 
645 	/* XXX todo: If we can have multiple windows on the same IOMMU, which
646 	 * isn't the case today, we probably want here to check whether the
647 	 * iommu for that node is already setup.
648 	 * However, there might be issue with getting the size right so let's
649 	 * ignore that for now. We might want to completely get rid of the
650 	 * multiple window support since the cell iommu supports per-page ioids
651 	 */
652 
653 	if (cbe_nr_iommus >= NR_IOMMUS) {
654 		printk(KERN_ERR "iommu: too many IOMMUs detected ! (%pOF)\n",
655 		       np);
656 		return NULL;
657 	}
658 
659 	/* Init base fields */
660 	i = cbe_nr_iommus++;
661 	iommu = &iommus[i];
662 	iommu->stab = NULL;
663 	iommu->nid = nid;
664 	snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i);
665 	INIT_LIST_HEAD(&iommu->windows);
666 
667 	return iommu;
668 }
669 
670 static void __init cell_iommu_init_one(struct device_node *np,
671 				       unsigned long offset)
672 {
673 	struct cbe_iommu *iommu;
674 	unsigned long base, size;
675 
676 	iommu = cell_iommu_alloc(np);
677 	if (!iommu)
678 		return;
679 
680 	/* Obtain a window for it */
681 	cell_iommu_get_window(np, &base, &size);
682 
683 	pr_debug("\ttranslating window 0x%lx...0x%lx\n",
684 		 base, base + size - 1);
685 
686 	/* Initialize the hardware */
687 	cell_iommu_setup_hardware(iommu, base, size);
688 
689 	/* Setup the iommu_table */
690 	cell_iommu_setup_window(iommu, np, base, size,
691 				offset >> IOMMU_PAGE_SHIFT_4K);
692 }
693 
694 static void __init cell_disable_iommus(void)
695 {
696 	int node;
697 	unsigned long base, val;
698 	void __iomem *xregs, *cregs;
699 
700 	/* Make sure IOC translation is disabled on all nodes */
701 	for_each_online_node(node) {
702 		if (cell_iommu_find_ioc(node, &base))
703 			continue;
704 		xregs = ioremap(base, IOC_Reg_Size);
705 		if (xregs == NULL)
706 			continue;
707 		cregs = xregs + IOC_IOCmd_Offset;
708 
709 		pr_debug("iommu: cleaning up iommu on node %d\n", node);
710 
711 		out_be64(xregs + IOC_IOST_Origin, 0);
712 		(void)in_be64(xregs + IOC_IOST_Origin);
713 		val = in_be64(cregs + IOC_IOCmd_Cfg);
714 		val &= ~IOC_IOCmd_Cfg_TE;
715 		out_be64(cregs + IOC_IOCmd_Cfg, val);
716 		(void)in_be64(cregs + IOC_IOCmd_Cfg);
717 
718 		iounmap(xregs);
719 	}
720 }
721 
722 static int __init cell_iommu_init_disabled(void)
723 {
724 	struct device_node *np = NULL;
725 	unsigned long base = 0, size;
726 
727 	/* When no iommu is present, we use direct DMA ops */
728 
729 	/* First make sure all IOC translation is turned off */
730 	cell_disable_iommus();
731 
732 	/* If we have no Axon, we set up the spider DMA magic offset */
733 	if (of_find_node_by_name(NULL, "axon") == NULL)
734 		cell_dma_nommu_offset = SPIDER_DMA_OFFSET;
735 
736 	/* Now we need to check to see where the memory is mapped
737 	 * in PCI space. We assume that all busses use the same dma
738 	 * window which is always the case so far on Cell, thus we
739 	 * pick up the first pci-internal node we can find and check
740 	 * the DMA window from there.
741 	 */
742 	for_each_node_by_name(np, "axon") {
743 		if (np->parent == NULL || np->parent->parent != NULL)
744 			continue;
745 		if (cell_iommu_get_window(np, &base, &size) == 0)
746 			break;
747 	}
748 	if (np == NULL) {
749 		for_each_node_by_name(np, "pci-internal") {
750 			if (np->parent == NULL || np->parent->parent != NULL)
751 				continue;
752 			if (cell_iommu_get_window(np, &base, &size) == 0)
753 				break;
754 		}
755 	}
756 	of_node_put(np);
757 
758 	/* If we found a DMA window, we check if it's big enough to enclose
759 	 * all of physical memory. If not, we force enable IOMMU
760 	 */
761 	if (np && size < memblock_end_of_DRAM()) {
762 		printk(KERN_WARNING "iommu: force-enabled, dma window"
763 		       " (%ldMB) smaller than total memory (%lldMB)\n",
764 		       size >> 20, memblock_end_of_DRAM() >> 20);
765 		return -ENODEV;
766 	}
767 
768 	cell_dma_nommu_offset += base;
769 
770 	if (cell_dma_nommu_offset != 0)
771 		cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
772 
773 	printk("iommu: disabled, direct DMA offset is 0x%lx\n",
774 	       cell_dma_nommu_offset);
775 
776 	return 0;
777 }
778 
779 /*
780  *  Fixed IOMMU mapping support
781  *
782  *  This code adds support for setting up a fixed IOMMU mapping on certain
783  *  cell machines. For 64-bit devices this avoids the performance overhead of
784  *  mapping and unmapping pages at runtime. 32-bit devices are unable to use
785  *  the fixed mapping.
786  *
787  *  The fixed mapping is established at boot, and maps all of physical memory
788  *  1:1 into device space at some offset. On machines with < 30 GB of memory
789  *  we setup the fixed mapping immediately above the normal IOMMU window.
790  *
791  *  For example a machine with 4GB of memory would end up with the normal
792  *  IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In
793  *  this case a 64-bit device wishing to DMA to 1GB would be told to DMA to
794  *  3GB, plus any offset required by firmware. The firmware offset is encoded
795  *  in the "dma-ranges" property.
796  *
797  *  On machines with 30GB or more of memory, we are unable to place the fixed
798  *  mapping above the normal IOMMU window as we would run out of address space.
799  *  Instead we move the normal IOMMU window to coincide with the hash page
800  *  table, this region does not need to be part of the fixed mapping as no
801  *  device should ever be DMA'ing to it. We then setup the fixed mapping
802  *  from 0 to 32GB.
803  */
804 
805 static u64 cell_iommu_get_fixed_address(struct device *dev)
806 {
807 	u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR;
808 	struct device_node *np;
809 	const u32 *ranges = NULL;
810 	int i, len, best, naddr, nsize, pna, range_size;
811 
812 	/* We can be called for platform devices that have no of_node */
813 	np = of_node_get(dev->of_node);
814 	if (!np)
815 		goto out;
816 
817 	while (1) {
818 		naddr = of_n_addr_cells(np);
819 		nsize = of_n_size_cells(np);
820 		np = of_get_next_parent(np);
821 		if (!np)
822 			break;
823 
824 		ranges = of_get_property(np, "dma-ranges", &len);
825 
826 		/* Ignore empty ranges, they imply no translation required */
827 		if (ranges && len > 0)
828 			break;
829 	}
830 
831 	if (!ranges) {
832 		dev_dbg(dev, "iommu: no dma-ranges found\n");
833 		goto out;
834 	}
835 
836 	len /= sizeof(u32);
837 
838 	pna = of_n_addr_cells(np);
839 	range_size = naddr + nsize + pna;
840 
841 	/* dma-ranges format:
842 	 * child addr	: naddr cells
843 	 * parent addr	: pna cells
844 	 * size		: nsize cells
845 	 */
846 	for (i = 0, best = -1, best_size = 0; i < len; i += range_size) {
847 		cpu_addr = of_translate_dma_address(np, ranges + i + naddr);
848 		size = of_read_number(ranges + i + naddr + pna, nsize);
849 
850 		if (cpu_addr == 0 && size > best_size) {
851 			best = i;
852 			best_size = size;
853 		}
854 	}
855 
856 	if (best >= 0) {
857 		dev_addr = of_read_number(ranges + best, naddr);
858 	} else
859 		dev_dbg(dev, "iommu: no suitable range found!\n");
860 
861 out:
862 	of_node_put(np);
863 
864 	return dev_addr;
865 }
866 
867 static bool cell_pci_iommu_bypass_supported(struct pci_dev *pdev, u64 mask)
868 {
869 	return mask == DMA_BIT_MASK(64) &&
870 		cell_iommu_get_fixed_address(&pdev->dev) != OF_BAD_ADDR;
871 }
872 
873 static void insert_16M_pte(unsigned long addr, unsigned long *ptab,
874 			   unsigned long base_pte)
875 {
876 	unsigned long segment, offset;
877 
878 	segment = addr >> IO_SEGMENT_SHIFT;
879 	offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24));
880 	ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long));
881 
882 	pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
883 		  addr, ptab, segment, offset);
884 
885 	ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask);
886 }
887 
888 static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
889 	struct device_node *np, unsigned long dbase, unsigned long dsize,
890 	unsigned long fbase, unsigned long fsize)
891 {
892 	unsigned long base_pte, uaddr, ioaddr, *ptab;
893 
894 	ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24);
895 
896 	dma_iommu_fixed_base = fbase;
897 
898 	pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
899 
900 	base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
901 		(cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask);
902 
903 	if (iommu_fixed_is_weak)
904 		pr_info("IOMMU: Using weak ordering for fixed mapping\n");
905 	else {
906 		pr_info("IOMMU: Using strong ordering for fixed mapping\n");
907 		base_pte |= CBE_IOPTE_SO_RW;
908 	}
909 
910 	for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
911 		/* Don't touch the dynamic region */
912 		ioaddr = uaddr + fbase;
913 		if (ioaddr >= dbase && ioaddr < (dbase + dsize)) {
914 			pr_debug("iommu: fixed/dynamic overlap, skipping\n");
915 			continue;
916 		}
917 
918 		insert_16M_pte(uaddr, ptab, base_pte);
919 	}
920 
921 	mb();
922 }
923 
924 static int __init cell_iommu_fixed_mapping_init(void)
925 {
926 	unsigned long dbase, dsize, fbase, fsize, hbase, hend;
927 	struct cbe_iommu *iommu;
928 	struct device_node *np;
929 
930 	/* The fixed mapping is only supported on axon machines */
931 	np = of_find_node_by_name(NULL, "axon");
932 	of_node_put(np);
933 
934 	if (!np) {
935 		pr_debug("iommu: fixed mapping disabled, no axons found\n");
936 		return -1;
937 	}
938 
939 	/* We must have dma-ranges properties for fixed mapping to work */
940 	np = of_find_node_with_property(NULL, "dma-ranges");
941 	of_node_put(np);
942 
943 	if (!np) {
944 		pr_debug("iommu: no dma-ranges found, no fixed mapping\n");
945 		return -1;
946 	}
947 
948 	/* The default setup is to have the fixed mapping sit after the
949 	 * dynamic region, so find the top of the largest IOMMU window
950 	 * on any axon, then add the size of RAM and that's our max value.
951 	 * If that is > 32GB we have to do other shennanigans.
952 	 */
953 	fbase = 0;
954 	for_each_node_by_name(np, "axon") {
955 		cell_iommu_get_window(np, &dbase, &dsize);
956 		fbase = max(fbase, dbase + dsize);
957 	}
958 
959 	fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT);
960 	fsize = memblock_phys_mem_size();
961 
962 	if ((fbase + fsize) <= 0x800000000ul)
963 		hbase = 0; /* use the device tree window */
964 	else {
965 		/* If we're over 32 GB we need to cheat. We can't map all of
966 		 * RAM with the fixed mapping, and also fit the dynamic
967 		 * region. So try to place the dynamic region where the hash
968 		 * table sits, drivers never need to DMA to it, we don't
969 		 * need a fixed mapping for that area.
970 		 */
971 		if (!htab_address) {
972 			pr_debug("iommu: htab is NULL, on LPAR? Huh?\n");
973 			return -1;
974 		}
975 		hbase = __pa(htab_address);
976 		hend  = hbase + htab_size_bytes;
977 
978 		/* The window must start and end on a segment boundary */
979 		if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) ||
980 		    (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) {
981 			pr_debug("iommu: hash window not segment aligned\n");
982 			return -1;
983 		}
984 
985 		/* Check the hash window fits inside the real DMA window */
986 		for_each_node_by_name(np, "axon") {
987 			cell_iommu_get_window(np, &dbase, &dsize);
988 
989 			if (hbase < dbase || (hend > (dbase + dsize))) {
990 				pr_debug("iommu: hash window doesn't fit in"
991 					 "real DMA window\n");
992 				return -1;
993 			}
994 		}
995 
996 		fbase = 0;
997 	}
998 
999 	/* Setup the dynamic regions */
1000 	for_each_node_by_name(np, "axon") {
1001 		iommu = cell_iommu_alloc(np);
1002 		BUG_ON(!iommu);
1003 
1004 		if (hbase == 0)
1005 			cell_iommu_get_window(np, &dbase, &dsize);
1006 		else {
1007 			dbase = hbase;
1008 			dsize = htab_size_bytes;
1009 		}
1010 
1011 		printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx "
1012 			"fixed window 0x%lx-0x%lx\n", iommu->nid, dbase,
1013 			 dbase + dsize, fbase, fbase + fsize);
1014 
1015 		cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize);
1016 		iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0,
1017 						    IOMMU_PAGE_SHIFT_4K);
1018 		cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize,
1019 					     fbase, fsize);
1020 		cell_iommu_enable_hardware(iommu);
1021 		cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
1022 	}
1023 
1024 	cell_pci_controller_ops.iommu_bypass_supported =
1025 		cell_pci_iommu_bypass_supported;
1026 	return 0;
1027 }
1028 
1029 static int iommu_fixed_disabled;
1030 
1031 static int __init setup_iommu_fixed(char *str)
1032 {
1033 	struct device_node *pciep;
1034 
1035 	if (strcmp(str, "off") == 0)
1036 		iommu_fixed_disabled = 1;
1037 
1038 	/* If we can find a pcie-endpoint in the device tree assume that
1039 	 * we're on a triblade or a CAB so by default the fixed mapping
1040 	 * should be set to be weakly ordered; but only if the boot
1041 	 * option WASN'T set for strong ordering
1042 	 */
1043 	pciep = of_find_node_by_type(NULL, "pcie-endpoint");
1044 
1045 	if (strcmp(str, "weak") == 0 || (pciep && strcmp(str, "strong") != 0))
1046 		iommu_fixed_is_weak = true;
1047 
1048 	of_node_put(pciep);
1049 
1050 	return 1;
1051 }
1052 __setup("iommu_fixed=", setup_iommu_fixed);
1053 
1054 static int __init cell_iommu_init(void)
1055 {
1056 	struct device_node *np;
1057 
1058 	/* If IOMMU is disabled or we have little enough RAM to not need
1059 	 * to enable it, we setup a direct mapping.
1060 	 *
1061 	 * Note: should we make sure we have the IOMMU actually disabled ?
1062 	 */
1063 	if (iommu_is_off ||
1064 	    (!iommu_force_on && memblock_end_of_DRAM() <= 0x80000000ull))
1065 		if (cell_iommu_init_disabled() == 0)
1066 			goto bail;
1067 
1068 	/* Setup various callbacks */
1069 	cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
1070 
1071 	if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0)
1072 		goto done;
1073 
1074 	/* Create an iommu for each /axon node.  */
1075 	for_each_node_by_name(np, "axon") {
1076 		if (np->parent == NULL || np->parent->parent != NULL)
1077 			continue;
1078 		cell_iommu_init_one(np, 0);
1079 	}
1080 
1081 	/* Create an iommu for each toplevel /pci-internal node for
1082 	 * old hardware/firmware
1083 	 */
1084 	for_each_node_by_name(np, "pci-internal") {
1085 		if (np->parent == NULL || np->parent->parent != NULL)
1086 			continue;
1087 		cell_iommu_init_one(np, SPIDER_DMA_OFFSET);
1088 	}
1089  done:
1090 	/* Setup default PCI iommu ops */
1091 	set_pci_dma_ops(&dma_iommu_ops);
1092 	cell_iommu_enabled = true;
1093  bail:
1094 	/* Register callbacks on OF platform device addition/removal
1095 	 * to handle linking them to the right DMA operations
1096 	 */
1097 	bus_register_notifier(&platform_bus_type, &cell_of_bus_notifier);
1098 
1099 	return 0;
1100 }
1101 machine_arch_initcall(cell, cell_iommu_init);
1102