1config PPC_CELL 2 bool 3 default n 4 5config PPC_CELL_COMMON 6 bool 7 select PPC_CELL 8 select PPC_DCR_MMIO 9 select PPC_INDIRECT_PIO 10 select PPC_INDIRECT_MMIO 11 select PPC_NATIVE 12 select PPC_RTAS 13 select IRQ_EDGE_EOI_HANDLER 14 15config PPC_CELL_NATIVE 16 bool 17 select PPC_CELL_COMMON 18 select MPIC 19 select PPC_IO_WORKAROUNDS 20 select IBM_EMAC_EMAC4 21 select IBM_EMAC_RGMII 22 select IBM_EMAC_ZMII #test only 23 select IBM_EMAC_TAH #test only 24 default n 25 26config PPC_IBM_CELL_BLADE 27 bool "IBM Cell Blade" 28 depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN 29 select PPC_CELL_NATIVE 30 select PPC_OF_PLATFORM_PCI 31 select PCI 32 select MMIO_NVRAM 33 select PPC_UDBG_16550 34 select UDBG_RTAS_CONSOLE 35 36config PPC_CELL_QPACE 37 bool "IBM Cell - QPACE" 38 depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN 39 select PPC_CELL_COMMON 40 41config AXON_MSI 42 bool 43 depends on PPC_IBM_CELL_BLADE && PCI_MSI 44 default y 45 46menu "Cell Broadband Engine options" 47 depends on PPC_CELL 48 49config SPU_FS 50 tristate "SPU file system" 51 default m 52 depends on PPC_CELL 53 select SPU_BASE 54 select MEMORY_HOTPLUG 55 help 56 The SPU file system is used to access Synergistic Processing 57 Units on machines implementing the Broadband Processor 58 Architecture. 59 60config SPU_BASE 61 bool 62 default n 63 select PPC_COPRO_BASE 64 65config CBE_RAS 66 bool "RAS features for bare metal Cell BE" 67 depends on PPC_CELL_NATIVE 68 default y 69 70config PPC_IBM_CELL_RESETBUTTON 71 bool "IBM Cell Blade Pinhole reset button" 72 depends on CBE_RAS && PPC_IBM_CELL_BLADE 73 default y 74 help 75 Support Pinhole Resetbutton on IBM Cell blades. 76 This adds a method to trigger system reset via front panel pinhole button. 77 78config PPC_IBM_CELL_POWERBUTTON 79 tristate "IBM Cell Blade power button" 80 depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV 81 default y 82 help 83 Support Powerbutton on IBM Cell blades. 84 This will enable the powerbutton as an input device. 85 86config CBE_THERM 87 tristate "CBE thermal support" 88 default m 89 depends on CBE_RAS && SPU_BASE 90 91config PPC_PMI 92 tristate 93 default y 94 depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON 95 help 96 PMI (Platform Management Interrupt) is a way to 97 communicate with the BMC (Baseboard Management Controller). 98 It is used in some IBM Cell blades. 99 100config CBE_CPUFREQ_SPU_GOVERNOR 101 tristate "CBE frequency scaling based on SPU usage" 102 depends on SPU_FS && CPU_FREQ 103 default m 104 help 105 This governor checks for spu usage to adjust the cpu frequency. 106 If no spu is running on a given cpu, that cpu will be throttled to 107 the minimal possible frequency. 108 109endmenu 110 111config OPROFILE_CELL 112 def_bool y 113 depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE 114 115