1config PPC_CELL 2 bool 3 default n 4 5config PPC_CELL_COMMON 6 bool 7 select PPC_CELL 8 select PPC_DCR_MMIO 9 select PPC_INDIRECT_PIO 10 select PPC_INDIRECT_MMIO 11 select PPC_NATIVE 12 select PPC_RTAS 13 select IRQ_EDGE_EOI_HANDLER 14 15config PPC_CELL_NATIVE 16 bool 17 select PPC_CELL_COMMON 18 select MPIC 19 select PPC_IO_WORKAROUNDS 20 select IBM_EMAC_EMAC4 21 select IBM_EMAC_RGMII 22 select IBM_EMAC_ZMII #test only 23 select IBM_EMAC_TAH #test only 24 default n 25 26config PPC_IBM_CELL_BLADE 27 bool "IBM Cell Blade" 28 depends on PPC64 && PPC_BOOK3S 29 select PPC_CELL_NATIVE 30 select PPC_OF_PLATFORM_PCI 31 select PCI 32 select MMIO_NVRAM 33 select PPC_UDBG_16550 34 select UDBG_RTAS_CONSOLE 35 36config PPC_CELL_QPACE 37 bool "IBM Cell - QPACE" 38 depends on PPC64 && PPC_BOOK3S 39 select PPC_CELL_COMMON 40 41config AXON_MSI 42 bool 43 depends on PPC_IBM_CELL_BLADE && PCI_MSI 44 default y 45 46menu "Cell Broadband Engine options" 47 depends on PPC_CELL 48 49config SPU_FS 50 tristate "SPU file system" 51 default m 52 depends on PPC_CELL 53 select SPU_BASE 54 select MEMORY_HOTPLUG 55 help 56 The SPU file system is used to access Synergistic Processing 57 Units on machines implementing the Broadband Processor 58 Architecture. 59 60config SPU_FS_64K_LS 61 bool "Use 64K pages to map SPE local store" 62 # we depend on PPC_MM_SLICES for now rather than selecting 63 # it because we depend on hugetlbfs hooks being present. We 64 # will fix that when the generic code has been improved to 65 # not require hijacking hugetlbfs hooks. 66 depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES 67 default y 68 select PPC_HAS_HASH_64K 69 help 70 This option causes SPE local stores to be mapped in process 71 address spaces using 64K pages while the rest of the kernel 72 uses 4K pages. This can improve performances of applications 73 using multiple SPEs by lowering the TLB pressure on them. 74 75config SPU_BASE 76 bool 77 default n 78 select PPC_COPRO_BASE 79 80config CBE_RAS 81 bool "RAS features for bare metal Cell BE" 82 depends on PPC_CELL_NATIVE 83 default y 84 85config PPC_IBM_CELL_RESETBUTTON 86 bool "IBM Cell Blade Pinhole reset button" 87 depends on CBE_RAS && PPC_IBM_CELL_BLADE 88 default y 89 help 90 Support Pinhole Resetbutton on IBM Cell blades. 91 This adds a method to trigger system reset via front panel pinhole button. 92 93config PPC_IBM_CELL_POWERBUTTON 94 tristate "IBM Cell Blade power button" 95 depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV 96 default y 97 help 98 Support Powerbutton on IBM Cell blades. 99 This will enable the powerbutton as an input device. 100 101config CBE_THERM 102 tristate "CBE thermal support" 103 default m 104 depends on CBE_RAS && SPU_BASE 105 106config PPC_PMI 107 tristate 108 default y 109 depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON 110 help 111 PMI (Platform Management Interrupt) is a way to 112 communicate with the BMC (Baseboard Management Controller). 113 It is used in some IBM Cell blades. 114 115config CBE_CPUFREQ_SPU_GOVERNOR 116 tristate "CBE frequency scaling based on SPU usage" 117 depends on SPU_FS && CPU_FREQ 118 default m 119 help 120 This governor checks for spu usage to adjust the cpu frequency. 121 If no spu is running on a given cpu, that cpu will be throttled to 122 the minimal possible frequency. 123 124endmenu 125 126config OPROFILE_CELL 127 def_bool y 128 depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE 129 130