1# SPDX-License-Identifier: GPL-2.0 2config PPC_CELL 3 bool 4 5config PPC_CELL_COMMON 6 bool 7 select PPC_CELL 8 select PPC_DCR_MMIO 9 select PPC_INDIRECT_PIO 10 select PPC_INDIRECT_MMIO 11 select PPC_NATIVE 12 select PPC_RTAS 13 select IRQ_EDGE_EOI_HANDLER 14 15config PPC_CELL_NATIVE 16 bool 17 select PPC_CELL_COMMON 18 select MPIC 19 select PPC_IO_WORKAROUNDS 20 select IBM_EMAC_EMAC4 if IBM_EMAC 21 select IBM_EMAC_RGMII if IBM_EMAC 22 select IBM_EMAC_ZMII if IBM_EMAC #test only 23 select IBM_EMAC_TAH if IBM_EMAC #test only 24 25config PPC_IBM_CELL_BLADE 26 bool "IBM Cell Blade" 27 depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN 28 select PPC_CELL_NATIVE 29 select PPC_OF_PLATFORM_PCI 30 select FORCE_PCI 31 select MMIO_NVRAM 32 select PPC_UDBG_16550 33 select UDBG_RTAS_CONSOLE 34 35config AXON_MSI 36 bool 37 depends on PPC_IBM_CELL_BLADE && PCI_MSI 38 default y 39 40menu "Cell Broadband Engine options" 41 depends on PPC_CELL 42 43config SPU_FS 44 tristate "SPU file system" 45 default m 46 depends on PPC_CELL 47 depends on COREDUMP 48 select SPU_BASE 49 help 50 The SPU file system is used to access Synergistic Processing 51 Units on machines implementing the Broadband Processor 52 Architecture. 53 54config SPU_BASE 55 bool 56 select PPC_COPRO_BASE 57 58config CBE_RAS 59 bool "RAS features for bare metal Cell BE" 60 depends on PPC_CELL_NATIVE 61 default y 62 63config PPC_IBM_CELL_RESETBUTTON 64 bool "IBM Cell Blade Pinhole reset button" 65 depends on CBE_RAS && PPC_IBM_CELL_BLADE 66 default y 67 help 68 Support Pinhole Resetbutton on IBM Cell blades. 69 This adds a method to trigger system reset via front panel pinhole button. 70 71config PPC_IBM_CELL_POWERBUTTON 72 tristate "IBM Cell Blade power button" 73 depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV 74 default y 75 help 76 Support Powerbutton on IBM Cell blades. 77 This will enable the powerbutton as an input device. 78 79config CBE_THERM 80 tristate "CBE thermal support" 81 default m 82 depends on CBE_RAS && SPU_BASE 83 84config PPC_PMI 85 tristate 86 default y 87 depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON 88 help 89 PMI (Platform Management Interrupt) is a way to 90 communicate with the BMC (Baseboard Management Controller). 91 It is used in some IBM Cell blades. 92 93config CBE_CPUFREQ_SPU_GOVERNOR 94 tristate "CBE frequency scaling based on SPU usage" 95 depends on SPU_FS && CPU_FREQ 96 default m 97 help 98 This governor checks for spu usage to adjust the cpu frequency. 99 If no spu is running on a given cpu, that cpu will be throttled to 100 the minimal possible frequency. 101 102endmenu 103