1config PPC_CELL 2 bool 3 default n 4 5config PPC_CELL_COMMON 6 bool 7 select PPC_CELL 8 select PPC_DCR_MMIO 9 select PPC_INDIRECT_IO 10 select PPC_NATIVE 11 select PPC_RTAS 12 13config PPC_CELL_NATIVE 14 bool 15 select PPC_CELL_COMMON 16 select MPIC 17 select IBM_NEW_EMAC_EMAC4 18 select IBM_NEW_EMAC_RGMII 19 select IBM_NEW_EMAC_ZMII #test only 20 select IBM_NEW_EMAC_TAH #test only 21 default n 22 23config PPC_IBM_CELL_BLADE 24 bool "IBM Cell Blade" 25 depends on PPC64 && PPC_BOOK3S 26 select PPC_CELL_NATIVE 27 select PPC_OF_PLATFORM_PCI 28 select PCI 29 select MMIO_NVRAM 30 select PPC_UDBG_16550 31 select UDBG_RTAS_CONSOLE 32 33config PPC_CELLEB 34 bool "Toshiba's Cell Reference Set 'Celleb' Architecture" 35 depends on PPC64 && PPC_BOOK3S 36 select PPC_CELL_NATIVE 37 select PPC_OF_PLATFORM_PCI 38 select PCI 39 select HAS_TXX9_SERIAL 40 select PPC_UDBG_BEAT 41 select USB_OHCI_BIG_ENDIAN_MMIO 42 select USB_EHCI_BIG_ENDIAN_MMIO 43 44config PPC_CELL_QPACE 45 bool "IBM Cell - QPACE" 46 depends on PPC64 && PPC_BOOK3S 47 select PPC_CELL_COMMON 48 49config AXON_MSI 50 bool 51 depends on PPC_IBM_CELL_BLADE && PCI_MSI 52 default y 53 54menu "Cell Broadband Engine options" 55 depends on PPC_CELL 56 57config SPU_FS 58 tristate "SPU file system" 59 default m 60 depends on PPC_CELL 61 select SPU_BASE 62 select MEMORY_HOTPLUG 63 help 64 The SPU file system is used to access Synergistic Processing 65 Units on machines implementing the Broadband Processor 66 Architecture. 67 68config SPU_FS_64K_LS 69 bool "Use 64K pages to map SPE local store" 70 # we depend on PPC_MM_SLICES for now rather than selecting 71 # it because we depend on hugetlbfs hooks being present. We 72 # will fix that when the generic code has been improved to 73 # not require hijacking hugetlbfs hooks. 74 depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES 75 default y 76 select PPC_HAS_HASH_64K 77 help 78 This option causes SPE local stores to be mapped in process 79 address spaces using 64K pages while the rest of the kernel 80 uses 4K pages. This can improve performances of applications 81 using multiple SPEs by lowering the TLB pressure on them. 82 83config SPU_BASE 84 bool 85 default n 86 87config CBE_RAS 88 bool "RAS features for bare metal Cell BE" 89 depends on PPC_CELL_NATIVE 90 default y 91 92config PPC_IBM_CELL_RESETBUTTON 93 bool "IBM Cell Blade Pinhole reset button" 94 depends on CBE_RAS && PPC_IBM_CELL_BLADE 95 default y 96 help 97 Support Pinhole Resetbutton on IBM Cell blades. 98 This adds a method to trigger system reset via front panel pinhole button. 99 100config PPC_IBM_CELL_POWERBUTTON 101 tristate "IBM Cell Blade power button" 102 depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV 103 default y 104 help 105 Support Powerbutton on IBM Cell blades. 106 This will enable the powerbutton as an input device. 107 108config CBE_THERM 109 tristate "CBE thermal support" 110 default m 111 depends on CBE_RAS && SPU_BASE 112 113config CBE_CPUFREQ 114 tristate "CBE frequency scaling" 115 depends on CBE_RAS && CPU_FREQ 116 default m 117 help 118 This adds the cpufreq driver for Cell BE processors. 119 For details, take a look at <file:Documentation/cpu-freq/>. 120 If you don't have such processor, say N 121 122config CBE_CPUFREQ_PMI_ENABLE 123 bool "CBE frequency scaling using PMI interface" 124 depends on CBE_CPUFREQ && EXPERIMENTAL 125 default n 126 help 127 Select this, if you want to use the PMI interface 128 to switch frequencies. Using PMI, the 129 processor will not only be able to run at lower speed, 130 but also at lower core voltage. 131 132config CBE_CPUFREQ_PMI 133 tristate 134 depends on CBE_CPUFREQ_PMI_ENABLE 135 default CBE_CPUFREQ 136 137config PPC_PMI 138 tristate 139 default y 140 depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON 141 help 142 PMI (Platform Management Interrupt) is a way to 143 communicate with the BMC (Baseboard Management Controller). 144 It is used in some IBM Cell blades. 145 146config CBE_CPUFREQ_SPU_GOVERNOR 147 tristate "CBE frequency scaling based on SPU usage" 148 depends on SPU_FS && CPU_FREQ 149 default m 150 help 151 This governor checks for spu usage to adjust the cpu frequency. 152 If no spu is running on a given cpu, that cpu will be throttled to 153 the minimal possible frequency. 154 155endmenu 156 157config OPROFILE_CELL 158 def_bool y 159 depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE 160 161