1menu "Platform support" 2 3source "arch/powerpc/platforms/powernv/Kconfig" 4source "arch/powerpc/platforms/pseries/Kconfig" 5source "arch/powerpc/platforms/chrp/Kconfig" 6source "arch/powerpc/platforms/512x/Kconfig" 7source "arch/powerpc/platforms/52xx/Kconfig" 8source "arch/powerpc/platforms/powermac/Kconfig" 9source "arch/powerpc/platforms/maple/Kconfig" 10source "arch/powerpc/platforms/pasemi/Kconfig" 11source "arch/powerpc/platforms/ps3/Kconfig" 12source "arch/powerpc/platforms/cell/Kconfig" 13source "arch/powerpc/platforms/8xx/Kconfig" 14source "arch/powerpc/platforms/82xx/Kconfig" 15source "arch/powerpc/platforms/83xx/Kconfig" 16source "arch/powerpc/platforms/85xx/Kconfig" 17source "arch/powerpc/platforms/86xx/Kconfig" 18source "arch/powerpc/platforms/embedded6xx/Kconfig" 19source "arch/powerpc/platforms/44x/Kconfig" 20source "arch/powerpc/platforms/40x/Kconfig" 21source "arch/powerpc/platforms/amigaone/Kconfig" 22source "arch/powerpc/platforms/wsp/Kconfig" 23 24config KVM_GUEST 25 bool "KVM Guest support" 26 default n 27 select EPAPR_PARAVIRT 28 ---help--- 29 This option enables various optimizations for running under the KVM 30 hypervisor. Overhead for the kernel when not running inside KVM should 31 be minimal. 32 33 In case of doubt, say Y 34 35config EPAPR_PARAVIRT 36 bool "ePAPR para-virtualization support" 37 default n 38 help 39 Enables ePAPR para-virtualization support for guests. 40 41 In case of doubt, say Y 42 43config PPC_NATIVE 44 bool 45 depends on 6xx || PPC64 46 help 47 Support for running natively on the hardware, i.e. without 48 a hypervisor. This option is not user-selectable but should 49 be selected by all platforms that need it. 50 51config PPC_OF_BOOT_TRAMPOLINE 52 bool "Support booting from Open Firmware or yaboot" 53 depends on 6xx || PPC64 54 default y 55 help 56 Support from booting from Open Firmware or yaboot using an 57 Open Firmware client interface. This enables the kernel to 58 communicate with open firmware to retrieve system information 59 such as the device tree. 60 61 In case of doubt, say Y 62 63config UDBG_RTAS_CONSOLE 64 bool "RTAS based debug console" 65 depends on PPC_RTAS 66 default n 67 68config PPC_SMP_MUXED_IPI 69 bool 70 help 71 Select this opton if your platform supports SMP and your 72 interrupt controller provides less than 4 interrupts to each 73 cpu. This will enable the generic code to multiplex the 4 74 messages on to one ipi. 75 76config PPC_UDBG_BEAT 77 bool "BEAT based debug console" 78 depends on PPC_CELLEB 79 default n 80 81config IPIC 82 bool 83 default n 84 85config MPIC 86 bool 87 default n 88 89config MPIC_TIMER 90 bool "MPIC Global Timer" 91 depends on MPIC && FSL_SOC 92 default n 93 help 94 The MPIC global timer is a hardware timer inside the 95 Freescale PIC complying with OpenPIC standard. When the 96 specified interval times out, the hardware timer generates 97 an interrupt. The driver currently is only tested on fsl 98 chip, but it can potentially support other global timers 99 complying with the OpenPIC standard. 100 101config FSL_MPIC_TIMER_WAKEUP 102 tristate "Freescale MPIC global timer wakeup driver" 103 depends on FSL_SOC && MPIC_TIMER && PM 104 default n 105 help 106 The driver provides a way to wake up the system by MPIC 107 timer. 108 e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup" 109 110config PPC_EPAPR_HV_PIC 111 bool 112 default n 113 select EPAPR_PARAVIRT 114 115config MPIC_WEIRD 116 bool 117 default n 118 119config MPIC_MSGR 120 bool "MPIC message register support" 121 depends on MPIC 122 default n 123 help 124 Enables support for the MPIC message registers. These 125 registers are used for inter-processor communication. 126 127config PPC_I8259 128 bool 129 default n 130 131config U3_DART 132 bool 133 depends on PPC64 134 default n 135 136config PPC_RTAS 137 bool 138 default n 139 140config RTAS_ERROR_LOGGING 141 bool 142 depends on PPC_RTAS 143 default n 144 145config PPC_RTAS_DAEMON 146 bool 147 depends on PPC_RTAS 148 default n 149 150config RTAS_PROC 151 bool "Proc interface to RTAS" 152 depends on PPC_RTAS && PROC_FS 153 default y 154 155config RTAS_FLASH 156 tristate "Firmware flash interface" 157 depends on PPC64 && RTAS_PROC 158 159config MMIO_NVRAM 160 bool 161 default n 162 163config MPIC_U3_HT_IRQS 164 bool 165 default n 166 167config MPIC_BROKEN_REGREAD 168 bool 169 depends on MPIC 170 help 171 This option enables a MPIC driver workaround for some chips 172 that have a bug that causes some interrupt source information 173 to not read back properly. It is safe to use on other chips as 174 well, but enabling it uses about 8KB of memory to keep copies 175 of the register contents in software. 176 177config IBMVIO 178 depends on PPC_PSERIES 179 bool 180 default y 181 182config IBMEBUS 183 depends on PPC_PSERIES 184 bool "Support for GX bus based adapters" 185 help 186 Bus device driver for GX bus based adapters. 187 188config EEH 189 bool 190 depends on (PPC_POWERNV || PPC_PSERIES) && PCI 191 default y 192 193config PPC_MPC106 194 bool 195 default n 196 197config PPC_970_NAP 198 bool 199 default n 200 201config PPC_P7_NAP 202 bool 203 default n 204 205config PPC_INDIRECT_PIO 206 bool 207 select GENERIC_IOMAP 208 209config PPC_INDIRECT_MMIO 210 bool 211 212config PPC_IO_WORKAROUNDS 213 bool 214 215source "drivers/cpufreq/Kconfig" 216 217menu "CPUIdle driver" 218 219source "drivers/cpuidle/Kconfig" 220 221endmenu 222 223config PPC601_SYNC_FIX 224 bool "Workarounds for PPC601 bugs" 225 depends on 6xx && PPC_PMAC 226 help 227 Some versions of the PPC601 (the first PowerPC chip) have bugs which 228 mean that extra synchronization instructions are required near 229 certain instructions, typically those that make major changes to the 230 CPU state. These extra instructions reduce performance slightly. 231 If you say N here, these extra instructions will not be included, 232 resulting in a kernel which will run faster but may not run at all 233 on some systems with the PPC601 chip. 234 235 If in doubt, say Y here. 236 237config TAU 238 bool "On-chip CPU temperature sensor support" 239 depends on 6xx 240 help 241 G3 and G4 processors have an on-chip temperature sensor called the 242 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die 243 temperature within 2-4 degrees Celsius. This option shows the current 244 on-die temperature in /proc/cpuinfo if the cpu supports it. 245 246 Unfortunately, on some chip revisions, this sensor is very inaccurate 247 and in many cases, does not work at all, so don't assume the cpu 248 temp is actually what /proc/cpuinfo says it is. 249 250config TAU_INT 251 bool "Interrupt driven TAU driver (DANGEROUS)" 252 depends on TAU 253 ---help--- 254 The TAU supports an interrupt driven mode which causes an interrupt 255 whenever the temperature goes out of range. This is the fastest way 256 to get notified the temp has exceeded a range. With this option off, 257 a timer is used to re-check the temperature periodically. 258 259 However, on some cpus it appears that the TAU interrupt hardware 260 is buggy and can cause a situation which would lead unexplained hard 261 lockups. 262 263 Unless you are extending the TAU driver, or enjoy kernel/hardware 264 debugging, leave this option off. 265 266config TAU_AVERAGE 267 bool "Average high and low temp" 268 depends on TAU 269 ---help--- 270 The TAU hardware can compare the temperature to an upper and lower 271 bound. The default behavior is to show both the upper and lower 272 bound in /proc/cpuinfo. If the range is large, the temperature is 273 either changing a lot, or the TAU hardware is broken (likely on some 274 G4's). If the range is small (around 4 degrees), the temperature is 275 relatively stable. If you say Y here, a single temperature value, 276 halfway between the upper and lower bounds, will be reported in 277 /proc/cpuinfo. 278 279 If in doubt, say N here. 280 281config QUICC_ENGINE 282 bool "Freescale QUICC Engine (QE) Support" 283 depends on FSL_SOC && PPC32 284 select PPC_LIB_RHEAP 285 select CRC32 286 help 287 The QUICC Engine (QE) is a new generation of communications 288 coprocessors on Freescale embedded CPUs (akin to CPM in older chips). 289 Selecting this option means that you wish to build a kernel 290 for a machine with a QE coprocessor. 291 292config QE_GPIO 293 bool "QE GPIO support" 294 depends on QUICC_ENGINE 295 select ARCH_REQUIRE_GPIOLIB 296 help 297 Say Y here if you're going to use hardware that connects to the 298 QE GPIOs. 299 300config CPM2 301 bool "Enable support for the CPM2 (Communications Processor Module)" 302 depends on (FSL_SOC_BOOKE && PPC32) || 8260 303 select CPM 304 select PPC_LIB_RHEAP 305 select PPC_PCI_CHOICE 306 select ARCH_REQUIRE_GPIOLIB 307 help 308 The CPM2 (Communications Processor Module) is a coprocessor on 309 embedded CPUs made by Freescale. Selecting this option means that 310 you wish to build a kernel for a machine with a CPM2 coprocessor 311 on it (826x, 827x, 8560). 312 313config AXON_RAM 314 tristate "Axon DDR2 memory device driver" 315 depends on PPC_IBM_CELL_BLADE && BLOCK 316 default m 317 help 318 It registers one block device per Axon's DDR2 memory bank found 319 on a system. Block devices are called axonram?, their major and 320 minor numbers are available in /proc/devices, /proc/partitions or 321 in /sys/block/axonram?/dev. 322 323config FSL_ULI1575 324 bool 325 default n 326 select GENERIC_ISA_DMA 327 help 328 Supports for the ULI1575 PCIe south bridge that exists on some 329 Freescale reference boards. The boards all use the ULI in pretty 330 much the same way. 331 332config CPM 333 bool 334 335config OF_RTC 336 bool 337 help 338 Uses information from the OF or flattened device tree to instantiate 339 platform devices for direct mapped RTC chips like the DS1742 or DS1743. 340 341config SIMPLE_GPIO 342 bool "Support for simple, memory-mapped GPIO controllers" 343 depends on PPC 344 select ARCH_REQUIRE_GPIOLIB 345 help 346 Say Y here to support simple, memory-mapped GPIO controllers. 347 These are usually BCSRs used to control board's switches, LEDs, 348 chip-selects, Ethernet/USB PHY's power and various other small 349 on-board peripherals. 350 351config MCU_MPC8349EMITX 352 bool "MPC8349E-mITX MCU driver" 353 depends on I2C=y && PPC_83xx 354 select ARCH_REQUIRE_GPIOLIB 355 help 356 Say Y here to enable soft power-off functionality on the Freescale 357 boards with the MPC8349E-mITX-compatible MCU chips. This driver will 358 also register MCU GPIOs with the generic GPIO API, so you'll able 359 to use MCU pins as GPIOs. 360 361config XILINX_PCI 362 bool "Xilinx PCI host bridge support" 363 depends on PCI && XILINX_VIRTEX 364 365endmenu 366