1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2df34403dSVitaly Bordug /* 3df34403dSVitaly Bordug * Copyright (C) 1995 Linus Torvalds 4df34403dSVitaly Bordug * Adapted from 'alpha' version by Gary Thomas 5df34403dSVitaly Bordug * Modified by Cort Dougan (cort@cs.nmt.edu) 6df34403dSVitaly Bordug * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net) 7df34403dSVitaly Bordug * Further modified for generic 8xx by Dan. 8df34403dSVitaly Bordug */ 9df34403dSVitaly Bordug 10df34403dSVitaly Bordug /* 11df34403dSVitaly Bordug * bootup setup stuff.. 12df34403dSVitaly Bordug */ 13df34403dSVitaly Bordug 14df34403dSVitaly Bordug #include <linux/kernel.h> 15df34403dSVitaly Bordug #include <linux/interrupt.h> 16df34403dSVitaly Bordug #include <linux/init.h> 17df34403dSVitaly Bordug #include <linux/time.h> 18df34403dSVitaly Bordug #include <linux/rtc.h> 1902753cb6SJochen Friedrich #include <linux/fsl_devices.h> 20*e6f6390aSChristophe Leroy #include <linux/of.h> 21*e6f6390aSChristophe Leroy #include <linux/of_irq.h> 22df34403dSVitaly Bordug 23df34403dSVitaly Bordug #include <asm/io.h> 24df34403dSVitaly Bordug #include <asm/8xx_immap.h> 25df34403dSVitaly Bordug #include <asm/fs_pd.h> 26df34403dSVitaly Bordug #include <mm/mmu_decl.h> 27df34403dSVitaly Bordug 28de41ef6eSChristophe Leroy #include "pic.h" 2949b51545SJochen Friedrich 3049b51545SJochen Friedrich #include "mpc8xx.h" 31df34403dSVitaly Bordug 32df34403dSVitaly Bordug extern int cpm_pic_init(void); 33df34403dSVitaly Bordug extern int cpm_get_irq(void); 34df34403dSVitaly Bordug 35df34403dSVitaly Bordug /* A place holder for time base interrupts, if they are ever enabled. */ 36fb533d0cSScott Wood static irqreturn_t timebase_interrupt(int irq, void *dev) 37df34403dSVitaly Bordug { 38df34403dSVitaly Bordug printk ("timebase_interrupt()\n"); 39df34403dSVitaly Bordug 40df34403dSVitaly Bordug return IRQ_HANDLED; 41df34403dSVitaly Bordug } 42df34403dSVitaly Bordug 43df34403dSVitaly Bordug /* per-board overridable init_internal_rtc() function. */ 44df34403dSVitaly Bordug void __init __attribute__ ((weak)) 45df34403dSVitaly Bordug init_internal_rtc(void) 46df34403dSVitaly Bordug { 47fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr = immr_map(im_sit); 48df34403dSVitaly Bordug 49df34403dSVitaly Bordug /* Disable the RTC one second and alarm interrupts. */ 50df34403dSVitaly Bordug clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); 51df34403dSVitaly Bordug 52df34403dSVitaly Bordug /* Enable the RTC */ 53df34403dSVitaly Bordug setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE)); 54df34403dSVitaly Bordug immr_unmap(sys_tmr); 55df34403dSVitaly Bordug } 56df34403dSVitaly Bordug 57df34403dSVitaly Bordug static int __init get_freq(char *name, unsigned long *val) 58df34403dSVitaly Bordug { 59df34403dSVitaly Bordug struct device_node *cpu; 60e2eb6392SStephen Rothwell const unsigned int *fp; 61df34403dSVitaly Bordug int found = 0; 62df34403dSVitaly Bordug 63df34403dSVitaly Bordug /* The cpu node should have timebase and clock frequency properties */ 6438959a09SRob Herring cpu = of_get_cpu_node(0, NULL); 65df34403dSVitaly Bordug 66df34403dSVitaly Bordug if (cpu) { 67e2eb6392SStephen Rothwell fp = of_get_property(cpu, name, NULL); 68df34403dSVitaly Bordug if (fp) { 69df34403dSVitaly Bordug found = 1; 70e2eb6392SStephen Rothwell *val = *fp; 71df34403dSVitaly Bordug } 72df34403dSVitaly Bordug 73df34403dSVitaly Bordug of_node_put(cpu); 74df34403dSVitaly Bordug } 75df34403dSVitaly Bordug 76df34403dSVitaly Bordug return found; 77df34403dSVitaly Bordug } 78df34403dSVitaly Bordug 79df34403dSVitaly Bordug /* The decrementer counts at the system (internal) clock frequency divided by 80df34403dSVitaly Bordug * sixteen, or external oscillator divided by four. We force the processor 81df34403dSVitaly Bordug * to use system clock divided by sixteen. 82df34403dSVitaly Bordug */ 83df34403dSVitaly Bordug void __init mpc8xx_calibrate_decr(void) 84df34403dSVitaly Bordug { 85df34403dSVitaly Bordug struct device_node *cpu; 86fb533d0cSScott Wood cark8xx_t __iomem *clk_r1; 87fb533d0cSScott Wood car8xx_t __iomem *clk_r2; 88fb533d0cSScott Wood sitk8xx_t __iomem *sys_tmr1; 89fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr2; 90df34403dSVitaly Bordug int irq, virq; 91df34403dSVitaly Bordug 92fb533d0cSScott Wood clk_r1 = immr_map(im_clkrstk); 93df34403dSVitaly Bordug 94df34403dSVitaly Bordug /* Unlock the SCCR. */ 95df34403dSVitaly Bordug out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY); 96df34403dSVitaly Bordug out_be32(&clk_r1->cark_sccrk, KAPWR_KEY); 97df34403dSVitaly Bordug immr_unmap(clk_r1); 98df34403dSVitaly Bordug 99df34403dSVitaly Bordug /* Force all 8xx processors to use divide by 16 processor clock. */ 100fb533d0cSScott Wood clk_r2 = immr_map(im_clkrst); 101df34403dSVitaly Bordug setbits32(&clk_r2->car_sccr, 0x02000000); 102df34403dSVitaly Bordug immr_unmap(clk_r2); 103df34403dSVitaly Bordug 104df34403dSVitaly Bordug /* Processor frequency is MHz. 105df34403dSVitaly Bordug */ 106df34403dSVitaly Bordug ppc_proc_freq = 50000000; 107df34403dSVitaly Bordug if (!get_freq("clock-frequency", &ppc_proc_freq)) 108df34403dSVitaly Bordug printk(KERN_ERR "WARNING: Estimating processor frequency " 109df34403dSVitaly Bordug "(not found)\n"); 110df34403dSVitaly Bordug 11150530378SAnton Vorontsov ppc_tb_freq = ppc_proc_freq / 16; 112df34403dSVitaly Bordug printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); 113df34403dSVitaly Bordug 114df34403dSVitaly Bordug /* Perform some more timer/timebase initialization. This used 115df34403dSVitaly Bordug * to be done elsewhere, but other changes caused it to get 116df34403dSVitaly Bordug * called more than once....that is a bad thing. 117df34403dSVitaly Bordug * 118df34403dSVitaly Bordug * First, unlock all of the registers we are going to modify. 119df34403dSVitaly Bordug * To protect them from corruption during power down, registers 120df34403dSVitaly Bordug * that are maintained by keep alive power are "locked". To 121df34403dSVitaly Bordug * modify these registers we have to write the key value to 122df34403dSVitaly Bordug * the key location associated with the register. 123df34403dSVitaly Bordug * Some boards power up with these unlocked, while others 124df34403dSVitaly Bordug * are locked. Writing anything (including the unlock code?) 125df34403dSVitaly Bordug * to the unlocked registers will lock them again. So, here 126df34403dSVitaly Bordug * we guarantee the registers are locked, then we unlock them 127df34403dSVitaly Bordug * for our use. 128df34403dSVitaly Bordug */ 129fb533d0cSScott Wood sys_tmr1 = immr_map(im_sitk); 130df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY); 131df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY); 132df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY); 133df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY); 134df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY); 135df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY); 136df34403dSVitaly Bordug immr_unmap(sys_tmr1); 137df34403dSVitaly Bordug 138df34403dSVitaly Bordug init_internal_rtc(); 139df34403dSVitaly Bordug 140df34403dSVitaly Bordug /* Enabling the decrementer also enables the timebase interrupts 141df34403dSVitaly Bordug * (or from the other point of view, to get decrementer interrupts 142df34403dSVitaly Bordug * we have to enable the timebase). The decrementer interrupt 143df34403dSVitaly Bordug * is wired into the vector table, nothing to do here for that. 144df34403dSVitaly Bordug */ 14538959a09SRob Herring cpu = of_get_cpu_node(0, NULL); 146df34403dSVitaly Bordug virq= irq_of_parse_and_map(cpu, 0); 14738959a09SRob Herring of_node_put(cpu); 148476eb491SGrant Likely irq = virq_to_hw(virq); 149df34403dSVitaly Bordug 150fb533d0cSScott Wood sys_tmr2 = immr_map(im_sit); 151df34403dSVitaly Bordug out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) | 152df34403dSVitaly Bordug (TBSCR_TBF | TBSCR_TBE)); 153df34403dSVitaly Bordug immr_unmap(sys_tmr2); 154df34403dSVitaly Bordug 155b4f00d5bSafzal mohammed if (request_irq(virq, timebase_interrupt, IRQF_NO_THREAD, "tbint", 156b4f00d5bSafzal mohammed NULL)) 157df34403dSVitaly Bordug panic("Could not allocate timer IRQ!"); 158df34403dSVitaly Bordug } 159df34403dSVitaly Bordug 160df34403dSVitaly Bordug /* The RTC on the MPC8xx is an internal register. 161df34403dSVitaly Bordug * We want to protect this during power down, so we need to unlock, 162df34403dSVitaly Bordug * modify, and re-lock. 163df34403dSVitaly Bordug */ 164df34403dSVitaly Bordug 165df34403dSVitaly Bordug int mpc8xx_set_rtc_time(struct rtc_time *tm) 166df34403dSVitaly Bordug { 167fb533d0cSScott Wood sitk8xx_t __iomem *sys_tmr1; 168fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr2; 1695235afa8SArnd Bergmann time64_t time; 170df34403dSVitaly Bordug 171fb533d0cSScott Wood sys_tmr1 = immr_map(im_sitk); 172fb533d0cSScott Wood sys_tmr2 = immr_map(im_sit); 1735235afa8SArnd Bergmann time = rtc_tm_to_time64(tm); 174df34403dSVitaly Bordug 175df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY); 1765235afa8SArnd Bergmann out_be32(&sys_tmr2->sit_rtc, (u32)time); 177df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY); 178df34403dSVitaly Bordug 179df34403dSVitaly Bordug immr_unmap(sys_tmr2); 180df34403dSVitaly Bordug immr_unmap(sys_tmr1); 181df34403dSVitaly Bordug return 0; 182df34403dSVitaly Bordug } 183df34403dSVitaly Bordug 184df34403dSVitaly Bordug void mpc8xx_get_rtc_time(struct rtc_time *tm) 185df34403dSVitaly Bordug { 186df34403dSVitaly Bordug unsigned long data; 187fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr = immr_map(im_sit); 188df34403dSVitaly Bordug 189df34403dSVitaly Bordug /* Get time from the RTC. */ 190df34403dSVitaly Bordug data = in_be32(&sys_tmr->sit_rtc); 1915bfd6435SArnd Bergmann rtc_time64_to_tm(data, tm); 192df34403dSVitaly Bordug immr_unmap(sys_tmr); 193df34403dSVitaly Bordug return; 194df34403dSVitaly Bordug } 195df34403dSVitaly Bordug 19695ec77c0SDaniel Axtens void __noreturn mpc8xx_restart(char *cmd) 197df34403dSVitaly Bordug { 198fb533d0cSScott Wood car8xx_t __iomem *clk_r = immr_map(im_clkrst); 199df34403dSVitaly Bordug 200df34403dSVitaly Bordug 201df34403dSVitaly Bordug local_irq_disable(); 202df34403dSVitaly Bordug 203df34403dSVitaly Bordug setbits32(&clk_r->car_plprcr, 0x00000080); 204df34403dSVitaly Bordug /* Clear the ME bit in MSR to cause checkstop on machine check 205df34403dSVitaly Bordug */ 206df34403dSVitaly Bordug mtmsr(mfmsr() & ~0x1000); 207df34403dSVitaly Bordug 208fb533d0cSScott Wood in_8(&clk_r->res[0]); 209fb533d0cSScott Wood panic("Restart failed\n"); 210df34403dSVitaly Bordug } 211df34403dSVitaly Bordug 212bd0b9ac4SThomas Gleixner static void cpm_cascade(struct irq_desc *desc) 213df34403dSVitaly Bordug { 214c554ac91SChristophe Leroy generic_handle_irq(cpm_get_irq()); 215df34403dSVitaly Bordug } 216df34403dSVitaly Bordug 217d0a02a06SJochen Friedrich /* Initialize the internal interrupt controllers. The number of 218df34403dSVitaly Bordug * interrupts supported can vary with the processor type, and the 219df34403dSVitaly Bordug * 82xx family can have up to 64. 220df34403dSVitaly Bordug * External interrupts can be either edge or level triggered, and 221df34403dSVitaly Bordug * need to be initialized by the appropriate driver. 222df34403dSVitaly Bordug */ 223d0a02a06SJochen Friedrich void __init mpc8xx_pics_init(void) 224df34403dSVitaly Bordug { 225df34403dSVitaly Bordug int irq; 226df34403dSVitaly Bordug 227df34403dSVitaly Bordug if (mpc8xx_pic_init()) { 228df34403dSVitaly Bordug printk(KERN_ERR "Failed interrupt 8xx controller initialization\n"); 229df34403dSVitaly Bordug return; 230df34403dSVitaly Bordug } 231df34403dSVitaly Bordug 232df34403dSVitaly Bordug irq = cpm_pic_init(); 233ef24ba70SMichael Ellerman if (irq) 234ec775d0eSThomas Gleixner irq_set_chained_handler(irq, cpm_cascade); 235df34403dSVitaly Bordug } 236