1df34403dSVitaly Bordug /* 2df34403dSVitaly Bordug * Copyright (C) 1995 Linus Torvalds 3df34403dSVitaly Bordug * Adapted from 'alpha' version by Gary Thomas 4df34403dSVitaly Bordug * Modified by Cort Dougan (cort@cs.nmt.edu) 5df34403dSVitaly Bordug * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net) 6df34403dSVitaly Bordug * Further modified for generic 8xx by Dan. 7df34403dSVitaly Bordug */ 8df34403dSVitaly Bordug 9df34403dSVitaly Bordug /* 10df34403dSVitaly Bordug * bootup setup stuff.. 11df34403dSVitaly Bordug */ 12df34403dSVitaly Bordug 13df34403dSVitaly Bordug #include <linux/kernel.h> 14df34403dSVitaly Bordug #include <linux/slab.h> 15df34403dSVitaly Bordug #include <linux/interrupt.h> 16df34403dSVitaly Bordug #include <linux/init.h> 17df34403dSVitaly Bordug #include <linux/time.h> 18df34403dSVitaly Bordug #include <linux/rtc.h> 19*02753cb6SJochen Friedrich #include <linux/fsl_devices.h> 20df34403dSVitaly Bordug 21df34403dSVitaly Bordug #include <asm/io.h> 22df34403dSVitaly Bordug #include <asm/mpc8xx.h> 23df34403dSVitaly Bordug #include <asm/8xx_immap.h> 24df34403dSVitaly Bordug #include <asm/prom.h> 25df34403dSVitaly Bordug #include <asm/fs_pd.h> 26df34403dSVitaly Bordug #include <mm/mmu_decl.h> 27df34403dSVitaly Bordug 28fb533d0cSScott Wood #include <sysdev/mpc8xx_pic.h> 2949b51545SJochen Friedrich 3049b51545SJochen Friedrich #include "mpc8xx.h" 31df34403dSVitaly Bordug 3280128ff7SVitaly Bordug struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; 3380128ff7SVitaly Bordug 34df34403dSVitaly Bordug extern int cpm_pic_init(void); 35df34403dSVitaly Bordug extern int cpm_get_irq(void); 36df34403dSVitaly Bordug 37df34403dSVitaly Bordug /* A place holder for time base interrupts, if they are ever enabled. */ 38fb533d0cSScott Wood static irqreturn_t timebase_interrupt(int irq, void *dev) 39df34403dSVitaly Bordug { 40df34403dSVitaly Bordug printk ("timebase_interrupt()\n"); 41df34403dSVitaly Bordug 42df34403dSVitaly Bordug return IRQ_HANDLED; 43df34403dSVitaly Bordug } 44df34403dSVitaly Bordug 45df34403dSVitaly Bordug static struct irqaction tbint_irqaction = { 46df34403dSVitaly Bordug .handler = timebase_interrupt, 47df34403dSVitaly Bordug .mask = CPU_MASK_NONE, 48df34403dSVitaly Bordug .name = "tbint", 49df34403dSVitaly Bordug }; 50df34403dSVitaly Bordug 51df34403dSVitaly Bordug /* per-board overridable init_internal_rtc() function. */ 52df34403dSVitaly Bordug void __init __attribute__ ((weak)) 53df34403dSVitaly Bordug init_internal_rtc(void) 54df34403dSVitaly Bordug { 55fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr = immr_map(im_sit); 56df34403dSVitaly Bordug 57df34403dSVitaly Bordug /* Disable the RTC one second and alarm interrupts. */ 58df34403dSVitaly Bordug clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); 59df34403dSVitaly Bordug 60df34403dSVitaly Bordug /* Enable the RTC */ 61df34403dSVitaly Bordug setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE)); 62df34403dSVitaly Bordug immr_unmap(sys_tmr); 63df34403dSVitaly Bordug } 64df34403dSVitaly Bordug 65df34403dSVitaly Bordug static int __init get_freq(char *name, unsigned long *val) 66df34403dSVitaly Bordug { 67df34403dSVitaly Bordug struct device_node *cpu; 68e2eb6392SStephen Rothwell const unsigned int *fp; 69df34403dSVitaly Bordug int found = 0; 70df34403dSVitaly Bordug 71df34403dSVitaly Bordug /* The cpu node should have timebase and clock frequency properties */ 72df34403dSVitaly Bordug cpu = of_find_node_by_type(NULL, "cpu"); 73df34403dSVitaly Bordug 74df34403dSVitaly Bordug if (cpu) { 75e2eb6392SStephen Rothwell fp = of_get_property(cpu, name, NULL); 76df34403dSVitaly Bordug if (fp) { 77df34403dSVitaly Bordug found = 1; 78e2eb6392SStephen Rothwell *val = *fp; 79df34403dSVitaly Bordug } 80df34403dSVitaly Bordug 81df34403dSVitaly Bordug of_node_put(cpu); 82df34403dSVitaly Bordug } 83df34403dSVitaly Bordug 84df34403dSVitaly Bordug return found; 85df34403dSVitaly Bordug } 86df34403dSVitaly Bordug 87df34403dSVitaly Bordug /* The decrementer counts at the system (internal) clock frequency divided by 88df34403dSVitaly Bordug * sixteen, or external oscillator divided by four. We force the processor 89df34403dSVitaly Bordug * to use system clock divided by sixteen. 90df34403dSVitaly Bordug */ 91df34403dSVitaly Bordug void __init mpc8xx_calibrate_decr(void) 92df34403dSVitaly Bordug { 93df34403dSVitaly Bordug struct device_node *cpu; 94fb533d0cSScott Wood cark8xx_t __iomem *clk_r1; 95fb533d0cSScott Wood car8xx_t __iomem *clk_r2; 96fb533d0cSScott Wood sitk8xx_t __iomem *sys_tmr1; 97fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr2; 98df34403dSVitaly Bordug int irq, virq; 99df34403dSVitaly Bordug 100fb533d0cSScott Wood clk_r1 = immr_map(im_clkrstk); 101df34403dSVitaly Bordug 102df34403dSVitaly Bordug /* Unlock the SCCR. */ 103df34403dSVitaly Bordug out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY); 104df34403dSVitaly Bordug out_be32(&clk_r1->cark_sccrk, KAPWR_KEY); 105df34403dSVitaly Bordug immr_unmap(clk_r1); 106df34403dSVitaly Bordug 107df34403dSVitaly Bordug /* Force all 8xx processors to use divide by 16 processor clock. */ 108fb533d0cSScott Wood clk_r2 = immr_map(im_clkrst); 109df34403dSVitaly Bordug setbits32(&clk_r2->car_sccr, 0x02000000); 110df34403dSVitaly Bordug immr_unmap(clk_r2); 111df34403dSVitaly Bordug 112df34403dSVitaly Bordug /* Processor frequency is MHz. 113df34403dSVitaly Bordug */ 114df34403dSVitaly Bordug ppc_tb_freq = 50000000; 115df34403dSVitaly Bordug if (!get_freq("bus-frequency", &ppc_tb_freq)) { 116df34403dSVitaly Bordug printk(KERN_ERR "WARNING: Estimating decrementer frequency " 117df34403dSVitaly Bordug "(not found)\n"); 118df34403dSVitaly Bordug } 119df34403dSVitaly Bordug ppc_tb_freq /= 16; 120df34403dSVitaly Bordug ppc_proc_freq = 50000000; 121df34403dSVitaly Bordug if (!get_freq("clock-frequency", &ppc_proc_freq)) 122df34403dSVitaly Bordug printk(KERN_ERR "WARNING: Estimating processor frequency " 123df34403dSVitaly Bordug "(not found)\n"); 124df34403dSVitaly Bordug 125df34403dSVitaly Bordug printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); 126df34403dSVitaly Bordug 127df34403dSVitaly Bordug /* Perform some more timer/timebase initialization. This used 128df34403dSVitaly Bordug * to be done elsewhere, but other changes caused it to get 129df34403dSVitaly Bordug * called more than once....that is a bad thing. 130df34403dSVitaly Bordug * 131df34403dSVitaly Bordug * First, unlock all of the registers we are going to modify. 132df34403dSVitaly Bordug * To protect them from corruption during power down, registers 133df34403dSVitaly Bordug * that are maintained by keep alive power are "locked". To 134df34403dSVitaly Bordug * modify these registers we have to write the key value to 135df34403dSVitaly Bordug * the key location associated with the register. 136df34403dSVitaly Bordug * Some boards power up with these unlocked, while others 137df34403dSVitaly Bordug * are locked. Writing anything (including the unlock code?) 138df34403dSVitaly Bordug * to the unlocked registers will lock them again. So, here 139df34403dSVitaly Bordug * we guarantee the registers are locked, then we unlock them 140df34403dSVitaly Bordug * for our use. 141df34403dSVitaly Bordug */ 142fb533d0cSScott Wood sys_tmr1 = immr_map(im_sitk); 143df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY); 144df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY); 145df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY); 146df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY); 147df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY); 148df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY); 149df34403dSVitaly Bordug immr_unmap(sys_tmr1); 150df34403dSVitaly Bordug 151df34403dSVitaly Bordug init_internal_rtc(); 152df34403dSVitaly Bordug 153df34403dSVitaly Bordug /* Enabling the decrementer also enables the timebase interrupts 154df34403dSVitaly Bordug * (or from the other point of view, to get decrementer interrupts 155df34403dSVitaly Bordug * we have to enable the timebase). The decrementer interrupt 156df34403dSVitaly Bordug * is wired into the vector table, nothing to do here for that. 157df34403dSVitaly Bordug */ 158df34403dSVitaly Bordug cpu = of_find_node_by_type(NULL, "cpu"); 159df34403dSVitaly Bordug virq= irq_of_parse_and_map(cpu, 0); 160df34403dSVitaly Bordug irq = irq_map[virq].hwirq; 161df34403dSVitaly Bordug 162fb533d0cSScott Wood sys_tmr2 = immr_map(im_sit); 163df34403dSVitaly Bordug out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) | 164df34403dSVitaly Bordug (TBSCR_TBF | TBSCR_TBE)); 165df34403dSVitaly Bordug immr_unmap(sys_tmr2); 166df34403dSVitaly Bordug 167df34403dSVitaly Bordug if (setup_irq(virq, &tbint_irqaction)) 168df34403dSVitaly Bordug panic("Could not allocate timer IRQ!"); 169df34403dSVitaly Bordug } 170df34403dSVitaly Bordug 171df34403dSVitaly Bordug /* The RTC on the MPC8xx is an internal register. 172df34403dSVitaly Bordug * We want to protect this during power down, so we need to unlock, 173df34403dSVitaly Bordug * modify, and re-lock. 174df34403dSVitaly Bordug */ 175df34403dSVitaly Bordug 176df34403dSVitaly Bordug int mpc8xx_set_rtc_time(struct rtc_time *tm) 177df34403dSVitaly Bordug { 178fb533d0cSScott Wood sitk8xx_t __iomem *sys_tmr1; 179fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr2; 180df34403dSVitaly Bordug int time; 181df34403dSVitaly Bordug 182fb533d0cSScott Wood sys_tmr1 = immr_map(im_sitk); 183fb533d0cSScott Wood sys_tmr2 = immr_map(im_sit); 184df34403dSVitaly Bordug time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, 185df34403dSVitaly Bordug tm->tm_hour, tm->tm_min, tm->tm_sec); 186df34403dSVitaly Bordug 187df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY); 188df34403dSVitaly Bordug out_be32(&sys_tmr2->sit_rtc, time); 189df34403dSVitaly Bordug out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY); 190df34403dSVitaly Bordug 191df34403dSVitaly Bordug immr_unmap(sys_tmr2); 192df34403dSVitaly Bordug immr_unmap(sys_tmr1); 193df34403dSVitaly Bordug return 0; 194df34403dSVitaly Bordug } 195df34403dSVitaly Bordug 196df34403dSVitaly Bordug void mpc8xx_get_rtc_time(struct rtc_time *tm) 197df34403dSVitaly Bordug { 198df34403dSVitaly Bordug unsigned long data; 199fb533d0cSScott Wood sit8xx_t __iomem *sys_tmr = immr_map(im_sit); 200df34403dSVitaly Bordug 201df34403dSVitaly Bordug /* Get time from the RTC. */ 202df34403dSVitaly Bordug data = in_be32(&sys_tmr->sit_rtc); 203df34403dSVitaly Bordug to_tm(data, tm); 204df34403dSVitaly Bordug tm->tm_year -= 1900; 205df34403dSVitaly Bordug tm->tm_mon -= 1; 206df34403dSVitaly Bordug immr_unmap(sys_tmr); 207df34403dSVitaly Bordug return; 208df34403dSVitaly Bordug } 209df34403dSVitaly Bordug 210df34403dSVitaly Bordug void mpc8xx_restart(char *cmd) 211df34403dSVitaly Bordug { 212fb533d0cSScott Wood car8xx_t __iomem *clk_r = immr_map(im_clkrst); 213df34403dSVitaly Bordug 214df34403dSVitaly Bordug 215df34403dSVitaly Bordug local_irq_disable(); 216df34403dSVitaly Bordug 217df34403dSVitaly Bordug setbits32(&clk_r->car_plprcr, 0x00000080); 218df34403dSVitaly Bordug /* Clear the ME bit in MSR to cause checkstop on machine check 219df34403dSVitaly Bordug */ 220df34403dSVitaly Bordug mtmsr(mfmsr() & ~0x1000); 221df34403dSVitaly Bordug 222fb533d0cSScott Wood in_8(&clk_r->res[0]); 223fb533d0cSScott Wood panic("Restart failed\n"); 224df34403dSVitaly Bordug } 225df34403dSVitaly Bordug 226df34403dSVitaly Bordug static void cpm_cascade(unsigned int irq, struct irq_desc *desc) 227df34403dSVitaly Bordug { 228df34403dSVitaly Bordug int cascade_irq; 229df34403dSVitaly Bordug 230df34403dSVitaly Bordug if ((cascade_irq = cpm_get_irq()) >= 0) { 231df34403dSVitaly Bordug struct irq_desc *cdesc = irq_desc + cascade_irq; 232df34403dSVitaly Bordug 233df34403dSVitaly Bordug generic_handle_irq(cascade_irq); 234df34403dSVitaly Bordug cdesc->chip->eoi(cascade_irq); 235df34403dSVitaly Bordug } 236df34403dSVitaly Bordug desc->chip->eoi(irq); 237df34403dSVitaly Bordug } 238df34403dSVitaly Bordug 239d0a02a06SJochen Friedrich /* Initialize the internal interrupt controllers. The number of 240df34403dSVitaly Bordug * interrupts supported can vary with the processor type, and the 241df34403dSVitaly Bordug * 82xx family can have up to 64. 242df34403dSVitaly Bordug * External interrupts can be either edge or level triggered, and 243df34403dSVitaly Bordug * need to be initialized by the appropriate driver. 244df34403dSVitaly Bordug */ 245d0a02a06SJochen Friedrich void __init mpc8xx_pics_init(void) 246df34403dSVitaly Bordug { 247df34403dSVitaly Bordug int irq; 248df34403dSVitaly Bordug 249df34403dSVitaly Bordug if (mpc8xx_pic_init()) { 250df34403dSVitaly Bordug printk(KERN_ERR "Failed interrupt 8xx controller initialization\n"); 251df34403dSVitaly Bordug return; 252df34403dSVitaly Bordug } 253df34403dSVitaly Bordug 254df34403dSVitaly Bordug irq = cpm_pic_init(); 255df34403dSVitaly Bordug if (irq != NO_IRQ) 256df34403dSVitaly Bordug set_irq_chained_handler(irq, cpm_cascade); 257df34403dSVitaly Bordug } 258