12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
28a6be2bdSXie Xiaobo /*
38a6be2bdSXie Xiaobo * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
48a6be2bdSXie Xiaobo *
58a6be2bdSXie Xiaobo * Author: Michael Johnston <michael.johnston@freescale.com>
68a6be2bdSXie Xiaobo *
78a6be2bdSXie Xiaobo * Description:
88a6be2bdSXie Xiaobo * TWR-P102x Board Setup
98a6be2bdSXie Xiaobo */
108a6be2bdSXie Xiaobo
118a6be2bdSXie Xiaobo #include <linux/kernel.h>
128a6be2bdSXie Xiaobo #include <linux/init.h>
138a6be2bdSXie Xiaobo #include <linux/errno.h>
1494848654SScott Wood #include <linux/fsl/guts.h>
158a6be2bdSXie Xiaobo #include <linux/pci.h>
16*81d7cac4SRob Herring #include <linux/of.h>
17*81d7cac4SRob Herring #include <linux/of_address.h>
188a6be2bdSXie Xiaobo
198a6be2bdSXie Xiaobo #include <asm/pci-bridge.h>
208a6be2bdSXie Xiaobo #include <asm/udbg.h>
218a6be2bdSXie Xiaobo #include <asm/mpic.h>
227aa1aa6eSZhao Qiang #include <soc/fsl/qe/qe.h>
238a6be2bdSXie Xiaobo
248a6be2bdSXie Xiaobo #include <sysdev/fsl_soc.h>
258a6be2bdSXie Xiaobo #include <sysdev/fsl_pci.h>
268a6be2bdSXie Xiaobo #include "smp.h"
278a6be2bdSXie Xiaobo
288a6be2bdSXie Xiaobo #include "mpc85xx.h"
298a6be2bdSXie Xiaobo
twr_p1025_pic_init(void)308a6be2bdSXie Xiaobo static void __init twr_p1025_pic_init(void)
318a6be2bdSXie Xiaobo {
328a6be2bdSXie Xiaobo struct mpic *mpic;
338a6be2bdSXie Xiaobo
348a6be2bdSXie Xiaobo mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
358a6be2bdSXie Xiaobo MPIC_SINGLE_DEST_CPU,
368a6be2bdSXie Xiaobo 0, 256, " OpenPIC ");
378a6be2bdSXie Xiaobo
388a6be2bdSXie Xiaobo BUG_ON(mpic == NULL);
398a6be2bdSXie Xiaobo mpic_init(mpic);
408a6be2bdSXie Xiaobo }
418a6be2bdSXie Xiaobo
428a6be2bdSXie Xiaobo /* ************************************************************************
438a6be2bdSXie Xiaobo *
448a6be2bdSXie Xiaobo * Setup the architecture
458a6be2bdSXie Xiaobo *
468a6be2bdSXie Xiaobo */
twr_p1025_setup_arch(void)478a6be2bdSXie Xiaobo static void __init twr_p1025_setup_arch(void)
488a6be2bdSXie Xiaobo {
498a6be2bdSXie Xiaobo if (ppc_md.progress)
508a6be2bdSXie Xiaobo ppc_md.progress("twr_p1025_setup_arch()", 0);
518a6be2bdSXie Xiaobo
528a6be2bdSXie Xiaobo mpc85xx_smp_init();
538a6be2bdSXie Xiaobo
548a6be2bdSXie Xiaobo fsl_pci_assign_primary();
558a6be2bdSXie Xiaobo
568a6be2bdSXie Xiaobo #ifdef CONFIG_QUICC_ENGINE
57706f4aa0SZhao Qiang mpc85xx_qe_par_io_init();
588a6be2bdSXie Xiaobo
5931ea9d5dSXie Xiaobo #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
608a6be2bdSXie Xiaobo if (machine_is(twr_p1025)) {
618a6be2bdSXie Xiaobo struct ccsr_guts __iomem *guts;
623a9d970fSSebastian Andrzej Siewior struct device_node *np;
638a6be2bdSXie Xiaobo
648a6be2bdSXie Xiaobo np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
658a6be2bdSXie Xiaobo if (np) {
668a6be2bdSXie Xiaobo guts = of_iomap(np, 0);
678a6be2bdSXie Xiaobo if (!guts)
688a6be2bdSXie Xiaobo pr_err("twr_p1025: could not map global utilities register\n");
698a6be2bdSXie Xiaobo else {
708a6be2bdSXie Xiaobo /* P1025 has pins muxed for QE and other functions. To
718a6be2bdSXie Xiaobo * enable QE UEC mode, we need to set bit QE0 for UCC1
728a6be2bdSXie Xiaobo * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
738a6be2bdSXie Xiaobo * and QE12 for QE MII management signals in PMUXCR
748a6be2bdSXie Xiaobo * register.
758a6be2bdSXie Xiaobo * Set QE mux bits in PMUXCR */
768a6be2bdSXie Xiaobo setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
778a6be2bdSXie Xiaobo MPC85xx_PMUXCR_QE(3) |
788a6be2bdSXie Xiaobo MPC85xx_PMUXCR_QE(9) |
798a6be2bdSXie Xiaobo MPC85xx_PMUXCR_QE(12));
808a6be2bdSXie Xiaobo iounmap(guts);
818a6be2bdSXie Xiaobo
8231ea9d5dSXie Xiaobo #if IS_ENABLED(CONFIG_SERIAL_QE)
838a6be2bdSXie Xiaobo /* On P1025TWR board, the UCC7 acted as UART port.
848a6be2bdSXie Xiaobo * However, The UCC7's CTS pin is low level in default,
858a6be2bdSXie Xiaobo * it will impact the transmission in full duplex
868a6be2bdSXie Xiaobo * communication. So disable the Flow control pin PA18.
878a6be2bdSXie Xiaobo * The UCC7 UART just can use RXD and TXD pins.
888a6be2bdSXie Xiaobo */
898a6be2bdSXie Xiaobo par_io_config_pin(0, 18, 0, 0, 0, 0);
908a6be2bdSXie Xiaobo #endif
918a6be2bdSXie Xiaobo /* Drive PB29 to CPLD low - CPLD will then change
928a6be2bdSXie Xiaobo * muxing from LBC to QE */
938a6be2bdSXie Xiaobo par_io_config_pin(1, 29, 1, 0, 0, 0);
948a6be2bdSXie Xiaobo par_io_data_set(1, 29, 0);
958a6be2bdSXie Xiaobo }
968a6be2bdSXie Xiaobo of_node_put(np);
978a6be2bdSXie Xiaobo }
988a6be2bdSXie Xiaobo }
998a6be2bdSXie Xiaobo #endif
1008a6be2bdSXie Xiaobo #endif /* CONFIG_QUICC_ENGINE */
1018a6be2bdSXie Xiaobo
1028a6be2bdSXie Xiaobo pr_info("TWR-P1025 board from Freescale Semiconductor\n");
1038a6be2bdSXie Xiaobo }
1048a6be2bdSXie Xiaobo
1058a6be2bdSXie Xiaobo machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
1068a6be2bdSXie Xiaobo
define_machine(twr_p1025)1078a6be2bdSXie Xiaobo define_machine(twr_p1025) {
1088a6be2bdSXie Xiaobo .name = "TWR-P1025",
1091c96fcdeSChristophe Leroy .compatible = "fsl,TWR-P1025",
1108a6be2bdSXie Xiaobo .setup_arch = twr_p1025_setup_arch,
1118a6be2bdSXie Xiaobo .init_IRQ = twr_p1025_pic_init,
1128a6be2bdSXie Xiaobo #ifdef CONFIG_PCI
1138a6be2bdSXie Xiaobo .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
1148a6be2bdSXie Xiaobo #endif
1158a6be2bdSXie Xiaobo .get_irq = mpic_get_irq,
1168a6be2bdSXie Xiaobo .progress = udbg_progress,
1178a6be2bdSXie Xiaobo };
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