1 /* 2 * P1022DS board specific routines 3 * 4 * Authors: Travis Wheatley <travis.wheatley@freescale.com> 5 * Dave Liu <daveliu@freescale.com> 6 * Timur Tabi <timur@freescale.com> 7 * 8 * Copyright 2010 Freescale Semiconductor, Inc. 9 * 10 * This file is taken from the Freescale P1022DS BSP, with modifications: 11 * 2) No AMP support 12 * 3) No PCI endpoint support 13 * 14 * This file is licensed under the terms of the GNU General Public License 15 * version 2. This program is licensed "as is" without any warranty of any 16 * kind, whether express or implied. 17 */ 18 19 #include <linux/pci.h> 20 #include <linux/of_platform.h> 21 #include <linux/memblock.h> 22 #include <asm/div64.h> 23 #include <asm/mpic.h> 24 #include <asm/swiotlb.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include <asm/fsl_guts.h> 29 30 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 31 32 /* 33 * Board-specific initialization of the DIU. This code should probably be 34 * executed when the DIU is opened, rather than in arch code, but the DIU 35 * driver does not have a mechanism for this (yet). 36 * 37 * This is especially problematic on the P1022DS because the local bus (eLBC) 38 * and the DIU video signals share the same pins, which means that enabling the 39 * DIU will disable access to NOR flash. 40 */ 41 42 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ 43 #define CLKDVDR_PXCKEN 0x80000000 44 #define CLKDVDR_PXCKINV 0x10000000 45 #define CLKDVDR_PXCKDLY 0x06000000 46 #define CLKDVDR_PXCLK_MASK 0x00FF0000 47 48 /* Some ngPIXIS register definitions */ 49 #define PX_BRDCFG1_DVIEN 0x80 50 #define PX_BRDCFG1_DFPEN 0x40 51 #define PX_BRDCFG1_BACKLIGHT 0x20 52 #define PX_BRDCFG1_DDCEN 0x10 53 54 /* 55 * DIU Area Descriptor 56 * 57 * Note that we need to byte-swap the value before it's written to the AD 58 * register. So even though the registers don't look like they're in the same 59 * bit positions as they are on the MPC8610, the same value is written to the 60 * AD register on the MPC8610 and on the P1022. 61 */ 62 #define AD_BYTE_F 0x10000000 63 #define AD_ALPHA_C_MASK 0x0E000000 64 #define AD_ALPHA_C_SHIFT 25 65 #define AD_BLUE_C_MASK 0x01800000 66 #define AD_BLUE_C_SHIFT 23 67 #define AD_GREEN_C_MASK 0x00600000 68 #define AD_GREEN_C_SHIFT 21 69 #define AD_RED_C_MASK 0x00180000 70 #define AD_RED_C_SHIFT 19 71 #define AD_PALETTE 0x00040000 72 #define AD_PIXEL_S_MASK 0x00030000 73 #define AD_PIXEL_S_SHIFT 16 74 #define AD_COMP_3_MASK 0x0000F000 75 #define AD_COMP_3_SHIFT 12 76 #define AD_COMP_2_MASK 0x00000F00 77 #define AD_COMP_2_SHIFT 8 78 #define AD_COMP_1_MASK 0x000000F0 79 #define AD_COMP_1_SHIFT 4 80 #define AD_COMP_0_MASK 0x0000000F 81 #define AD_COMP_0_SHIFT 0 82 83 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ 84 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ 85 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ 86 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ 87 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ 88 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) 89 90 /** 91 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth 92 * 93 * The Area Descriptor is a 32-bit value that determine which bits in each 94 * pixel are to be used for each color. 95 */ 96 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port, 97 unsigned int bits_per_pixel) 98 { 99 switch (bits_per_pixel) { 100 case 32: 101 /* 0x88883316 */ 102 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8); 103 case 24: 104 /* 0x88082219 */ 105 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8); 106 case 16: 107 /* 0x65053118 */ 108 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0); 109 default: 110 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); 111 return 0; 112 } 113 } 114 115 /** 116 * p1022ds_set_gamma_table: update the gamma table, if necessary 117 * 118 * On some boards, the gamma table for some ports may need to be modified. 119 * This is not the case on the P1022DS, so we do nothing. 120 */ 121 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port, 122 char *gamma_table_base) 123 { 124 } 125 126 /** 127 * p1022ds_set_monitor_port: switch the output to a different monitor port 128 * 129 */ 130 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) 131 { 132 struct device_node *np; 133 void __iomem *pixis; 134 u8 __iomem *brdcfg1; 135 136 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga"); 137 if (!np) 138 /* older device trees used "fsl,p1022ds-pixis" */ 139 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); 140 if (!np) { 141 pr_err("p1022ds: missing ngPIXIS node\n"); 142 return; 143 } 144 145 pixis = of_iomap(np, 0); 146 if (!pixis) { 147 pr_err("p1022ds: could not map ngPIXIS registers\n"); 148 return; 149 } 150 brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ 151 152 switch (port) { 153 case FSL_DIU_PORT_DVI: 154 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 155 /* Enable the DVI port, disable the DFP and the backlight */ 156 clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT, 157 PX_BRDCFG1_DVIEN); 158 break; 159 case FSL_DIU_PORT_LVDS: 160 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 161 /* Enable the DFP port, disable the DVI and the backlight */ 162 clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT, 163 PX_BRDCFG1_DFPEN); 164 break; 165 default: 166 pr_err("p1022ds: unsupported monitor port %i\n", port); 167 } 168 169 iounmap(pixis); 170 } 171 172 /** 173 * p1022ds_set_pixel_clock: program the DIU's clock 174 * 175 * @pixclock: the wavelength, in picoseconds, of the clock 176 */ 177 void p1022ds_set_pixel_clock(unsigned int pixclock) 178 { 179 struct device_node *guts_np = NULL; 180 struct ccsr_guts_85xx __iomem *guts; 181 unsigned long freq; 182 u64 temp; 183 u32 pxclk; 184 185 /* Map the global utilities registers. */ 186 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); 187 if (!guts_np) { 188 pr_err("p1022ds: missing global utilties device node\n"); 189 return; 190 } 191 192 guts = of_iomap(guts_np, 0); 193 of_node_put(guts_np); 194 if (!guts) { 195 pr_err("p1022ds: could not map global utilties device\n"); 196 return; 197 } 198 199 /* Convert pixclock from a wavelength to a frequency */ 200 temp = 1000000000000ULL; 201 do_div(temp, pixclock); 202 freq = temp; 203 204 /* 205 * 'pxclk' is the ratio of the platform clock to the pixel clock. 206 * This number is programmed into the CLKDVDR register, and the valid 207 * range of values is 2-255. 208 */ 209 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); 210 pxclk = clamp_t(u32, pxclk, 2, 255); 211 212 /* Disable the pixel clock, and set it to non-inverted and no delay */ 213 clrbits32(&guts->clkdvdr, 214 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); 215 216 /* Enable the clock and set the pxclk */ 217 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); 218 219 iounmap(guts); 220 } 221 222 /** 223 * p1022ds_valid_monitor_port: set the monitor port for sysfs 224 */ 225 enum fsl_diu_monitor_port 226 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port) 227 { 228 switch (port) { 229 case FSL_DIU_PORT_DVI: 230 case FSL_DIU_PORT_LVDS: 231 return port; 232 default: 233 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */ 234 } 235 } 236 237 #endif 238 239 void __init p1022_ds_pic_init(void) 240 { 241 struct mpic *mpic; 242 struct resource r; 243 struct device_node *np; 244 245 np = of_find_node_by_type(NULL, "open-pic"); 246 if (!np) { 247 pr_err("Could not find open-pic node\n"); 248 return; 249 } 250 251 if (of_address_to_resource(np, 0, &r)) { 252 pr_err("Failed to map mpic register space\n"); 253 of_node_put(np); 254 return; 255 } 256 257 mpic = mpic_alloc(np, r.start, 258 MPIC_PRIMARY | MPIC_WANTS_RESET | 259 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 260 MPIC_SINGLE_DEST_CPU, 261 0, 256, " OpenPIC "); 262 263 BUG_ON(mpic == NULL); 264 of_node_put(np); 265 266 mpic_init(mpic); 267 } 268 269 #ifdef CONFIG_SMP 270 void __init mpc85xx_smp_init(void); 271 #endif 272 273 /* 274 * Setup the architecture 275 */ 276 static void __init p1022_ds_setup_arch(void) 277 { 278 #ifdef CONFIG_PCI 279 struct device_node *np; 280 #endif 281 dma_addr_t max = 0xffffffff; 282 283 if (ppc_md.progress) 284 ppc_md.progress("p1022_ds_setup_arch()", 0); 285 286 #ifdef CONFIG_PCI 287 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") { 288 struct resource rsrc; 289 struct pci_controller *hose; 290 291 of_address_to_resource(np, 0, &rsrc); 292 293 if ((rsrc.start & 0xfffff) == 0x8000) 294 fsl_add_bridge(np, 1); 295 else 296 fsl_add_bridge(np, 0); 297 298 hose = pci_find_hose_for_OF_device(np); 299 max = min(max, hose->dma_window_base_cur + 300 hose->dma_window_size); 301 } 302 #endif 303 304 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 305 diu_ops.get_pixel_format = p1022ds_get_pixel_format; 306 diu_ops.set_gamma_table = p1022ds_set_gamma_table; 307 diu_ops.set_monitor_port = p1022ds_set_monitor_port; 308 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; 309 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; 310 #endif 311 312 #ifdef CONFIG_SMP 313 mpc85xx_smp_init(); 314 #endif 315 316 #ifdef CONFIG_SWIOTLB 317 if (memblock_end_of_DRAM() > max) { 318 ppc_swiotlb_enable = 1; 319 set_pci_dma_ops(&swiotlb_dma_ops); 320 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 321 } 322 #endif 323 324 pr_info("Freescale P1022 DS reference board\n"); 325 } 326 327 static struct of_device_id __initdata p1022_ds_ids[] = { 328 { .type = "soc", }, 329 { .compatible = "soc", }, 330 { .compatible = "simple-bus", }, 331 { .compatible = "gianfar", }, 332 /* So that the DMA channel nodes can be probed individually: */ 333 { .compatible = "fsl,eloplus-dma", }, 334 {}, 335 }; 336 337 static int __init p1022_ds_publish_devices(void) 338 { 339 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL); 340 } 341 machine_device_initcall(p1022_ds, p1022_ds_publish_devices); 342 343 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); 344 345 /* 346 * Called very early, device-tree isn't unflattened 347 */ 348 static int __init p1022_ds_probe(void) 349 { 350 unsigned long root = of_get_flat_dt_root(); 351 352 return of_flat_dt_is_compatible(root, "fsl,p1022ds"); 353 } 354 355 define_machine(p1022_ds) { 356 .name = "P1022 DS", 357 .probe = p1022_ds_probe, 358 .setup_arch = p1022_ds_setup_arch, 359 .init_IRQ = p1022_ds_pic_init, 360 #ifdef CONFIG_PCI 361 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 362 #endif 363 .get_irq = mpic_get_irq, 364 .restart = fsl_rstcr_restart, 365 .calibrate_decr = generic_calibrate_decr, 366 .progress = udbg_progress, 367 }; 368