1 /* 2 * P1022DS board specific routines 3 * 4 * Authors: Travis Wheatley <travis.wheatley@freescale.com> 5 * Dave Liu <daveliu@freescale.com> 6 * Timur Tabi <timur@freescale.com> 7 * 8 * Copyright 2010 Freescale Semiconductor, Inc. 9 * 10 * This file is taken from the Freescale P1022DS BSP, with modifications: 11 * 2) No AMP support 12 * 3) No PCI endpoint support 13 * 14 * This file is licensed under the terms of the GNU General Public License 15 * version 2. This program is licensed "as is" without any warranty of any 16 * kind, whether express or implied. 17 */ 18 19 #include <linux/pci.h> 20 #include <linux/of_platform.h> 21 #include <linux/memblock.h> 22 #include <asm/div64.h> 23 #include <asm/mpic.h> 24 #include <asm/swiotlb.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include <asm/fsl_guts.h> 29 #include "smp.h" 30 31 #include "mpc85xx.h" 32 33 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 34 35 /* 36 * Board-specific initialization of the DIU. This code should probably be 37 * executed when the DIU is opened, rather than in arch code, but the DIU 38 * driver does not have a mechanism for this (yet). 39 * 40 * This is especially problematic on the P1022DS because the local bus (eLBC) 41 * and the DIU video signals share the same pins, which means that enabling the 42 * DIU will disable access to NOR flash. 43 */ 44 45 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ 46 #define CLKDVDR_PXCKEN 0x80000000 47 #define CLKDVDR_PXCKINV 0x10000000 48 #define CLKDVDR_PXCKDLY 0x06000000 49 #define CLKDVDR_PXCLK_MASK 0x00FF0000 50 51 /* Some ngPIXIS register definitions */ 52 #define PX_BRDCFG1_DVIEN 0x80 53 #define PX_BRDCFG1_DFPEN 0x40 54 #define PX_BRDCFG1_BACKLIGHT 0x20 55 #define PX_BRDCFG1_DDCEN 0x10 56 57 /* 58 * DIU Area Descriptor 59 * 60 * Note that we need to byte-swap the value before it's written to the AD 61 * register. So even though the registers don't look like they're in the same 62 * bit positions as they are on the MPC8610, the same value is written to the 63 * AD register on the MPC8610 and on the P1022. 64 */ 65 #define AD_BYTE_F 0x10000000 66 #define AD_ALPHA_C_MASK 0x0E000000 67 #define AD_ALPHA_C_SHIFT 25 68 #define AD_BLUE_C_MASK 0x01800000 69 #define AD_BLUE_C_SHIFT 23 70 #define AD_GREEN_C_MASK 0x00600000 71 #define AD_GREEN_C_SHIFT 21 72 #define AD_RED_C_MASK 0x00180000 73 #define AD_RED_C_SHIFT 19 74 #define AD_PALETTE 0x00040000 75 #define AD_PIXEL_S_MASK 0x00030000 76 #define AD_PIXEL_S_SHIFT 16 77 #define AD_COMP_3_MASK 0x0000F000 78 #define AD_COMP_3_SHIFT 12 79 #define AD_COMP_2_MASK 0x00000F00 80 #define AD_COMP_2_SHIFT 8 81 #define AD_COMP_1_MASK 0x000000F0 82 #define AD_COMP_1_SHIFT 4 83 #define AD_COMP_0_MASK 0x0000000F 84 #define AD_COMP_0_SHIFT 0 85 86 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ 87 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ 88 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ 89 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ 90 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ 91 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) 92 93 /** 94 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth 95 * 96 * The Area Descriptor is a 32-bit value that determine which bits in each 97 * pixel are to be used for each color. 98 */ 99 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port, 100 unsigned int bits_per_pixel) 101 { 102 switch (bits_per_pixel) { 103 case 32: 104 /* 0x88883316 */ 105 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8); 106 case 24: 107 /* 0x88082219 */ 108 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8); 109 case 16: 110 /* 0x65053118 */ 111 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0); 112 default: 113 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); 114 return 0; 115 } 116 } 117 118 /** 119 * p1022ds_set_gamma_table: update the gamma table, if necessary 120 * 121 * On some boards, the gamma table for some ports may need to be modified. 122 * This is not the case on the P1022DS, so we do nothing. 123 */ 124 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port, 125 char *gamma_table_base) 126 { 127 } 128 129 /** 130 * p1022ds_set_monitor_port: switch the output to a different monitor port 131 * 132 */ 133 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) 134 { 135 struct device_node *np; 136 void __iomem *pixis; 137 u8 __iomem *brdcfg1; 138 139 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga"); 140 if (!np) 141 /* older device trees used "fsl,p1022ds-pixis" */ 142 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); 143 if (!np) { 144 pr_err("p1022ds: missing ngPIXIS node\n"); 145 return; 146 } 147 148 pixis = of_iomap(np, 0); 149 if (!pixis) { 150 pr_err("p1022ds: could not map ngPIXIS registers\n"); 151 return; 152 } 153 brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ 154 155 switch (port) { 156 case FSL_DIU_PORT_DVI: 157 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 158 /* Enable the DVI port, disable the DFP and the backlight */ 159 clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT, 160 PX_BRDCFG1_DVIEN); 161 break; 162 case FSL_DIU_PORT_LVDS: 163 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 164 /* Enable the DFP port, disable the DVI and the backlight */ 165 clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT, 166 PX_BRDCFG1_DFPEN); 167 break; 168 default: 169 pr_err("p1022ds: unsupported monitor port %i\n", port); 170 } 171 172 iounmap(pixis); 173 } 174 175 /** 176 * p1022ds_set_pixel_clock: program the DIU's clock 177 * 178 * @pixclock: the wavelength, in picoseconds, of the clock 179 */ 180 void p1022ds_set_pixel_clock(unsigned int pixclock) 181 { 182 struct device_node *guts_np = NULL; 183 struct ccsr_guts_85xx __iomem *guts; 184 unsigned long freq; 185 u64 temp; 186 u32 pxclk; 187 188 /* Map the global utilities registers. */ 189 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); 190 if (!guts_np) { 191 pr_err("p1022ds: missing global utilties device node\n"); 192 return; 193 } 194 195 guts = of_iomap(guts_np, 0); 196 of_node_put(guts_np); 197 if (!guts) { 198 pr_err("p1022ds: could not map global utilties device\n"); 199 return; 200 } 201 202 /* Convert pixclock from a wavelength to a frequency */ 203 temp = 1000000000000ULL; 204 do_div(temp, pixclock); 205 freq = temp; 206 207 /* 208 * 'pxclk' is the ratio of the platform clock to the pixel clock. 209 * This number is programmed into the CLKDVDR register, and the valid 210 * range of values is 2-255. 211 */ 212 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); 213 pxclk = clamp_t(u32, pxclk, 2, 255); 214 215 /* Disable the pixel clock, and set it to non-inverted and no delay */ 216 clrbits32(&guts->clkdvdr, 217 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); 218 219 /* Enable the clock and set the pxclk */ 220 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); 221 222 iounmap(guts); 223 } 224 225 /** 226 * p1022ds_valid_monitor_port: set the monitor port for sysfs 227 */ 228 enum fsl_diu_monitor_port 229 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port) 230 { 231 switch (port) { 232 case FSL_DIU_PORT_DVI: 233 case FSL_DIU_PORT_LVDS: 234 return port; 235 default: 236 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */ 237 } 238 } 239 240 #endif 241 242 void __init p1022_ds_pic_init(void) 243 { 244 struct mpic *mpic = mpic_alloc(NULL, 0, 245 MPIC_WANTS_RESET | 246 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 247 MPIC_SINGLE_DEST_CPU, 248 0, 256, " OpenPIC "); 249 BUG_ON(mpic == NULL); 250 mpic_init(mpic); 251 } 252 253 /* 254 * Setup the architecture 255 */ 256 static void __init p1022_ds_setup_arch(void) 257 { 258 #ifdef CONFIG_PCI 259 struct device_node *np; 260 #endif 261 dma_addr_t max = 0xffffffff; 262 263 if (ppc_md.progress) 264 ppc_md.progress("p1022_ds_setup_arch()", 0); 265 266 #ifdef CONFIG_PCI 267 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") { 268 struct resource rsrc; 269 struct pci_controller *hose; 270 271 of_address_to_resource(np, 0, &rsrc); 272 273 if ((rsrc.start & 0xfffff) == 0x8000) 274 fsl_add_bridge(np, 1); 275 else 276 fsl_add_bridge(np, 0); 277 278 hose = pci_find_hose_for_OF_device(np); 279 max = min(max, hose->dma_window_base_cur + 280 hose->dma_window_size); 281 } 282 #endif 283 284 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 285 diu_ops.get_pixel_format = p1022ds_get_pixel_format; 286 diu_ops.set_gamma_table = p1022ds_set_gamma_table; 287 diu_ops.set_monitor_port = p1022ds_set_monitor_port; 288 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; 289 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; 290 #endif 291 292 mpc85xx_smp_init(); 293 294 #ifdef CONFIG_SWIOTLB 295 if (memblock_end_of_DRAM() > max) { 296 ppc_swiotlb_enable = 1; 297 set_pci_dma_ops(&swiotlb_dma_ops); 298 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 299 } 300 #endif 301 302 pr_info("Freescale P1022 DS reference board\n"); 303 } 304 305 static struct of_device_id __initdata p1022_ds_ids[] = { 306 /* So that the DMA channel nodes can be probed individually: */ 307 { .compatible = "fsl,eloplus-dma", }, 308 {}, 309 }; 310 311 static int __init p1022_ds_publish_devices(void) 312 { 313 mpc85xx_common_publish_devices(); 314 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL); 315 } 316 machine_device_initcall(p1022_ds, p1022_ds_publish_devices); 317 318 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); 319 320 /* 321 * Called very early, device-tree isn't unflattened 322 */ 323 static int __init p1022_ds_probe(void) 324 { 325 unsigned long root = of_get_flat_dt_root(); 326 327 return of_flat_dt_is_compatible(root, "fsl,p1022ds"); 328 } 329 330 define_machine(p1022_ds) { 331 .name = "P1022 DS", 332 .probe = p1022_ds_probe, 333 .setup_arch = p1022_ds_setup_arch, 334 .init_IRQ = p1022_ds_pic_init, 335 #ifdef CONFIG_PCI 336 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 337 #endif 338 .get_irq = mpic_get_irq, 339 .restart = fsl_rstcr_restart, 340 .calibrate_decr = generic_calibrate_decr, 341 .progress = udbg_progress, 342 }; 343