1 /* 2 * P1022DS board specific routines 3 * 4 * Authors: Travis Wheatley <travis.wheatley@freescale.com> 5 * Dave Liu <daveliu@freescale.com> 6 * Timur Tabi <timur@freescale.com> 7 * 8 * Copyright 2010 Freescale Semiconductor, Inc. 9 * 10 * This file is taken from the Freescale P1022DS BSP, with modifications: 11 * 2) No AMP support 12 * 3) No PCI endpoint support 13 * 14 * This file is licensed under the terms of the GNU General Public License 15 * version 2. This program is licensed "as is" without any warranty of any 16 * kind, whether express or implied. 17 */ 18 19 #include <linux/pci.h> 20 #include <linux/of_platform.h> 21 #include <linux/memblock.h> 22 #include <asm/div64.h> 23 #include <asm/mpic.h> 24 #include <asm/swiotlb.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include <asm/fsl_guts.h> 29 30 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 31 32 /* 33 * Board-specific initialization of the DIU. This code should probably be 34 * executed when the DIU is opened, rather than in arch code, but the DIU 35 * driver does not have a mechanism for this (yet). 36 * 37 * This is especially problematic on the P1022DS because the local bus (eLBC) 38 * and the DIU video signals share the same pins, which means that enabling the 39 * DIU will disable access to NOR flash. 40 */ 41 42 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ 43 #define CLKDVDR_PXCKEN 0x80000000 44 #define CLKDVDR_PXCKINV 0x10000000 45 #define CLKDVDR_PXCKDLY 0x06000000 46 #define CLKDVDR_PXCLK_MASK 0x00FF0000 47 48 /* Some ngPIXIS register definitions */ 49 #define PX_BRDCFG1_DVIEN 0x80 50 #define PX_BRDCFG1_DFPEN 0x40 51 #define PX_BRDCFG1_BACKLIGHT 0x20 52 #define PX_BRDCFG1_DDCEN 0x10 53 54 /* 55 * DIU Area Descriptor 56 * 57 * Note that we need to byte-swap the value before it's written to the AD 58 * register. So even though the registers don't look like they're in the same 59 * bit positions as they are on the MPC8610, the same value is written to the 60 * AD register on the MPC8610 and on the P1022. 61 */ 62 #define AD_BYTE_F 0x10000000 63 #define AD_ALPHA_C_MASK 0x0E000000 64 #define AD_ALPHA_C_SHIFT 25 65 #define AD_BLUE_C_MASK 0x01800000 66 #define AD_BLUE_C_SHIFT 23 67 #define AD_GREEN_C_MASK 0x00600000 68 #define AD_GREEN_C_SHIFT 21 69 #define AD_RED_C_MASK 0x00180000 70 #define AD_RED_C_SHIFT 19 71 #define AD_PALETTE 0x00040000 72 #define AD_PIXEL_S_MASK 0x00030000 73 #define AD_PIXEL_S_SHIFT 16 74 #define AD_COMP_3_MASK 0x0000F000 75 #define AD_COMP_3_SHIFT 12 76 #define AD_COMP_2_MASK 0x00000F00 77 #define AD_COMP_2_SHIFT 8 78 #define AD_COMP_1_MASK 0x000000F0 79 #define AD_COMP_1_SHIFT 4 80 #define AD_COMP_0_MASK 0x0000000F 81 #define AD_COMP_0_SHIFT 0 82 83 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ 84 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ 85 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ 86 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ 87 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ 88 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) 89 90 /** 91 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth 92 * 93 * The Area Descriptor is a 32-bit value that determine which bits in each 94 * pixel are to be used for each color. 95 */ 96 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port, 97 unsigned int bits_per_pixel) 98 { 99 switch (bits_per_pixel) { 100 case 32: 101 /* 0x88883316 */ 102 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8); 103 case 24: 104 /* 0x88082219 */ 105 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8); 106 case 16: 107 /* 0x65053118 */ 108 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0); 109 default: 110 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); 111 return 0; 112 } 113 } 114 115 /** 116 * p1022ds_set_gamma_table: update the gamma table, if necessary 117 * 118 * On some boards, the gamma table for some ports may need to be modified. 119 * This is not the case on the P1022DS, so we do nothing. 120 */ 121 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port, 122 char *gamma_table_base) 123 { 124 } 125 126 /** 127 * p1022ds_set_monitor_port: switch the output to a different monitor port 128 * 129 */ 130 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) 131 { 132 struct device_node *pixis_node; 133 void __iomem *pixis; 134 u8 __iomem *brdcfg1; 135 136 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); 137 if (!pixis_node) { 138 pr_err("p1022ds: missing ngPIXIS node\n"); 139 return; 140 } 141 142 pixis = of_iomap(pixis_node, 0); 143 if (!pixis) { 144 pr_err("p1022ds: could not map ngPIXIS registers\n"); 145 return; 146 } 147 brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ 148 149 switch (port) { 150 case FSL_DIU_PORT_DVI: 151 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 152 /* Enable the DVI port, disable the DFP and the backlight */ 153 clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT, 154 PX_BRDCFG1_DVIEN); 155 break; 156 case FSL_DIU_PORT_LVDS: 157 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 158 /* Enable the DFP port, disable the DVI and the backlight */ 159 clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT, 160 PX_BRDCFG1_DFPEN); 161 break; 162 default: 163 pr_err("p1022ds: unsupported monitor port %i\n", port); 164 } 165 166 iounmap(pixis); 167 } 168 169 /** 170 * p1022ds_set_pixel_clock: program the DIU's clock 171 * 172 * @pixclock: the wavelength, in picoseconds, of the clock 173 */ 174 void p1022ds_set_pixel_clock(unsigned int pixclock) 175 { 176 struct device_node *guts_np = NULL; 177 struct ccsr_guts_85xx __iomem *guts; 178 unsigned long freq; 179 u64 temp; 180 u32 pxclk; 181 182 /* Map the global utilities registers. */ 183 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); 184 if (!guts_np) { 185 pr_err("p1022ds: missing global utilties device node\n"); 186 return; 187 } 188 189 guts = of_iomap(guts_np, 0); 190 of_node_put(guts_np); 191 if (!guts) { 192 pr_err("p1022ds: could not map global utilties device\n"); 193 return; 194 } 195 196 /* Convert pixclock from a wavelength to a frequency */ 197 temp = 1000000000000ULL; 198 do_div(temp, pixclock); 199 freq = temp; 200 201 /* 202 * 'pxclk' is the ratio of the platform clock to the pixel clock. 203 * This number is programmed into the CLKDVDR register, and the valid 204 * range of values is 2-255. 205 */ 206 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); 207 pxclk = clamp_t(u32, pxclk, 2, 255); 208 209 /* Disable the pixel clock, and set it to non-inverted and no delay */ 210 clrbits32(&guts->clkdvdr, 211 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); 212 213 /* Enable the clock and set the pxclk */ 214 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); 215 216 iounmap(guts); 217 } 218 219 /** 220 * p1022ds_valid_monitor_port: set the monitor port for sysfs 221 */ 222 enum fsl_diu_monitor_port 223 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port) 224 { 225 switch (port) { 226 case FSL_DIU_PORT_DVI: 227 case FSL_DIU_PORT_LVDS: 228 return port; 229 default: 230 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */ 231 } 232 } 233 234 #endif 235 236 void __init p1022_ds_pic_init(void) 237 { 238 struct mpic *mpic; 239 struct resource r; 240 struct device_node *np; 241 242 np = of_find_node_by_type(NULL, "open-pic"); 243 if (!np) { 244 pr_err("Could not find open-pic node\n"); 245 return; 246 } 247 248 if (of_address_to_resource(np, 0, &r)) { 249 pr_err("Failed to map mpic register space\n"); 250 of_node_put(np); 251 return; 252 } 253 254 mpic = mpic_alloc(np, r.start, 255 MPIC_PRIMARY | MPIC_WANTS_RESET | 256 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | 257 MPIC_SINGLE_DEST_CPU, 258 0, 256, " OpenPIC "); 259 260 BUG_ON(mpic == NULL); 261 of_node_put(np); 262 263 mpic_init(mpic); 264 } 265 266 #ifdef CONFIG_SMP 267 void __init mpc85xx_smp_init(void); 268 #endif 269 270 /* 271 * Setup the architecture 272 */ 273 static void __init p1022_ds_setup_arch(void) 274 { 275 #ifdef CONFIG_PCI 276 struct device_node *np; 277 #endif 278 dma_addr_t max = 0xffffffff; 279 280 if (ppc_md.progress) 281 ppc_md.progress("p1022_ds_setup_arch()", 0); 282 283 #ifdef CONFIG_PCI 284 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") { 285 struct resource rsrc; 286 struct pci_controller *hose; 287 288 of_address_to_resource(np, 0, &rsrc); 289 290 if ((rsrc.start & 0xfffff) == 0x8000) 291 fsl_add_bridge(np, 1); 292 else 293 fsl_add_bridge(np, 0); 294 295 hose = pci_find_hose_for_OF_device(np); 296 max = min(max, hose->dma_window_base_cur + 297 hose->dma_window_size); 298 } 299 #endif 300 301 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 302 diu_ops.get_pixel_format = p1022ds_get_pixel_format; 303 diu_ops.set_gamma_table = p1022ds_set_gamma_table; 304 diu_ops.set_monitor_port = p1022ds_set_monitor_port; 305 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; 306 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; 307 #endif 308 309 #ifdef CONFIG_SMP 310 mpc85xx_smp_init(); 311 #endif 312 313 #ifdef CONFIG_SWIOTLB 314 if (memblock_end_of_DRAM() > max) { 315 ppc_swiotlb_enable = 1; 316 set_pci_dma_ops(&swiotlb_dma_ops); 317 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 318 } 319 #endif 320 321 pr_info("Freescale P1022 DS reference board\n"); 322 } 323 324 static struct of_device_id __initdata p1022_ds_ids[] = { 325 { .type = "soc", }, 326 { .compatible = "soc", }, 327 { .compatible = "simple-bus", }, 328 { .compatible = "gianfar", }, 329 /* So that the DMA channel nodes can be probed individually: */ 330 { .compatible = "fsl,eloplus-dma", }, 331 {}, 332 }; 333 334 static int __init p1022_ds_publish_devices(void) 335 { 336 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL); 337 } 338 machine_device_initcall(p1022_ds, p1022_ds_publish_devices); 339 340 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); 341 342 /* 343 * Called very early, device-tree isn't unflattened 344 */ 345 static int __init p1022_ds_probe(void) 346 { 347 unsigned long root = of_get_flat_dt_root(); 348 349 return of_flat_dt_is_compatible(root, "fsl,p1022ds"); 350 } 351 352 define_machine(p1022_ds) { 353 .name = "P1022 DS", 354 .probe = p1022_ds_probe, 355 .setup_arch = p1022_ds_setup_arch, 356 .init_IRQ = p1022_ds_pic_init, 357 #ifdef CONFIG_PCI 358 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 359 #endif 360 .get_irq = mpic_get_irq, 361 .restart = fsl_rstcr_restart, 362 .calibrate_decr = generic_calibrate_decr, 363 .progress = udbg_progress, 364 }; 365