1 /* 2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved. 3 * 4 * Author: Andy Fleming <afleming@freescale.com> 5 * 6 * Based on 83xx/mpc8360e_pb.c by: 7 * Li Yang <LeoLi@freescale.com> 8 * Yin Olivia <Hong-hua.Yin@freescale.com> 9 * 10 * Description: 11 * MPC85xx MDS board specific routines. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19 #include <linux/stddef.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/reboot.h> 24 #include <linux/pci.h> 25 #include <linux/kdev_t.h> 26 #include <linux/major.h> 27 #include <linux/console.h> 28 #include <linux/delay.h> 29 #include <linux/seq_file.h> 30 #include <linux/initrd.h> 31 #include <linux/fsl_devices.h> 32 #include <linux/of_platform.h> 33 #include <linux/of_device.h> 34 #include <linux/phy.h> 35 #include <linux/memblock.h> 36 37 #include <asm/system.h> 38 #include <linux/atomic.h> 39 #include <asm/time.h> 40 #include <asm/io.h> 41 #include <asm/machdep.h> 42 #include <asm/pci-bridge.h> 43 #include <asm/irq.h> 44 #include <mm/mmu_decl.h> 45 #include <asm/prom.h> 46 #include <asm/udbg.h> 47 #include <sysdev/fsl_soc.h> 48 #include <sysdev/fsl_pci.h> 49 #include <sysdev/simple_gpio.h> 50 #include <asm/qe.h> 51 #include <asm/qe_ic.h> 52 #include <asm/mpic.h> 53 #include <asm/swiotlb.h> 54 55 #undef DEBUG 56 #ifdef DEBUG 57 #define DBG(fmt...) udbg_printf(fmt) 58 #else 59 #define DBG(fmt...) 60 #endif 61 62 #define MV88E1111_SCR 0x10 63 #define MV88E1111_SCR_125CLK 0x0010 64 static int mpc8568_fixup_125_clock(struct phy_device *phydev) 65 { 66 int scr; 67 int err; 68 69 /* Workaround for the 125 CLK Toggle */ 70 scr = phy_read(phydev, MV88E1111_SCR); 71 72 if (scr < 0) 73 return scr; 74 75 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); 76 77 if (err) 78 return err; 79 80 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 81 82 if (err) 83 return err; 84 85 scr = phy_read(phydev, MV88E1111_SCR); 86 87 if (scr < 0) 88 return scr; 89 90 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); 91 92 return err; 93 } 94 95 static int mpc8568_mds_phy_fixups(struct phy_device *phydev) 96 { 97 int temp; 98 int err; 99 100 /* Errata */ 101 err = phy_write(phydev,29, 0x0006); 102 103 if (err) 104 return err; 105 106 temp = phy_read(phydev, 30); 107 108 if (temp < 0) 109 return temp; 110 111 temp = (temp & (~0x8000)) | 0x4000; 112 err = phy_write(phydev,30, temp); 113 114 if (err) 115 return err; 116 117 err = phy_write(phydev,29, 0x000a); 118 119 if (err) 120 return err; 121 122 temp = phy_read(phydev, 30); 123 124 if (temp < 0) 125 return temp; 126 127 temp = phy_read(phydev, 30); 128 129 if (temp < 0) 130 return temp; 131 132 temp &= ~0x0020; 133 134 err = phy_write(phydev,30,temp); 135 136 if (err) 137 return err; 138 139 /* Disable automatic MDI/MDIX selection */ 140 temp = phy_read(phydev, 16); 141 142 if (temp < 0) 143 return temp; 144 145 temp &= ~0x0060; 146 err = phy_write(phydev,16,temp); 147 148 return err; 149 } 150 151 /* ************************************************************************ 152 * 153 * Setup the architecture 154 * 155 */ 156 #ifdef CONFIG_SMP 157 extern void __init mpc85xx_smp_init(void); 158 #endif 159 160 #ifdef CONFIG_QUICC_ENGINE 161 static struct of_device_id mpc85xx_qe_ids[] __initdata = { 162 { .type = "qe", }, 163 { .compatible = "fsl,qe", }, 164 { }, 165 }; 166 167 static void __init mpc85xx_publish_qe_devices(void) 168 { 169 struct device_node *np; 170 171 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 172 if (!of_device_is_available(np)) { 173 of_node_put(np); 174 return; 175 } 176 177 of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL); 178 } 179 180 static void __init mpc85xx_mds_reset_ucc_phys(void) 181 { 182 struct device_node *np; 183 static u8 __iomem *bcsr_regs; 184 185 /* Map BCSR area */ 186 np = of_find_node_by_name(NULL, "bcsr"); 187 if (!np) 188 return; 189 190 bcsr_regs = of_iomap(np, 0); 191 of_node_put(np); 192 if (!bcsr_regs) 193 return; 194 195 if (machine_is(mpc8568_mds)) { 196 #define BCSR_UCC1_GETH_EN (0x1 << 7) 197 #define BCSR_UCC2_GETH_EN (0x1 << 7) 198 #define BCSR_UCC1_MODE_MSK (0x3 << 4) 199 #define BCSR_UCC2_MODE_MSK (0x3 << 0) 200 201 /* Turn off UCC1 & UCC2 */ 202 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 203 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 204 205 /* Mode is RGMII, all bits clear */ 206 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | 207 BCSR_UCC2_MODE_MSK); 208 209 /* Turn UCC1 & UCC2 on */ 210 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 211 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 212 } else if (machine_is(mpc8569_mds)) { 213 #define BCSR7_UCC12_GETHnRST (0x1 << 2) 214 #define BCSR8_UEM_MARVELL_RST (0x1 << 1) 215 #define BCSR_UCC_RGMII (0x1 << 6) 216 #define BCSR_UCC_RTBI (0x1 << 5) 217 /* 218 * U-Boot mangles interrupt polarity for Marvell PHYs, 219 * so reset built-in and UEM Marvell PHYs, this puts 220 * the PHYs into their normal state. 221 */ 222 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); 223 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); 224 225 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); 226 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); 227 228 for (np = NULL; (np = of_find_compatible_node(np, 229 "network", 230 "ucc_geth")) != NULL;) { 231 const unsigned int *prop; 232 int ucc_num; 233 234 prop = of_get_property(np, "cell-index", NULL); 235 if (prop == NULL) 236 continue; 237 238 ucc_num = *prop - 1; 239 240 prop = of_get_property(np, "phy-connection-type", NULL); 241 if (prop == NULL) 242 continue; 243 244 if (strcmp("rtbi", (const char *)prop) == 0) 245 clrsetbits_8(&bcsr_regs[7 + ucc_num], 246 BCSR_UCC_RGMII, BCSR_UCC_RTBI); 247 } 248 } else if (machine_is(p1021_mds)) { 249 #define BCSR11_ENET_MICRST (0x1 << 5) 250 /* Reset Micrel PHY */ 251 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); 252 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); 253 } 254 255 iounmap(bcsr_regs); 256 } 257 258 static void __init mpc85xx_mds_qe_init(void) 259 { 260 struct device_node *np; 261 262 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 263 if (!np) { 264 np = of_find_node_by_name(NULL, "qe"); 265 if (!np) 266 return; 267 } 268 269 if (!of_device_is_available(np)) { 270 of_node_put(np); 271 return; 272 } 273 274 qe_reset(); 275 of_node_put(np); 276 277 np = of_find_node_by_name(NULL, "par_io"); 278 if (np) { 279 struct device_node *ucc; 280 281 par_io_init(np); 282 of_node_put(np); 283 284 for_each_node_by_name(ucc, "ucc") 285 par_io_of_config(ucc); 286 } 287 288 mpc85xx_mds_reset_ucc_phys(); 289 290 if (machine_is(p1021_mds)) { 291 #define MPC85xx_PMUXCR_OFFSET 0x60 292 #define MPC85xx_PMUXCR_QE0 0x00008000 293 #define MPC85xx_PMUXCR_QE3 0x00001000 294 #define MPC85xx_PMUXCR_QE9 0x00000040 295 #define MPC85xx_PMUXCR_QE12 0x00000008 296 static __be32 __iomem *pmuxcr; 297 298 np = of_find_node_by_name(NULL, "global-utilities"); 299 300 if (np) { 301 pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET; 302 303 if (!pmuxcr) 304 printk(KERN_EMERG "Error: Alternate function" 305 " signal multiplex control register not" 306 " mapped!\n"); 307 else 308 /* P1021 has pins muxed for QE and other functions. To 309 * enable QE UEC mode, we need to set bit QE0 for UCC1 310 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 311 * and QE12 for QE MII management signals in PMUXCR 312 * register. 313 */ 314 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 | 315 MPC85xx_PMUXCR_QE3 | 316 MPC85xx_PMUXCR_QE9 | 317 MPC85xx_PMUXCR_QE12); 318 319 of_node_put(np); 320 } 321 322 } 323 } 324 325 static void __init mpc85xx_mds_qeic_init(void) 326 { 327 struct device_node *np; 328 329 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 330 if (!of_device_is_available(np)) { 331 of_node_put(np); 332 return; 333 } 334 335 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 336 if (!np) { 337 np = of_find_node_by_type(NULL, "qeic"); 338 if (!np) 339 return; 340 } 341 342 if (machine_is(p1021_mds)) 343 qe_ic_init(np, 0, qe_ic_cascade_low_mpic, 344 qe_ic_cascade_high_mpic); 345 else 346 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); 347 of_node_put(np); 348 } 349 #else 350 static void __init mpc85xx_publish_qe_devices(void) { } 351 static void __init mpc85xx_mds_qe_init(void) { } 352 static void __init mpc85xx_mds_qeic_init(void) { } 353 #endif /* CONFIG_QUICC_ENGINE */ 354 355 static void __init mpc85xx_mds_setup_arch(void) 356 { 357 #ifdef CONFIG_PCI 358 struct pci_controller *hose; 359 struct device_node *np; 360 #endif 361 dma_addr_t max = 0xffffffff; 362 363 if (ppc_md.progress) 364 ppc_md.progress("mpc85xx_mds_setup_arch()", 0); 365 366 #ifdef CONFIG_PCI 367 for_each_node_by_type(np, "pci") { 368 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 369 of_device_is_compatible(np, "fsl,mpc8548-pcie")) { 370 struct resource rsrc; 371 of_address_to_resource(np, 0, &rsrc); 372 if ((rsrc.start & 0xfffff) == 0x8000) 373 fsl_add_bridge(np, 1); 374 else 375 fsl_add_bridge(np, 0); 376 377 hose = pci_find_hose_for_OF_device(np); 378 max = min(max, hose->dma_window_base_cur + 379 hose->dma_window_size); 380 } 381 } 382 #endif 383 384 #ifdef CONFIG_SMP 385 mpc85xx_smp_init(); 386 #endif 387 388 mpc85xx_mds_qe_init(); 389 390 #ifdef CONFIG_SWIOTLB 391 if (memblock_end_of_DRAM() > max) { 392 ppc_swiotlb_enable = 1; 393 set_pci_dma_ops(&swiotlb_dma_ops); 394 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 395 } 396 #endif 397 } 398 399 400 static int __init board_fixups(void) 401 { 402 char phy_id[20]; 403 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"}; 404 struct device_node *mdio; 405 struct resource res; 406 int i; 407 408 for (i = 0; i < ARRAY_SIZE(compstrs); i++) { 409 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]); 410 411 of_address_to_resource(mdio, 0, &res); 412 snprintf(phy_id, sizeof(phy_id), "%llx:%02x", 413 (unsigned long long)res.start, 1); 414 415 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock); 416 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups); 417 418 /* Register a workaround for errata */ 419 snprintf(phy_id, sizeof(phy_id), "%llx:%02x", 420 (unsigned long long)res.start, 7); 421 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups); 422 423 of_node_put(mdio); 424 } 425 426 return 0; 427 } 428 machine_arch_initcall(mpc8568_mds, board_fixups); 429 machine_arch_initcall(mpc8569_mds, board_fixups); 430 431 static struct of_device_id mpc85xx_ids[] = { 432 { .type = "soc", }, 433 { .compatible = "soc", }, 434 { .compatible = "simple-bus", }, 435 { .compatible = "gianfar", }, 436 { .compatible = "fsl,rapidio-delta", }, 437 { .compatible = "fsl,mpc8548-guts", }, 438 { .compatible = "gpio-leds", }, 439 {}, 440 }; 441 442 static struct of_device_id p1021_ids[] = { 443 { .type = "soc", }, 444 { .compatible = "soc", }, 445 { .compatible = "simple-bus", }, 446 { .compatible = "gianfar", }, 447 {}, 448 }; 449 450 static int __init mpc85xx_publish_devices(void) 451 { 452 if (machine_is(mpc8568_mds)) 453 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio"); 454 if (machine_is(mpc8569_mds)) 455 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); 456 457 of_platform_bus_probe(NULL, mpc85xx_ids, NULL); 458 mpc85xx_publish_qe_devices(); 459 460 return 0; 461 } 462 463 static int __init p1021_publish_devices(void) 464 { 465 of_platform_bus_probe(NULL, p1021_ids, NULL); 466 mpc85xx_publish_qe_devices(); 467 468 return 0; 469 } 470 471 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 472 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); 473 machine_device_initcall(p1021_mds, p1021_publish_devices); 474 475 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); 476 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); 477 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier); 478 479 static void __init mpc85xx_mds_pic_init(void) 480 { 481 struct mpic *mpic; 482 struct resource r; 483 struct device_node *np = NULL; 484 485 np = of_find_node_by_type(NULL, "open-pic"); 486 if (!np) 487 return; 488 489 if (of_address_to_resource(np, 0, &r)) { 490 printk(KERN_ERR "Failed to map mpic register space\n"); 491 of_node_put(np); 492 return; 493 } 494 495 mpic = mpic_alloc(np, r.start, 496 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | 497 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, 498 0, 256, " OpenPIC "); 499 BUG_ON(mpic == NULL); 500 of_node_put(np); 501 502 mpic_init(mpic); 503 mpc85xx_mds_qeic_init(); 504 } 505 506 static int __init mpc85xx_mds_probe(void) 507 { 508 unsigned long root = of_get_flat_dt_root(); 509 510 return of_flat_dt_is_compatible(root, "MPC85xxMDS"); 511 } 512 513 define_machine(mpc8568_mds) { 514 .name = "MPC8568 MDS", 515 .probe = mpc85xx_mds_probe, 516 .setup_arch = mpc85xx_mds_setup_arch, 517 .init_IRQ = mpc85xx_mds_pic_init, 518 .get_irq = mpic_get_irq, 519 .restart = fsl_rstcr_restart, 520 .calibrate_decr = generic_calibrate_decr, 521 .progress = udbg_progress, 522 #ifdef CONFIG_PCI 523 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 524 #endif 525 }; 526 527 static int __init mpc8569_mds_probe(void) 528 { 529 unsigned long root = of_get_flat_dt_root(); 530 531 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS"); 532 } 533 534 define_machine(mpc8569_mds) { 535 .name = "MPC8569 MDS", 536 .probe = mpc8569_mds_probe, 537 .setup_arch = mpc85xx_mds_setup_arch, 538 .init_IRQ = mpc85xx_mds_pic_init, 539 .get_irq = mpic_get_irq, 540 .restart = fsl_rstcr_restart, 541 .calibrate_decr = generic_calibrate_decr, 542 .progress = udbg_progress, 543 #ifdef CONFIG_PCI 544 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 545 #endif 546 }; 547 548 static int __init p1021_mds_probe(void) 549 { 550 unsigned long root = of_get_flat_dt_root(); 551 552 return of_flat_dt_is_compatible(root, "fsl,P1021MDS"); 553 554 } 555 556 define_machine(p1021_mds) { 557 .name = "P1021 MDS", 558 .probe = p1021_mds_probe, 559 .setup_arch = mpc85xx_mds_setup_arch, 560 .init_IRQ = mpc85xx_mds_pic_init, 561 .get_irq = mpic_get_irq, 562 .restart = fsl_rstcr_restart, 563 .calibrate_decr = generic_calibrate_decr, 564 .progress = udbg_progress, 565 #ifdef CONFIG_PCI 566 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 567 #endif 568 }; 569 570