1 /* 2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved. 3 * 4 * Author: Andy Fleming <afleming@freescale.com> 5 * 6 * Based on 83xx/mpc8360e_pb.c by: 7 * Li Yang <LeoLi@freescale.com> 8 * Yin Olivia <Hong-hua.Yin@freescale.com> 9 * 10 * Description: 11 * MPC85xx MDS board specific routines. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19 #include <linux/stddef.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/reboot.h> 24 #include <linux/pci.h> 25 #include <linux/kdev_t.h> 26 #include <linux/major.h> 27 #include <linux/console.h> 28 #include <linux/delay.h> 29 #include <linux/seq_file.h> 30 #include <linux/initrd.h> 31 #include <linux/fsl_devices.h> 32 #include <linux/of_platform.h> 33 #include <linux/of_device.h> 34 #include <linux/phy.h> 35 #include <linux/memblock.h> 36 37 #include <asm/system.h> 38 #include <linux/atomic.h> 39 #include <asm/time.h> 40 #include <asm/io.h> 41 #include <asm/machdep.h> 42 #include <asm/pci-bridge.h> 43 #include <asm/irq.h> 44 #include <mm/mmu_decl.h> 45 #include <asm/prom.h> 46 #include <asm/udbg.h> 47 #include <sysdev/fsl_soc.h> 48 #include <sysdev/fsl_pci.h> 49 #include <sysdev/simple_gpio.h> 50 #include <asm/qe.h> 51 #include <asm/qe_ic.h> 52 #include <asm/mpic.h> 53 #include <asm/swiotlb.h> 54 #include "smp.h" 55 56 #include "mpc85xx.h" 57 58 #undef DEBUG 59 #ifdef DEBUG 60 #define DBG(fmt...) udbg_printf(fmt) 61 #else 62 #define DBG(fmt...) 63 #endif 64 65 #define MV88E1111_SCR 0x10 66 #define MV88E1111_SCR_125CLK 0x0010 67 static int mpc8568_fixup_125_clock(struct phy_device *phydev) 68 { 69 int scr; 70 int err; 71 72 /* Workaround for the 125 CLK Toggle */ 73 scr = phy_read(phydev, MV88E1111_SCR); 74 75 if (scr < 0) 76 return scr; 77 78 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); 79 80 if (err) 81 return err; 82 83 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 84 85 if (err) 86 return err; 87 88 scr = phy_read(phydev, MV88E1111_SCR); 89 90 if (scr < 0) 91 return scr; 92 93 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); 94 95 return err; 96 } 97 98 static int mpc8568_mds_phy_fixups(struct phy_device *phydev) 99 { 100 int temp; 101 int err; 102 103 /* Errata */ 104 err = phy_write(phydev,29, 0x0006); 105 106 if (err) 107 return err; 108 109 temp = phy_read(phydev, 30); 110 111 if (temp < 0) 112 return temp; 113 114 temp = (temp & (~0x8000)) | 0x4000; 115 err = phy_write(phydev,30, temp); 116 117 if (err) 118 return err; 119 120 err = phy_write(phydev,29, 0x000a); 121 122 if (err) 123 return err; 124 125 temp = phy_read(phydev, 30); 126 127 if (temp < 0) 128 return temp; 129 130 temp = phy_read(phydev, 30); 131 132 if (temp < 0) 133 return temp; 134 135 temp &= ~0x0020; 136 137 err = phy_write(phydev,30,temp); 138 139 if (err) 140 return err; 141 142 /* Disable automatic MDI/MDIX selection */ 143 temp = phy_read(phydev, 16); 144 145 if (temp < 0) 146 return temp; 147 148 temp &= ~0x0060; 149 err = phy_write(phydev,16,temp); 150 151 return err; 152 } 153 154 /* ************************************************************************ 155 * 156 * Setup the architecture 157 * 158 */ 159 #ifdef CONFIG_QUICC_ENGINE 160 static void __init mpc85xx_mds_reset_ucc_phys(void) 161 { 162 struct device_node *np; 163 static u8 __iomem *bcsr_regs; 164 165 /* Map BCSR area */ 166 np = of_find_node_by_name(NULL, "bcsr"); 167 if (!np) 168 return; 169 170 bcsr_regs = of_iomap(np, 0); 171 of_node_put(np); 172 if (!bcsr_regs) 173 return; 174 175 if (machine_is(mpc8568_mds)) { 176 #define BCSR_UCC1_GETH_EN (0x1 << 7) 177 #define BCSR_UCC2_GETH_EN (0x1 << 7) 178 #define BCSR_UCC1_MODE_MSK (0x3 << 4) 179 #define BCSR_UCC2_MODE_MSK (0x3 << 0) 180 181 /* Turn off UCC1 & UCC2 */ 182 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 183 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 184 185 /* Mode is RGMII, all bits clear */ 186 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | 187 BCSR_UCC2_MODE_MSK); 188 189 /* Turn UCC1 & UCC2 on */ 190 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); 191 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); 192 } else if (machine_is(mpc8569_mds)) { 193 #define BCSR7_UCC12_GETHnRST (0x1 << 2) 194 #define BCSR8_UEM_MARVELL_RST (0x1 << 1) 195 #define BCSR_UCC_RGMII (0x1 << 6) 196 #define BCSR_UCC_RTBI (0x1 << 5) 197 /* 198 * U-Boot mangles interrupt polarity for Marvell PHYs, 199 * so reset built-in and UEM Marvell PHYs, this puts 200 * the PHYs into their normal state. 201 */ 202 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); 203 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); 204 205 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); 206 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); 207 208 for (np = NULL; (np = of_find_compatible_node(np, 209 "network", 210 "ucc_geth")) != NULL;) { 211 const unsigned int *prop; 212 int ucc_num; 213 214 prop = of_get_property(np, "cell-index", NULL); 215 if (prop == NULL) 216 continue; 217 218 ucc_num = *prop - 1; 219 220 prop = of_get_property(np, "phy-connection-type", NULL); 221 if (prop == NULL) 222 continue; 223 224 if (strcmp("rtbi", (const char *)prop) == 0) 225 clrsetbits_8(&bcsr_regs[7 + ucc_num], 226 BCSR_UCC_RGMII, BCSR_UCC_RTBI); 227 } 228 } else if (machine_is(p1021_mds)) { 229 #define BCSR11_ENET_MICRST (0x1 << 5) 230 /* Reset Micrel PHY */ 231 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); 232 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); 233 } 234 235 iounmap(bcsr_regs); 236 } 237 238 static void __init mpc85xx_mds_qe_init(void) 239 { 240 struct device_node *np; 241 242 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 243 if (!np) { 244 np = of_find_node_by_name(NULL, "qe"); 245 if (!np) 246 return; 247 } 248 249 if (!of_device_is_available(np)) { 250 of_node_put(np); 251 return; 252 } 253 254 qe_reset(); 255 of_node_put(np); 256 257 np = of_find_node_by_name(NULL, "par_io"); 258 if (np) { 259 struct device_node *ucc; 260 261 par_io_init(np); 262 of_node_put(np); 263 264 for_each_node_by_name(ucc, "ucc") 265 par_io_of_config(ucc); 266 } 267 268 mpc85xx_mds_reset_ucc_phys(); 269 270 if (machine_is(p1021_mds)) { 271 #define MPC85xx_PMUXCR_OFFSET 0x60 272 #define MPC85xx_PMUXCR_QE0 0x00008000 273 #define MPC85xx_PMUXCR_QE3 0x00001000 274 #define MPC85xx_PMUXCR_QE9 0x00000040 275 #define MPC85xx_PMUXCR_QE12 0x00000008 276 static __be32 __iomem *pmuxcr; 277 278 np = of_find_node_by_name(NULL, "global-utilities"); 279 280 if (np) { 281 pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET; 282 283 if (!pmuxcr) 284 printk(KERN_EMERG "Error: Alternate function" 285 " signal multiplex control register not" 286 " mapped!\n"); 287 else 288 /* P1021 has pins muxed for QE and other functions. To 289 * enable QE UEC mode, we need to set bit QE0 for UCC1 290 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 291 * and QE12 for QE MII management signals in PMUXCR 292 * register. 293 */ 294 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 | 295 MPC85xx_PMUXCR_QE3 | 296 MPC85xx_PMUXCR_QE9 | 297 MPC85xx_PMUXCR_QE12); 298 299 of_node_put(np); 300 } 301 302 } 303 } 304 305 static void __init mpc85xx_mds_qeic_init(void) 306 { 307 struct device_node *np; 308 309 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 310 if (!of_device_is_available(np)) { 311 of_node_put(np); 312 return; 313 } 314 315 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 316 if (!np) { 317 np = of_find_node_by_type(NULL, "qeic"); 318 if (!np) 319 return; 320 } 321 322 if (machine_is(p1021_mds)) 323 qe_ic_init(np, 0, qe_ic_cascade_low_mpic, 324 qe_ic_cascade_high_mpic); 325 else 326 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); 327 of_node_put(np); 328 } 329 #else 330 static void __init mpc85xx_mds_qe_init(void) { } 331 static void __init mpc85xx_mds_qeic_init(void) { } 332 #endif /* CONFIG_QUICC_ENGINE */ 333 334 static void __init mpc85xx_mds_setup_arch(void) 335 { 336 #ifdef CONFIG_PCI 337 struct pci_controller *hose; 338 struct device_node *np; 339 #endif 340 dma_addr_t max = 0xffffffff; 341 342 if (ppc_md.progress) 343 ppc_md.progress("mpc85xx_mds_setup_arch()", 0); 344 345 #ifdef CONFIG_PCI 346 for_each_node_by_type(np, "pci") { 347 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 348 of_device_is_compatible(np, "fsl,mpc8548-pcie")) { 349 struct resource rsrc; 350 of_address_to_resource(np, 0, &rsrc); 351 if ((rsrc.start & 0xfffff) == 0x8000) 352 fsl_add_bridge(np, 1); 353 else 354 fsl_add_bridge(np, 0); 355 356 hose = pci_find_hose_for_OF_device(np); 357 max = min(max, hose->dma_window_base_cur + 358 hose->dma_window_size); 359 } 360 } 361 #endif 362 363 mpc85xx_smp_init(); 364 365 mpc85xx_mds_qe_init(); 366 367 #ifdef CONFIG_SWIOTLB 368 if (memblock_end_of_DRAM() > max) { 369 ppc_swiotlb_enable = 1; 370 set_pci_dma_ops(&swiotlb_dma_ops); 371 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 372 } 373 #endif 374 } 375 376 377 static int __init board_fixups(void) 378 { 379 char phy_id[20]; 380 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"}; 381 struct device_node *mdio; 382 struct resource res; 383 int i; 384 385 for (i = 0; i < ARRAY_SIZE(compstrs); i++) { 386 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]); 387 388 of_address_to_resource(mdio, 0, &res); 389 snprintf(phy_id, sizeof(phy_id), "%llx:%02x", 390 (unsigned long long)res.start, 1); 391 392 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock); 393 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups); 394 395 /* Register a workaround for errata */ 396 snprintf(phy_id, sizeof(phy_id), "%llx:%02x", 397 (unsigned long long)res.start, 7); 398 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups); 399 400 of_node_put(mdio); 401 } 402 403 return 0; 404 } 405 machine_arch_initcall(mpc8568_mds, board_fixups); 406 machine_arch_initcall(mpc8569_mds, board_fixups); 407 408 static struct of_device_id mpc85xx_ids[] = { 409 { .compatible = "fsl,mpc8548-guts", }, 410 { .compatible = "gpio-leds", }, 411 {}, 412 }; 413 414 static int __init mpc85xx_publish_devices(void) 415 { 416 if (machine_is(mpc8568_mds)) 417 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio"); 418 if (machine_is(mpc8569_mds)) 419 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); 420 421 mpc85xx_common_publish_devices(); 422 of_platform_bus_probe(NULL, mpc85xx_ids, NULL); 423 424 return 0; 425 } 426 427 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 428 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); 429 machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices); 430 431 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); 432 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); 433 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier); 434 435 static void __init mpc85xx_mds_pic_init(void) 436 { 437 struct mpic *mpic = mpic_alloc(NULL, 0, 438 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | 439 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, 440 0, 256, " OpenPIC "); 441 BUG_ON(mpic == NULL); 442 443 mpic_init(mpic); 444 mpc85xx_mds_qeic_init(); 445 } 446 447 static int __init mpc85xx_mds_probe(void) 448 { 449 unsigned long root = of_get_flat_dt_root(); 450 451 return of_flat_dt_is_compatible(root, "MPC85xxMDS"); 452 } 453 454 define_machine(mpc8568_mds) { 455 .name = "MPC8568 MDS", 456 .probe = mpc85xx_mds_probe, 457 .setup_arch = mpc85xx_mds_setup_arch, 458 .init_IRQ = mpc85xx_mds_pic_init, 459 .get_irq = mpic_get_irq, 460 .restart = fsl_rstcr_restart, 461 .calibrate_decr = generic_calibrate_decr, 462 .progress = udbg_progress, 463 #ifdef CONFIG_PCI 464 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 465 #endif 466 }; 467 468 static int __init mpc8569_mds_probe(void) 469 { 470 unsigned long root = of_get_flat_dt_root(); 471 472 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS"); 473 } 474 475 define_machine(mpc8569_mds) { 476 .name = "MPC8569 MDS", 477 .probe = mpc8569_mds_probe, 478 .setup_arch = mpc85xx_mds_setup_arch, 479 .init_IRQ = mpc85xx_mds_pic_init, 480 .get_irq = mpic_get_irq, 481 .restart = fsl_rstcr_restart, 482 .calibrate_decr = generic_calibrate_decr, 483 .progress = udbg_progress, 484 #ifdef CONFIG_PCI 485 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 486 #endif 487 }; 488 489 static int __init p1021_mds_probe(void) 490 { 491 unsigned long root = of_get_flat_dt_root(); 492 493 return of_flat_dt_is_compatible(root, "fsl,P1021MDS"); 494 495 } 496 497 define_machine(p1021_mds) { 498 .name = "P1021 MDS", 499 .probe = p1021_mds_probe, 500 .setup_arch = mpc85xx_mds_setup_arch, 501 .init_IRQ = mpc85xx_mds_pic_init, 502 .get_irq = mpic_get_irq, 503 .restart = fsl_rstcr_restart, 504 .calibrate_decr = generic_calibrate_decr, 505 .progress = udbg_progress, 506 #ifdef CONFIG_PCI 507 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 508 #endif 509 }; 510 511