1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx DS Board Setup 4 * 5 * Author Xianghua Xiao (x.xiao@freescale.com) 6 * Roy Zang <tie-fei.zang@freescale.com> 7 * - Add PCI/PCI Exprees support 8 * Copyright 2007 Freescale Semiconductor Inc. 9 */ 10 11 #include <linux/stddef.h> 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/kdev_t.h> 15 #include <linux/delay.h> 16 #include <linux/seq_file.h> 17 #include <linux/interrupt.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_platform.h> 20 21 #include <asm/time.h> 22 #include <asm/machdep.h> 23 #include <asm/pci-bridge.h> 24 #include <mm/mmu_decl.h> 25 #include <asm/udbg.h> 26 #include <asm/mpic.h> 27 #include <asm/i8259.h> 28 #include <asm/swiotlb.h> 29 #include <asm/ppc-pci.h> 30 31 #include <sysdev/fsl_soc.h> 32 #include <sysdev/fsl_pci.h> 33 #include "smp.h" 34 35 #include "mpc85xx.h" 36 37 static void mpc85xx_8259_cascade(struct irq_desc *desc) 38 { 39 struct irq_chip *chip = irq_desc_get_chip(desc); 40 unsigned int cascade_irq = i8259_irq(); 41 42 if (cascade_irq) { 43 generic_handle_irq(cascade_irq); 44 } 45 chip->irq_eoi(&desc->irq_data); 46 } 47 48 static void __init mpc85xx_8259_init(void) 49 { 50 struct device_node *np; 51 struct device_node *cascade_node = NULL; 52 int cascade_irq; 53 54 if (!IS_ENABLED(CONFIG_PPC_I8259)) 55 return; 56 57 /* Initialize the i8259 controller */ 58 for_each_node_by_type(np, "interrupt-controller") 59 if (of_device_is_compatible(np, "chrp,iic")) { 60 cascade_node = np; 61 break; 62 } 63 64 if (cascade_node == NULL) { 65 pr_debug("Could not find i8259 PIC\n"); 66 return; 67 } 68 69 cascade_irq = irq_of_parse_and_map(cascade_node, 0); 70 if (!cascade_irq) { 71 pr_err("Failed to map cascade interrupt\n"); 72 return; 73 } 74 75 pr_debug("mpc85xxds: cascade mapped to irq %d\n", cascade_irq); 76 77 i8259_init(cascade_node, 0); 78 of_node_put(cascade_node); 79 80 irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade); 81 } 82 83 void __init mpc85xx_ds_pic_init(void) 84 { 85 struct mpic *mpic; 86 int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU; 87 88 if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) 89 flags |= MPIC_NO_RESET; 90 91 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); 92 93 if (WARN_ON(!mpic)) 94 return; 95 96 mpic_init(mpic); 97 98 mpc85xx_8259_init(); 99 } 100 101 /* 102 * Setup the architecture 103 */ 104 void __init mpc85xx_ds_setup_arch(void) 105 { 106 if (ppc_md.progress) 107 ppc_md.progress("mpc85xx_ds_setup_arch()", 0); 108 109 swiotlb_detect_4g(); 110 fsl_pci_assign_primary(); 111 uli_init(); 112 mpc85xx_smp_init(); 113 114 pr_info("MPC85xx DS board from Freescale Semiconductor\n"); 115 } 116 117 machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices); 118 machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices); 119 120 define_machine(mpc8544_ds) { 121 .name = "MPC8544 DS", 122 .compatible = "MPC8544DS", 123 .setup_arch = mpc85xx_ds_setup_arch, 124 .init_IRQ = mpc85xx_ds_pic_init, 125 #ifdef CONFIG_PCI 126 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 127 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 128 #endif 129 .get_irq = mpic_get_irq, 130 .progress = udbg_progress, 131 }; 132 133 define_machine(mpc8572_ds) { 134 .name = "MPC8572 DS", 135 .compatible = "fsl,MPC8572DS", 136 .setup_arch = mpc85xx_ds_setup_arch, 137 .init_IRQ = mpc85xx_ds_pic_init, 138 #ifdef CONFIG_PCI 139 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 140 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 141 #endif 142 .get_irq = mpic_get_irq, 143 .progress = udbg_progress, 144 }; 145