1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * misc setup functions for MPC83xx 4 * 5 * Maintainer: Kumar Gala <galak@kernel.crashing.org> 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/of_platform.h> 11 #include <linux/pci.h> 12 13 #include <asm/debug.h> 14 #include <asm/io.h> 15 #include <asm/hw_irq.h> 16 #include <asm/ipic.h> 17 #include <asm/fixmap.h> 18 19 #include <sysdev/fsl_soc.h> 20 #include <sysdev/fsl_pci.h> 21 22 #include <mm/mmu_decl.h> 23 24 #include "mpc83xx.h" 25 26 static __be32 __iomem *restart_reg_base; 27 28 static int __init mpc83xx_restart_init(void) 29 { 30 /* map reset restart_reg_baseister space */ 31 restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff); 32 33 return 0; 34 } 35 36 arch_initcall(mpc83xx_restart_init); 37 38 void __noreturn mpc83xx_restart(char *cmd) 39 { 40 #define RST_OFFSET 0x00000900 41 #define RST_PROT_REG 0x00000018 42 #define RST_CTRL_REG 0x0000001c 43 44 local_irq_disable(); 45 46 if (restart_reg_base) { 47 /* enable software reset "RSTE" */ 48 out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445); 49 50 /* set software hard reset */ 51 out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2); 52 } else { 53 printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n"); 54 } 55 56 for (;;) ; 57 } 58 59 long __init mpc83xx_time_init(void) 60 { 61 #define SPCR_OFFSET 0x00000110 62 #define SPCR_TBEN 0x00400000 63 __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4); 64 __be32 tmp; 65 66 tmp = in_be32(spcr); 67 out_be32(spcr, tmp | SPCR_TBEN); 68 69 iounmap(spcr); 70 71 return 0; 72 } 73 74 void __init mpc83xx_ipic_init_IRQ(void) 75 { 76 struct device_node *np; 77 78 /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */ 79 np = of_find_compatible_node(NULL, NULL, "fsl,ipic"); 80 if (!np) 81 np = of_find_node_by_type(NULL, "ipic"); 82 if (!np) 83 return; 84 85 ipic_init(np, 0); 86 87 of_node_put(np); 88 89 /* Initialize the default interrupt mapping priorities, 90 * in case the boot rom changed something on us. 91 */ 92 ipic_set_default_priority(); 93 } 94 95 static const struct of_device_id of_bus_ids[] __initconst = { 96 { .type = "soc", }, 97 { .compatible = "soc", }, 98 { .compatible = "simple-bus" }, 99 { .compatible = "gianfar" }, 100 { .compatible = "gpio-leds", }, 101 { .type = "qe", }, 102 { .compatible = "fsl,qe", }, 103 {}, 104 }; 105 106 int __init mpc83xx_declare_of_platform_devices(void) 107 { 108 of_platform_bus_probe(NULL, of_bus_ids, NULL); 109 return 0; 110 } 111 112 #ifdef CONFIG_PCI 113 void __init mpc83xx_setup_pci(void) 114 { 115 struct device_node *np; 116 117 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") 118 mpc83xx_add_bridge(np); 119 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") 120 mpc83xx_add_bridge(np); 121 } 122 #endif 123 124 void __init mpc83xx_setup_arch(void) 125 { 126 phys_addr_t immrbase = get_immrbase(); 127 int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M; 128 unsigned long va = fix_to_virt(FIX_IMMR_BASE); 129 130 if (ppc_md.progress) 131 ppc_md.progress("mpc83xx_setup_arch()", 0); 132 133 setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG); 134 update_bats(); 135 } 136 137 int machine_check_83xx(struct pt_regs *regs) 138 { 139 u32 mask = 1 << (31 - IPIC_MCP_WDT); 140 141 if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask)) 142 return machine_check_generic(regs); 143 ipic_clear_mcp_status(mask); 144 145 if (debugger_fault_handler(regs)) 146 return 1; 147 148 die("Watchdog NMI Reset", regs, 0); 149 150 return 1; 151 } 152