1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/init.h> 3 #include <linux/suspend.h> 4 #include <linux/io.h> 5 #include <asm/time.h> 6 #include <asm/cacheflush.h> 7 #include <asm/mpc52xx.h> 8 9 /* these are defined in mpc52xx_sleep.S, and only used here */ 10 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs, 11 struct mpc52xx_cdm __iomem *, struct mpc52xx_intr __iomem*); 12 extern void mpc52xx_ds_sram(void); 13 extern const long mpc52xx_ds_sram_size; 14 extern void mpc52xx_ds_cached(void); 15 extern const long mpc52xx_ds_cached_size; 16 17 static void __iomem *mbar; 18 static void __iomem *sdram; 19 static struct mpc52xx_cdm __iomem *cdm; 20 static struct mpc52xx_intr __iomem *intr; 21 static struct mpc52xx_gpio_wkup __iomem *gpiow; 22 static void __iomem *sram; 23 static int sram_size; 24 25 struct mpc52xx_suspend mpc52xx_suspend; 26 27 static int mpc52xx_pm_valid(suspend_state_t state) 28 { 29 switch (state) { 30 case PM_SUSPEND_STANDBY: 31 return 1; 32 default: 33 return 0; 34 } 35 } 36 37 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level) 38 { 39 u16 tmp; 40 41 /* enable gpio */ 42 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); 43 /* set as input */ 44 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); 45 /* enable deep sleep interrupt */ 46 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); 47 /* low/high level creates wakeup interrupt */ 48 tmp = in_be16(&gpiow->wkup_itype); 49 tmp &= ~(0x3 << (pin * 2)); 50 tmp |= (!level + 1) << (pin * 2); 51 out_be16(&gpiow->wkup_itype, tmp); 52 /* master enable */ 53 out_8(&gpiow->wkup_maste, 1); 54 55 return 0; 56 } 57 58 int mpc52xx_pm_prepare(void) 59 { 60 struct device_node *np; 61 const struct of_device_id immr_ids[] = { 62 { .compatible = "fsl,mpc5200-immr", }, 63 { .compatible = "fsl,mpc5200b-immr", }, 64 { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */ 65 { .type = "builtin", .compatible = "mpc5200", }, /* efika */ 66 {} 67 }; 68 struct resource res; 69 70 /* map the whole register space */ 71 np = of_find_matching_node(NULL, immr_ids); 72 73 if (of_address_to_resource(np, 0, &res)) { 74 pr_err("mpc52xx_pm_prepare(): could not get IMMR address\n"); 75 of_node_put(np); 76 return -ENOSYS; 77 } 78 79 mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */ 80 81 of_node_put(np); 82 if (!mbar) { 83 pr_err("mpc52xx_pm_prepare(): could not map registers\n"); 84 return -ENOSYS; 85 } 86 /* these offsets are from mpc5200 users manual */ 87 sdram = mbar + 0x100; 88 cdm = mbar + 0x200; 89 intr = mbar + 0x500; 90 gpiow = mbar + 0xc00; 91 sram = mbar + 0x8000; /* Those will be handled by the */ 92 sram_size = 0x4000; /* bestcomm driver soon */ 93 94 /* call board suspend code, if applicable */ 95 if (mpc52xx_suspend.board_suspend_prepare) 96 mpc52xx_suspend.board_suspend_prepare(mbar); 97 else { 98 printk(KERN_ALERT "%s: %i don't know how to wake up the board\n", 99 __func__, __LINE__); 100 goto out_unmap; 101 } 102 103 return 0; 104 105 out_unmap: 106 iounmap(mbar); 107 return -ENOSYS; 108 } 109 110 111 char saved_sram[0x4000]; 112 113 int mpc52xx_pm_enter(suspend_state_t state) 114 { 115 u32 clk_enables; 116 u32 msr, hid0; 117 u32 intr_main_mask; 118 void __iomem * irq_0x500 = (void __iomem *)CONFIG_KERNEL_START + 0x500; 119 unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size; 120 char saved_0x500[mpc52xx_ds_cached_size]; 121 122 /* disable all interrupts in PIC */ 123 intr_main_mask = in_be32(&intr->main_mask); 124 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff); 125 126 /* don't let DEC expire any time soon */ 127 mtspr(SPRN_DEC, 0x7fffffff); 128 129 /* save SRAM */ 130 memcpy(saved_sram, sram, sram_size); 131 132 /* copy low level suspend code to sram */ 133 memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size); 134 135 out_8(&cdm->ccs_sleep_enable, 1); 136 out_8(&cdm->osc_sleep_enable, 1); 137 out_8(&cdm->ccs_qreq_test, 1); 138 139 /* disable all but SDRAM and bestcomm (SRAM) clocks */ 140 clk_enables = in_be32(&cdm->clk_enables); 141 out_be32(&cdm->clk_enables, clk_enables & 0x00088000); 142 143 /* disable power management */ 144 msr = mfmsr(); 145 mtmsr(msr & ~MSR_POW); 146 147 /* enable sleep mode, disable others */ 148 hid0 = mfspr(SPRN_HID0); 149 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP); 150 151 /* save original, copy our irq handler, flush from dcache and invalidate icache */ 152 memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size); 153 memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size); 154 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop); 155 156 /* call low-level sleep code */ 157 mpc52xx_deep_sleep(sram, sdram, cdm, intr); 158 159 /* restore original irq handler */ 160 memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size); 161 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop); 162 163 /* restore old power mode */ 164 mtmsr(msr & ~MSR_POW); 165 mtspr(SPRN_HID0, hid0); 166 mtmsr(msr); 167 168 out_be32(&cdm->clk_enables, clk_enables); 169 out_8(&cdm->ccs_sleep_enable, 0); 170 out_8(&cdm->osc_sleep_enable, 0); 171 172 /* restore SRAM */ 173 memcpy(sram, saved_sram, sram_size); 174 175 /* reenable interrupts in PIC */ 176 out_be32(&intr->main_mask, intr_main_mask); 177 178 return 0; 179 } 180 181 void mpc52xx_pm_finish(void) 182 { 183 /* call board resume code */ 184 if (mpc52xx_suspend.board_resume_finish) 185 mpc52xx_suspend.board_resume_finish(mbar); 186 187 iounmap(mbar); 188 } 189 190 static const struct platform_suspend_ops mpc52xx_pm_ops = { 191 .valid = mpc52xx_pm_valid, 192 .prepare = mpc52xx_pm_prepare, 193 .enter = mpc52xx_pm_enter, 194 .finish = mpc52xx_pm_finish, 195 }; 196 197 int __init mpc52xx_pm_init(void) 198 { 199 suspend_set_ops(&mpc52xx_pm_ops); 200 return 0; 201 } 202