1 /* 2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: John Rigby <jrigby@freescale.com> 5 * 6 * Description: 7 * MPC512x Shared code 8 * 9 * This is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/of_platform.h> 19 #include <linux/fsl-diu-fb.h> 20 #include <linux/bootmem.h> 21 #include <sysdev/fsl_soc.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/machdep.h> 25 #include <asm/ipic.h> 26 #include <asm/prom.h> 27 #include <asm/time.h> 28 #include <asm/mpc5121.h> 29 #include <asm/mpc52xx_psc.h> 30 31 #include "mpc512x.h" 32 33 static struct mpc512x_reset_module __iomem *reset_module_base; 34 35 static void __init mpc512x_restart_init(void) 36 { 37 struct device_node *np; 38 39 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset"); 40 if (!np) 41 return; 42 43 reset_module_base = of_iomap(np, 0); 44 of_node_put(np); 45 } 46 47 void mpc512x_restart(char *cmd) 48 { 49 if (reset_module_base) { 50 /* Enable software reset "RSTE" */ 51 out_be32(&reset_module_base->rpr, 0x52535445); 52 /* Set software hard reset */ 53 out_be32(&reset_module_base->rcr, 0x2); 54 } else { 55 pr_err("Restart module not mapped.\n"); 56 } 57 for (;;) 58 ; 59 } 60 61 struct fsl_diu_shared_fb { 62 u8 gamma[0x300]; /* 32-bit aligned! */ 63 struct diu_ad ad0; /* 32-bit aligned! */ 64 phys_addr_t fb_phys; 65 size_t fb_len; 66 bool in_use; 67 }; 68 69 u32 mpc512x_get_pixel_format(enum fsl_diu_monitor_port port, 70 unsigned int bits_per_pixel) 71 { 72 switch (bits_per_pixel) { 73 case 32: 74 return 0x88883316; 75 case 24: 76 return 0x88082219; 77 case 16: 78 return 0x65053118; 79 } 80 return 0x00000400; 81 } 82 83 void mpc512x_set_gamma_table(enum fsl_diu_monitor_port port, 84 char *gamma_table_base) 85 { 86 } 87 88 void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port) 89 { 90 } 91 92 #define DIU_DIV_MASK 0x000000ff 93 void mpc512x_set_pixel_clock(unsigned int pixclock) 94 { 95 unsigned long bestval, bestfreq, speed, busfreq; 96 unsigned long minpixclock, maxpixclock, pixval; 97 struct mpc512x_ccm __iomem *ccm; 98 struct device_node *np; 99 u32 temp; 100 long err; 101 int i; 102 103 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock"); 104 if (!np) { 105 pr_err("Can't find clock control module.\n"); 106 return; 107 } 108 109 ccm = of_iomap(np, 0); 110 of_node_put(np); 111 if (!ccm) { 112 pr_err("Can't map clock control module reg.\n"); 113 return; 114 } 115 116 np = of_find_node_by_type(NULL, "cpu"); 117 if (np) { 118 const unsigned int *prop = 119 of_get_property(np, "bus-frequency", NULL); 120 121 of_node_put(np); 122 if (prop) { 123 busfreq = *prop; 124 } else { 125 pr_err("Can't get bus-frequency property\n"); 126 return; 127 } 128 } else { 129 pr_err("Can't find 'cpu' node.\n"); 130 return; 131 } 132 133 /* Pixel Clock configuration */ 134 pr_debug("DIU: Bus Frequency = %lu\n", busfreq); 135 speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */ 136 137 /* Calculate the pixel clock with the smallest error */ 138 /* calculate the following in steps to avoid overflow */ 139 pr_debug("DIU pixclock in ps - %d\n", pixclock); 140 temp = (1000000000 / pixclock) * 1000; 141 pixclock = temp; 142 pr_debug("DIU pixclock freq - %u\n", pixclock); 143 144 temp = temp / 20; /* pixclock * 0.05 */ 145 pr_debug("deviation = %d\n", temp); 146 minpixclock = pixclock - temp; 147 maxpixclock = pixclock + temp; 148 pr_debug("DIU minpixclock - %lu\n", minpixclock); 149 pr_debug("DIU maxpixclock - %lu\n", maxpixclock); 150 pixval = speed/pixclock; 151 pr_debug("DIU pixval = %lu\n", pixval); 152 153 err = LONG_MAX; 154 bestval = pixval; 155 pr_debug("DIU bestval = %lu\n", bestval); 156 157 bestfreq = 0; 158 for (i = -1; i <= 1; i++) { 159 temp = speed / (pixval+i); 160 pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n", 161 i, pixval, temp); 162 if ((temp < minpixclock) || (temp > maxpixclock)) 163 pr_debug("DIU exceeds monitor range (%lu to %lu)\n", 164 minpixclock, maxpixclock); 165 else if (abs(temp - pixclock) < err) { 166 pr_debug("Entered the else if block %d\n", i); 167 err = abs(temp - pixclock); 168 bestval = pixval + i; 169 bestfreq = temp; 170 } 171 } 172 173 pr_debug("DIU chose = %lx\n", bestval); 174 pr_debug("DIU error = %ld\n NomPixClk ", err); 175 pr_debug("DIU: Best Freq = %lx\n", bestfreq); 176 /* Modify DIU_DIV in CCM SCFR1 */ 177 temp = in_be32(&ccm->scfr1); 178 pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp); 179 temp &= ~DIU_DIV_MASK; 180 temp |= (bestval & DIU_DIV_MASK); 181 out_be32(&ccm->scfr1, temp); 182 pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp); 183 iounmap(ccm); 184 } 185 186 enum fsl_diu_monitor_port 187 mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port) 188 { 189 return FSL_DIU_PORT_DVI; 190 } 191 192 static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb; 193 194 static inline void mpc512x_free_bootmem(struct page *page) 195 { 196 __ClearPageReserved(page); 197 BUG_ON(PageTail(page)); 198 BUG_ON(atomic_read(&page->_count) > 1); 199 atomic_set(&page->_count, 1); 200 __free_page(page); 201 totalram_pages++; 202 } 203 204 void mpc512x_release_bootmem(void) 205 { 206 unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK; 207 unsigned long size = diu_shared_fb.fb_len; 208 unsigned long start, end; 209 210 if (diu_shared_fb.in_use) { 211 start = PFN_UP(addr); 212 end = PFN_DOWN(addr + size); 213 214 for (; start < end; start++) 215 mpc512x_free_bootmem(pfn_to_page(start)); 216 217 diu_shared_fb.in_use = false; 218 } 219 diu_ops.release_bootmem = NULL; 220 } 221 222 /* 223 * Check if DIU was pre-initialized. If so, perform steps 224 * needed to continue displaying through the whole boot process. 225 * Move area descriptor and gamma table elsewhere, they are 226 * destroyed by bootmem allocator otherwise. The frame buffer 227 * address range will be reserved in setup_arch() after bootmem 228 * allocator is up. 229 */ 230 void __init mpc512x_init_diu(void) 231 { 232 struct device_node *np; 233 struct diu __iomem *diu_reg; 234 phys_addr_t desc; 235 void __iomem *vaddr; 236 unsigned long mode, pix_fmt, res, bpp; 237 unsigned long dst; 238 239 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); 240 if (!np) { 241 pr_err("No DIU node\n"); 242 return; 243 } 244 245 diu_reg = of_iomap(np, 0); 246 of_node_put(np); 247 if (!diu_reg) { 248 pr_err("Can't map DIU\n"); 249 return; 250 } 251 252 mode = in_be32(&diu_reg->diu_mode); 253 if (mode == MFB_MODE0) { 254 pr_info("%s: DIU OFF\n", __func__); 255 goto out; 256 } 257 258 desc = in_be32(&diu_reg->desc[0]); 259 vaddr = ioremap(desc, sizeof(struct diu_ad)); 260 if (!vaddr) { 261 pr_err("Can't map DIU area desc.\n"); 262 goto out; 263 } 264 memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad)); 265 /* flush fb area descriptor */ 266 dst = (unsigned long)&diu_shared_fb.ad0; 267 flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1); 268 269 res = in_be32(&diu_reg->disp_size); 270 pix_fmt = in_le32(vaddr); 271 bpp = ((pix_fmt >> 16) & 0x3) + 1; 272 diu_shared_fb.fb_phys = in_le32(vaddr + 4); 273 diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp; 274 diu_shared_fb.in_use = true; 275 iounmap(vaddr); 276 277 desc = in_be32(&diu_reg->gamma); 278 vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma)); 279 if (!vaddr) { 280 pr_err("Can't map DIU area desc.\n"); 281 diu_shared_fb.in_use = false; 282 goto out; 283 } 284 memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma)); 285 /* flush gamma table */ 286 dst = (unsigned long)&diu_shared_fb.gamma; 287 flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1); 288 289 iounmap(vaddr); 290 out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma)); 291 out_be32(&diu_reg->desc[1], 0); 292 out_be32(&diu_reg->desc[2], 0); 293 out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0)); 294 295 out: 296 iounmap(diu_reg); 297 } 298 299 void __init mpc512x_setup_diu(void) 300 { 301 int ret; 302 303 /* 304 * We do not allocate and configure new area for bitmap buffer 305 * because it would requere copying bitmap data (splash image) 306 * and so negatively affect boot time. Instead we reserve the 307 * already configured frame buffer area so that it won't be 308 * destroyed. The starting address of the area to reserve and 309 * also it's length is passed to reserve_bootmem(). It will be 310 * freed later on first open of fbdev, when splash image is not 311 * needed any more. 312 */ 313 if (diu_shared_fb.in_use) { 314 ret = reserve_bootmem(diu_shared_fb.fb_phys, 315 diu_shared_fb.fb_len, 316 BOOTMEM_EXCLUSIVE); 317 if (ret) { 318 pr_err("%s: reserve bootmem failed\n", __func__); 319 diu_shared_fb.in_use = false; 320 } 321 } 322 323 diu_ops.get_pixel_format = mpc512x_get_pixel_format; 324 diu_ops.set_gamma_table = mpc512x_set_gamma_table; 325 diu_ops.set_monitor_port = mpc512x_set_monitor_port; 326 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; 327 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; 328 diu_ops.release_bootmem = mpc512x_release_bootmem; 329 } 330 331 void __init mpc512x_init_IRQ(void) 332 { 333 struct device_node *np; 334 335 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic"); 336 if (!np) 337 return; 338 339 ipic_init(np, 0); 340 of_node_put(np); 341 342 /* 343 * Initialize the default interrupt mapping priorities, 344 * in case the boot rom changed something on us. 345 */ 346 ipic_set_default_priority(); 347 } 348 349 /* 350 * Nodes to do bus probe on, soc and localbus 351 */ 352 static struct of_device_id __initdata of_bus_ids[] = { 353 { .compatible = "fsl,mpc5121-immr", }, 354 { .compatible = "fsl,mpc5121-localbus", }, 355 {}, 356 }; 357 358 void __init mpc512x_declare_of_platform_devices(void) 359 { 360 struct device_node *np; 361 362 if (of_platform_bus_probe(NULL, of_bus_ids, NULL)) 363 printk(KERN_ERR __FILE__ ": " 364 "Error while probing of_platform bus\n"); 365 366 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-nfc"); 367 if (np) { 368 of_platform_device_create(np, NULL, NULL); 369 of_node_put(np); 370 } 371 } 372 373 #define DEFAULT_FIFO_SIZE 16 374 375 static unsigned int __init get_fifo_size(struct device_node *np, 376 char *prop_name) 377 { 378 const unsigned int *fp; 379 380 fp = of_get_property(np, prop_name, NULL); 381 if (fp) 382 return *fp; 383 384 pr_warning("no %s property in %s node, defaulting to %d\n", 385 prop_name, np->full_name, DEFAULT_FIFO_SIZE); 386 387 return DEFAULT_FIFO_SIZE; 388 } 389 390 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \ 391 ((u32)(_base) + sizeof(struct mpc52xx_psc))) 392 393 /* Init PSC FIFO space for TX and RX slices */ 394 void __init mpc512x_psc_fifo_init(void) 395 { 396 struct device_node *np; 397 void __iomem *psc; 398 unsigned int tx_fifo_size; 399 unsigned int rx_fifo_size; 400 int fifobase = 0; /* current fifo address in 32 bit words */ 401 402 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") { 403 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size"); 404 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size"); 405 406 /* size in register is in 4 byte units */ 407 tx_fifo_size /= 4; 408 rx_fifo_size /= 4; 409 if (!tx_fifo_size) 410 tx_fifo_size = 1; 411 if (!rx_fifo_size) 412 rx_fifo_size = 1; 413 414 psc = of_iomap(np, 0); 415 if (!psc) { 416 pr_err("%s: Can't map %s device\n", 417 __func__, np->full_name); 418 continue; 419 } 420 421 /* FIFO space is 4KiB, check if requested size is available */ 422 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) { 423 pr_err("%s: no fifo space available for %s\n", 424 __func__, np->full_name); 425 iounmap(psc); 426 /* 427 * chances are that another device requests less 428 * fifo space, so we continue. 429 */ 430 continue; 431 } 432 433 /* set tx and rx fifo size registers */ 434 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size); 435 fifobase += tx_fifo_size; 436 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size); 437 fifobase += rx_fifo_size; 438 439 /* reset and enable the slices */ 440 out_be32(&FIFOC(psc)->txcmd, 0x80); 441 out_be32(&FIFOC(psc)->txcmd, 0x01); 442 out_be32(&FIFOC(psc)->rxcmd, 0x80); 443 out_be32(&FIFOC(psc)->rxcmd, 0x01); 444 445 iounmap(psc); 446 } 447 } 448 449 void __init mpc512x_init(void) 450 { 451 mpc512x_declare_of_platform_devices(); 452 mpc5121_clk_init(); 453 mpc512x_restart_init(); 454 mpc512x_psc_fifo_init(); 455 } 456