1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Author: John Rigby <jrigby@freescale.com> 6 * 7 * Description: 8 * MPC512x Shared code 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/kernel.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/of_address.h> 16 #include <linux/of_platform.h> 17 #include <linux/fsl-diu-fb.h> 18 #include <linux/memblock.h> 19 #include <sysdev/fsl_soc.h> 20 21 #include <asm/cacheflush.h> 22 #include <asm/machdep.h> 23 #include <asm/ipic.h> 24 #include <asm/time.h> 25 #include <asm/mpc5121.h> 26 #include <asm/mpc52xx_psc.h> 27 28 #include "mpc512x.h" 29 30 static struct mpc512x_reset_module __iomem *reset_module_base; 31 32 static void __init mpc512x_restart_init(void) 33 { 34 struct device_node *np; 35 const char *reset_compat; 36 37 reset_compat = mpc512x_select_reset_compat(); 38 np = of_find_compatible_node(NULL, NULL, reset_compat); 39 if (!np) 40 return; 41 42 reset_module_base = of_iomap(np, 0); 43 of_node_put(np); 44 } 45 46 void __noreturn mpc512x_restart(char *cmd) 47 { 48 if (reset_module_base) { 49 /* Enable software reset "RSTE" */ 50 out_be32(&reset_module_base->rpr, 0x52535445); 51 /* Set software hard reset */ 52 out_be32(&reset_module_base->rcr, 0x2); 53 } else { 54 pr_err("Restart module not mapped.\n"); 55 } 56 for (;;) 57 ; 58 } 59 60 struct fsl_diu_shared_fb { 61 u8 gamma[0x300]; /* 32-bit aligned! */ 62 struct diu_ad ad0; /* 32-bit aligned! */ 63 phys_addr_t fb_phys; 64 size_t fb_len; 65 bool in_use; 66 }; 67 68 /* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */ 69 static void mpc512x_set_pixel_clock(unsigned int pixclock) 70 { 71 struct device_node *np; 72 struct clk *clk_diu; 73 unsigned long epsilon, minpixclock, maxpixclock; 74 unsigned long offset, want, got, delta; 75 76 /* lookup and enable the DIU clock */ 77 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); 78 if (!np) { 79 pr_err("Could not find DIU device tree node.\n"); 80 return; 81 } 82 clk_diu = of_clk_get(np, 0); 83 if (IS_ERR(clk_diu)) { 84 /* backwards compat with device trees that lack clock specs */ 85 clk_diu = clk_get_sys(np->name, "ipg"); 86 } 87 of_node_put(np); 88 if (IS_ERR(clk_diu)) { 89 pr_err("Could not lookup DIU clock.\n"); 90 return; 91 } 92 if (clk_prepare_enable(clk_diu)) { 93 pr_err("Could not enable DIU clock.\n"); 94 return; 95 } 96 97 /* 98 * convert the picoseconds spec into the desired clock rate, 99 * determine the acceptable clock range for the monitor (+/- 5%), 100 * do the calculation in steps to avoid integer overflow 101 */ 102 pr_debug("DIU pixclock in ps - %u\n", pixclock); 103 pixclock = (1000000000 / pixclock) * 1000; 104 pr_debug("DIU pixclock freq - %u\n", pixclock); 105 epsilon = pixclock / 20; /* pixclock * 0.05 */ 106 pr_debug("DIU deviation - %lu\n", epsilon); 107 minpixclock = pixclock - epsilon; 108 maxpixclock = pixclock + epsilon; 109 pr_debug("DIU minpixclock - %lu\n", minpixclock); 110 pr_debug("DIU maxpixclock - %lu\n", maxpixclock); 111 112 /* 113 * check whether the DIU supports the desired pixel clock 114 * 115 * - simply request the desired clock and see what the 116 * platform's clock driver will make of it, assuming that it 117 * will setup the best approximation of the requested value 118 * - try other candidate frequencies in the order of decreasing 119 * preference (i.e. with increasing distance from the desired 120 * pixel clock, and checking the lower frequency before the 121 * higher frequency to not overload the hardware) until the 122 * first match is found -- any potential subsequent match 123 * would only be as good as the former match or typically 124 * would be less preferrable 125 * 126 * the offset increment of pixelclock divided by 64 is an 127 * arbitrary choice -- it's simple to calculate, in the typical 128 * case we expect the first check to succeed already, in the 129 * worst case seven frequencies get tested (the exact center and 130 * three more values each to the left and to the right) before 131 * the 5% tolerance window is exceeded, resulting in fast enough 132 * execution yet high enough probability of finding a suitable 133 * value, while the error rate will be in the order of single 134 * percents 135 */ 136 for (offset = 0; offset <= epsilon; offset += pixclock / 64) { 137 want = pixclock - offset; 138 pr_debug("DIU checking clock - %lu\n", want); 139 clk_set_rate(clk_diu, want); 140 got = clk_get_rate(clk_diu); 141 delta = abs(pixclock - got); 142 if (delta < epsilon) 143 break; 144 if (!offset) 145 continue; 146 want = pixclock + offset; 147 pr_debug("DIU checking clock - %lu\n", want); 148 clk_set_rate(clk_diu, want); 149 got = clk_get_rate(clk_diu); 150 delta = abs(pixclock - got); 151 if (delta < epsilon) 152 break; 153 } 154 if (offset <= epsilon) { 155 pr_debug("DIU clock accepted - %lu\n", want); 156 pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n", 157 pixclock, got, delta, epsilon); 158 return; 159 } 160 pr_warn("DIU pixclock auto search unsuccessful\n"); 161 162 /* 163 * what is the most appropriate action to take when the search 164 * for an available pixel clock which is acceptable to the 165 * monitor has failed? disable the DIU (clock) or just provide 166 * a "best effort"? we go with the latter 167 */ 168 pr_warn("DIU pixclock best effort fallback (backend's choice)\n"); 169 clk_set_rate(clk_diu, pixclock); 170 got = clk_get_rate(clk_diu); 171 delta = abs(pixclock - got); 172 pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n", 173 pixclock, got, delta, epsilon); 174 } 175 176 static enum fsl_diu_monitor_port 177 mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port) 178 { 179 return FSL_DIU_PORT_DVI; 180 } 181 182 static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb; 183 184 static inline void mpc512x_free_bootmem(struct page *page) 185 { 186 BUG_ON(PageTail(page)); 187 BUG_ON(page_ref_count(page) > 1); 188 free_reserved_page(page); 189 } 190 191 static void mpc512x_release_bootmem(void) 192 { 193 unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK; 194 unsigned long size = diu_shared_fb.fb_len; 195 unsigned long start, end; 196 197 if (diu_shared_fb.in_use) { 198 start = PFN_UP(addr); 199 end = PFN_DOWN(addr + size); 200 201 for (; start < end; start++) 202 mpc512x_free_bootmem(pfn_to_page(start)); 203 204 diu_shared_fb.in_use = false; 205 } 206 diu_ops.release_bootmem = NULL; 207 } 208 209 /* 210 * Check if DIU was pre-initialized. If so, perform steps 211 * needed to continue displaying through the whole boot process. 212 * Move area descriptor and gamma table elsewhere, they are 213 * destroyed by bootmem allocator otherwise. The frame buffer 214 * address range will be reserved in setup_arch() after bootmem 215 * allocator is up. 216 */ 217 static void __init mpc512x_init_diu(void) 218 { 219 struct device_node *np; 220 struct diu __iomem *diu_reg; 221 phys_addr_t desc; 222 void __iomem *vaddr; 223 unsigned long mode, pix_fmt, res, bpp; 224 unsigned long dst; 225 226 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); 227 if (!np) { 228 pr_err("No DIU node\n"); 229 return; 230 } 231 232 diu_reg = of_iomap(np, 0); 233 of_node_put(np); 234 if (!diu_reg) { 235 pr_err("Can't map DIU\n"); 236 return; 237 } 238 239 mode = in_be32(&diu_reg->diu_mode); 240 if (mode == MFB_MODE0) { 241 pr_info("%s: DIU OFF\n", __func__); 242 goto out; 243 } 244 245 desc = in_be32(&diu_reg->desc[0]); 246 vaddr = ioremap(desc, sizeof(struct diu_ad)); 247 if (!vaddr) { 248 pr_err("Can't map DIU area desc.\n"); 249 goto out; 250 } 251 memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad)); 252 /* flush fb area descriptor */ 253 dst = (unsigned long)&diu_shared_fb.ad0; 254 flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1); 255 256 res = in_be32(&diu_reg->disp_size); 257 pix_fmt = in_le32(vaddr); 258 bpp = ((pix_fmt >> 16) & 0x3) + 1; 259 diu_shared_fb.fb_phys = in_le32(vaddr + 4); 260 diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp; 261 diu_shared_fb.in_use = true; 262 iounmap(vaddr); 263 264 desc = in_be32(&diu_reg->gamma); 265 vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma)); 266 if (!vaddr) { 267 pr_err("Can't map DIU area desc.\n"); 268 diu_shared_fb.in_use = false; 269 goto out; 270 } 271 memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma)); 272 /* flush gamma table */ 273 dst = (unsigned long)&diu_shared_fb.gamma; 274 flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1); 275 276 iounmap(vaddr); 277 out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma)); 278 out_be32(&diu_reg->desc[1], 0); 279 out_be32(&diu_reg->desc[2], 0); 280 out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0)); 281 282 out: 283 iounmap(diu_reg); 284 } 285 286 static void __init mpc512x_setup_diu(void) 287 { 288 int ret; 289 290 /* 291 * We do not allocate and configure new area for bitmap buffer 292 * because it would require copying bitmap data (splash image) 293 * and so negatively affect boot time. Instead we reserve the 294 * already configured frame buffer area so that it won't be 295 * destroyed. The starting address of the area to reserve and 296 * also it's length is passed to memblock_reserve(). It will be 297 * freed later on first open of fbdev, when splash image is not 298 * needed any more. 299 */ 300 if (diu_shared_fb.in_use) { 301 ret = memblock_reserve(diu_shared_fb.fb_phys, 302 diu_shared_fb.fb_len); 303 if (ret) { 304 pr_err("%s: reserve bootmem failed\n", __func__); 305 diu_shared_fb.in_use = false; 306 } 307 } 308 309 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; 310 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; 311 diu_ops.release_bootmem = mpc512x_release_bootmem; 312 } 313 314 void __init mpc512x_init_IRQ(void) 315 { 316 struct device_node *np; 317 318 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic"); 319 if (!np) 320 return; 321 322 ipic_init(np, 0); 323 of_node_put(np); 324 325 /* 326 * Initialize the default interrupt mapping priorities, 327 * in case the boot rom changed something on us. 328 */ 329 ipic_set_default_priority(); 330 } 331 332 /* 333 * Nodes to do bus probe on, soc and localbus 334 */ 335 static const struct of_device_id of_bus_ids[] __initconst = { 336 { .compatible = "fsl,mpc5121-immr", }, 337 { .compatible = "fsl,mpc5121-localbus", }, 338 { .compatible = "fsl,mpc5121-mbx", }, 339 { .compatible = "fsl,mpc5121-nfc", }, 340 { .compatible = "fsl,mpc5121-sram", }, 341 { .compatible = "fsl,mpc5121-pci", }, 342 { .compatible = "gpio-leds", }, 343 {}, 344 }; 345 346 static void __init mpc512x_declare_of_platform_devices(void) 347 { 348 if (of_platform_bus_probe(NULL, of_bus_ids, NULL)) 349 printk(KERN_ERR __FILE__ ": " 350 "Error while probing of_platform bus\n"); 351 } 352 353 #define DEFAULT_FIFO_SIZE 16 354 355 const char *__init mpc512x_select_psc_compat(void) 356 { 357 if (of_machine_is_compatible("fsl,mpc5121")) 358 return "fsl,mpc5121-psc"; 359 360 if (of_machine_is_compatible("fsl,mpc5125")) 361 return "fsl,mpc5125-psc"; 362 363 return NULL; 364 } 365 366 const char *__init mpc512x_select_reset_compat(void) 367 { 368 if (of_machine_is_compatible("fsl,mpc5121")) 369 return "fsl,mpc5121-reset"; 370 371 if (of_machine_is_compatible("fsl,mpc5125")) 372 return "fsl,mpc5125-reset"; 373 374 return NULL; 375 } 376 377 static unsigned int __init get_fifo_size(struct device_node *np, 378 char *prop_name) 379 { 380 const unsigned int *fp; 381 382 fp = of_get_property(np, prop_name, NULL); 383 if (fp) 384 return *fp; 385 386 pr_warn("no %s property in %pOF node, defaulting to %d\n", 387 prop_name, np, DEFAULT_FIFO_SIZE); 388 389 return DEFAULT_FIFO_SIZE; 390 } 391 392 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \ 393 ((u32)(_base) + sizeof(struct mpc52xx_psc))) 394 395 /* Init PSC FIFO space for TX and RX slices */ 396 static void __init mpc512x_psc_fifo_init(void) 397 { 398 struct device_node *np; 399 void __iomem *psc; 400 unsigned int tx_fifo_size; 401 unsigned int rx_fifo_size; 402 const char *psc_compat; 403 int fifobase = 0; /* current fifo address in 32 bit words */ 404 405 psc_compat = mpc512x_select_psc_compat(); 406 if (!psc_compat) { 407 pr_err("%s: no compatible devices found\n", __func__); 408 return; 409 } 410 411 for_each_compatible_node(np, NULL, psc_compat) { 412 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size"); 413 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size"); 414 415 /* size in register is in 4 byte units */ 416 tx_fifo_size /= 4; 417 rx_fifo_size /= 4; 418 if (!tx_fifo_size) 419 tx_fifo_size = 1; 420 if (!rx_fifo_size) 421 rx_fifo_size = 1; 422 423 psc = of_iomap(np, 0); 424 if (!psc) { 425 pr_err("%s: Can't map %pOF device\n", 426 __func__, np); 427 continue; 428 } 429 430 /* FIFO space is 4KiB, check if requested size is available */ 431 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) { 432 pr_err("%s: no fifo space available for %pOF\n", 433 __func__, np); 434 iounmap(psc); 435 /* 436 * chances are that another device requests less 437 * fifo space, so we continue. 438 */ 439 continue; 440 } 441 442 /* set tx and rx fifo size registers */ 443 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size); 444 fifobase += tx_fifo_size; 445 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size); 446 fifobase += rx_fifo_size; 447 448 /* reset and enable the slices */ 449 out_be32(&FIFOC(psc)->txcmd, 0x80); 450 out_be32(&FIFOC(psc)->txcmd, 0x01); 451 out_be32(&FIFOC(psc)->rxcmd, 0x80); 452 out_be32(&FIFOC(psc)->rxcmd, 0x01); 453 454 iounmap(psc); 455 } 456 } 457 458 void __init mpc512x_init_early(void) 459 { 460 mpc512x_restart_init(); 461 if (IS_ENABLED(CONFIG_FB_FSL_DIU)) 462 mpc512x_init_diu(); 463 } 464 465 void __init mpc512x_init(void) 466 { 467 mpc5121_clk_init(); 468 mpc512x_declare_of_platform_devices(); 469 mpc512x_psc_fifo_init(); 470 } 471 472 void __init mpc512x_setup_arch(void) 473 { 474 if (IS_ENABLED(CONFIG_FB_FSL_DIU)) 475 mpc512x_setup_diu(); 476 } 477 478 /** 479 * mpc512x_cs_config - Setup chip select configuration 480 * @cs: chip select number 481 * @val: chip select configuration value 482 * 483 * Perform chip select configuration for devices on LocalPlus Bus. 484 * Intended to dynamically reconfigure the chip select parameters 485 * for configurable devices on the bus. 486 */ 487 int mpc512x_cs_config(unsigned int cs, u32 val) 488 { 489 static struct mpc512x_lpc __iomem *lpc; 490 struct device_node *np; 491 492 if (cs > 7) 493 return -EINVAL; 494 495 if (!lpc) { 496 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-lpc"); 497 lpc = of_iomap(np, 0); 498 of_node_put(np); 499 if (!lpc) 500 return -ENOMEM; 501 } 502 503 out_be32(&lpc->cs_cfg[cs], val); 504 return 0; 505 } 506 EXPORT_SYMBOL(mpc512x_cs_config); 507