1 /* 2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: John Rigby <jrigby@freescale.com> 5 * 6 * Description: 7 * MPC512x Shared code 8 * 9 * This is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/of_platform.h> 19 #include <linux/fsl-diu-fb.h> 20 #include <linux/bootmem.h> 21 #include <sysdev/fsl_soc.h> 22 23 #include <asm/cacheflush.h> 24 #include <asm/machdep.h> 25 #include <asm/ipic.h> 26 #include <asm/prom.h> 27 #include <asm/time.h> 28 #include <asm/mpc5121.h> 29 #include <asm/mpc52xx_psc.h> 30 31 #include "mpc512x.h" 32 33 static struct mpc512x_reset_module __iomem *reset_module_base; 34 35 static void __init mpc512x_restart_init(void) 36 { 37 struct device_node *np; 38 39 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset"); 40 if (!np) 41 return; 42 43 reset_module_base = of_iomap(np, 0); 44 of_node_put(np); 45 } 46 47 void mpc512x_restart(char *cmd) 48 { 49 if (reset_module_base) { 50 /* Enable software reset "RSTE" */ 51 out_be32(&reset_module_base->rpr, 0x52535445); 52 /* Set software hard reset */ 53 out_be32(&reset_module_base->rcr, 0x2); 54 } else { 55 pr_err("Restart module not mapped.\n"); 56 } 57 for (;;) 58 ; 59 } 60 61 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 62 63 struct fsl_diu_shared_fb { 64 u8 gamma[0x300]; /* 32-bit aligned! */ 65 struct diu_ad ad0; /* 32-bit aligned! */ 66 phys_addr_t fb_phys; 67 size_t fb_len; 68 bool in_use; 69 }; 70 71 void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port) 72 { 73 } 74 75 #define DIU_DIV_MASK 0x000000ff 76 void mpc512x_set_pixel_clock(unsigned int pixclock) 77 { 78 unsigned long bestval, bestfreq, speed, busfreq; 79 unsigned long minpixclock, maxpixclock, pixval; 80 struct mpc512x_ccm __iomem *ccm; 81 struct device_node *np; 82 u32 temp; 83 long err; 84 int i; 85 86 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock"); 87 if (!np) { 88 pr_err("Can't find clock control module.\n"); 89 return; 90 } 91 92 ccm = of_iomap(np, 0); 93 of_node_put(np); 94 if (!ccm) { 95 pr_err("Can't map clock control module reg.\n"); 96 return; 97 } 98 99 np = of_find_node_by_type(NULL, "cpu"); 100 if (np) { 101 const unsigned int *prop = 102 of_get_property(np, "bus-frequency", NULL); 103 104 of_node_put(np); 105 if (prop) { 106 busfreq = *prop; 107 } else { 108 pr_err("Can't get bus-frequency property\n"); 109 return; 110 } 111 } else { 112 pr_err("Can't find 'cpu' node.\n"); 113 return; 114 } 115 116 /* Pixel Clock configuration */ 117 pr_debug("DIU: Bus Frequency = %lu\n", busfreq); 118 speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */ 119 120 /* Calculate the pixel clock with the smallest error */ 121 /* calculate the following in steps to avoid overflow */ 122 pr_debug("DIU pixclock in ps - %d\n", pixclock); 123 temp = (1000000000 / pixclock) * 1000; 124 pixclock = temp; 125 pr_debug("DIU pixclock freq - %u\n", pixclock); 126 127 temp = temp / 20; /* pixclock * 0.05 */ 128 pr_debug("deviation = %d\n", temp); 129 minpixclock = pixclock - temp; 130 maxpixclock = pixclock + temp; 131 pr_debug("DIU minpixclock - %lu\n", minpixclock); 132 pr_debug("DIU maxpixclock - %lu\n", maxpixclock); 133 pixval = speed/pixclock; 134 pr_debug("DIU pixval = %lu\n", pixval); 135 136 err = LONG_MAX; 137 bestval = pixval; 138 pr_debug("DIU bestval = %lu\n", bestval); 139 140 bestfreq = 0; 141 for (i = -1; i <= 1; i++) { 142 temp = speed / (pixval+i); 143 pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n", 144 i, pixval, temp); 145 if ((temp < minpixclock) || (temp > maxpixclock)) 146 pr_debug("DIU exceeds monitor range (%lu to %lu)\n", 147 minpixclock, maxpixclock); 148 else if (abs(temp - pixclock) < err) { 149 pr_debug("Entered the else if block %d\n", i); 150 err = abs(temp - pixclock); 151 bestval = pixval + i; 152 bestfreq = temp; 153 } 154 } 155 156 pr_debug("DIU chose = %lx\n", bestval); 157 pr_debug("DIU error = %ld\n NomPixClk ", err); 158 pr_debug("DIU: Best Freq = %lx\n", bestfreq); 159 /* Modify DIU_DIV in CCM SCFR1 */ 160 temp = in_be32(&ccm->scfr1); 161 pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp); 162 temp &= ~DIU_DIV_MASK; 163 temp |= (bestval & DIU_DIV_MASK); 164 out_be32(&ccm->scfr1, temp); 165 pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp); 166 iounmap(ccm); 167 } 168 169 enum fsl_diu_monitor_port 170 mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port) 171 { 172 return FSL_DIU_PORT_DVI; 173 } 174 175 static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb; 176 177 static inline void mpc512x_free_bootmem(struct page *page) 178 { 179 __ClearPageReserved(page); 180 BUG_ON(PageTail(page)); 181 BUG_ON(atomic_read(&page->_count) > 1); 182 atomic_set(&page->_count, 1); 183 __free_page(page); 184 totalram_pages++; 185 } 186 187 void mpc512x_release_bootmem(void) 188 { 189 unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK; 190 unsigned long size = diu_shared_fb.fb_len; 191 unsigned long start, end; 192 193 if (diu_shared_fb.in_use) { 194 start = PFN_UP(addr); 195 end = PFN_DOWN(addr + size); 196 197 for (; start < end; start++) 198 mpc512x_free_bootmem(pfn_to_page(start)); 199 200 diu_shared_fb.in_use = false; 201 } 202 diu_ops.release_bootmem = NULL; 203 } 204 205 /* 206 * Check if DIU was pre-initialized. If so, perform steps 207 * needed to continue displaying through the whole boot process. 208 * Move area descriptor and gamma table elsewhere, they are 209 * destroyed by bootmem allocator otherwise. The frame buffer 210 * address range will be reserved in setup_arch() after bootmem 211 * allocator is up. 212 */ 213 void __init mpc512x_init_diu(void) 214 { 215 struct device_node *np; 216 struct diu __iomem *diu_reg; 217 phys_addr_t desc; 218 void __iomem *vaddr; 219 unsigned long mode, pix_fmt, res, bpp; 220 unsigned long dst; 221 222 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); 223 if (!np) { 224 pr_err("No DIU node\n"); 225 return; 226 } 227 228 diu_reg = of_iomap(np, 0); 229 of_node_put(np); 230 if (!diu_reg) { 231 pr_err("Can't map DIU\n"); 232 return; 233 } 234 235 mode = in_be32(&diu_reg->diu_mode); 236 if (mode == MFB_MODE0) { 237 pr_info("%s: DIU OFF\n", __func__); 238 goto out; 239 } 240 241 desc = in_be32(&diu_reg->desc[0]); 242 vaddr = ioremap(desc, sizeof(struct diu_ad)); 243 if (!vaddr) { 244 pr_err("Can't map DIU area desc.\n"); 245 goto out; 246 } 247 memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad)); 248 /* flush fb area descriptor */ 249 dst = (unsigned long)&diu_shared_fb.ad0; 250 flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1); 251 252 res = in_be32(&diu_reg->disp_size); 253 pix_fmt = in_le32(vaddr); 254 bpp = ((pix_fmt >> 16) & 0x3) + 1; 255 diu_shared_fb.fb_phys = in_le32(vaddr + 4); 256 diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp; 257 diu_shared_fb.in_use = true; 258 iounmap(vaddr); 259 260 desc = in_be32(&diu_reg->gamma); 261 vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma)); 262 if (!vaddr) { 263 pr_err("Can't map DIU area desc.\n"); 264 diu_shared_fb.in_use = false; 265 goto out; 266 } 267 memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma)); 268 /* flush gamma table */ 269 dst = (unsigned long)&diu_shared_fb.gamma; 270 flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1); 271 272 iounmap(vaddr); 273 out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma)); 274 out_be32(&diu_reg->desc[1], 0); 275 out_be32(&diu_reg->desc[2], 0); 276 out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0)); 277 278 out: 279 iounmap(diu_reg); 280 } 281 282 void __init mpc512x_setup_diu(void) 283 { 284 int ret; 285 286 /* 287 * We do not allocate and configure new area for bitmap buffer 288 * because it would requere copying bitmap data (splash image) 289 * and so negatively affect boot time. Instead we reserve the 290 * already configured frame buffer area so that it won't be 291 * destroyed. The starting address of the area to reserve and 292 * also it's length is passed to reserve_bootmem(). It will be 293 * freed later on first open of fbdev, when splash image is not 294 * needed any more. 295 */ 296 if (diu_shared_fb.in_use) { 297 ret = reserve_bootmem(diu_shared_fb.fb_phys, 298 diu_shared_fb.fb_len, 299 BOOTMEM_EXCLUSIVE); 300 if (ret) { 301 pr_err("%s: reserve bootmem failed\n", __func__); 302 diu_shared_fb.in_use = false; 303 } 304 } 305 306 diu_ops.set_monitor_port = mpc512x_set_monitor_port; 307 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; 308 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; 309 diu_ops.release_bootmem = mpc512x_release_bootmem; 310 } 311 312 #endif 313 314 void __init mpc512x_init_IRQ(void) 315 { 316 struct device_node *np; 317 318 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic"); 319 if (!np) 320 return; 321 322 ipic_init(np, 0); 323 of_node_put(np); 324 325 /* 326 * Initialize the default interrupt mapping priorities, 327 * in case the boot rom changed something on us. 328 */ 329 ipic_set_default_priority(); 330 } 331 332 /* 333 * Nodes to do bus probe on, soc and localbus 334 */ 335 static struct of_device_id __initdata of_bus_ids[] = { 336 { .compatible = "fsl,mpc5121-immr", }, 337 { .compatible = "fsl,mpc5121-localbus", }, 338 {}, 339 }; 340 341 void __init mpc512x_declare_of_platform_devices(void) 342 { 343 struct device_node *np; 344 345 if (of_platform_bus_probe(NULL, of_bus_ids, NULL)) 346 printk(KERN_ERR __FILE__ ": " 347 "Error while probing of_platform bus\n"); 348 349 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-nfc"); 350 if (np) { 351 of_platform_device_create(np, NULL, NULL); 352 of_node_put(np); 353 } 354 } 355 356 #define DEFAULT_FIFO_SIZE 16 357 358 static unsigned int __init get_fifo_size(struct device_node *np, 359 char *prop_name) 360 { 361 const unsigned int *fp; 362 363 fp = of_get_property(np, prop_name, NULL); 364 if (fp) 365 return *fp; 366 367 pr_warning("no %s property in %s node, defaulting to %d\n", 368 prop_name, np->full_name, DEFAULT_FIFO_SIZE); 369 370 return DEFAULT_FIFO_SIZE; 371 } 372 373 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \ 374 ((u32)(_base) + sizeof(struct mpc52xx_psc))) 375 376 /* Init PSC FIFO space for TX and RX slices */ 377 void __init mpc512x_psc_fifo_init(void) 378 { 379 struct device_node *np; 380 void __iomem *psc; 381 unsigned int tx_fifo_size; 382 unsigned int rx_fifo_size; 383 int fifobase = 0; /* current fifo address in 32 bit words */ 384 385 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") { 386 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size"); 387 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size"); 388 389 /* size in register is in 4 byte units */ 390 tx_fifo_size /= 4; 391 rx_fifo_size /= 4; 392 if (!tx_fifo_size) 393 tx_fifo_size = 1; 394 if (!rx_fifo_size) 395 rx_fifo_size = 1; 396 397 psc = of_iomap(np, 0); 398 if (!psc) { 399 pr_err("%s: Can't map %s device\n", 400 __func__, np->full_name); 401 continue; 402 } 403 404 /* FIFO space is 4KiB, check if requested size is available */ 405 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) { 406 pr_err("%s: no fifo space available for %s\n", 407 __func__, np->full_name); 408 iounmap(psc); 409 /* 410 * chances are that another device requests less 411 * fifo space, so we continue. 412 */ 413 continue; 414 } 415 416 /* set tx and rx fifo size registers */ 417 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size); 418 fifobase += tx_fifo_size; 419 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size); 420 fifobase += rx_fifo_size; 421 422 /* reset and enable the slices */ 423 out_be32(&FIFOC(psc)->txcmd, 0x80); 424 out_be32(&FIFOC(psc)->txcmd, 0x01); 425 out_be32(&FIFOC(psc)->rxcmd, 0x80); 426 out_be32(&FIFOC(psc)->rxcmd, 0x01); 427 428 iounmap(psc); 429 } 430 } 431 432 void __init mpc512x_init(void) 433 { 434 mpc512x_declare_of_platform_devices(); 435 mpc5121_clk_init(); 436 mpc512x_restart_init(); 437 mpc512x_psc_fifo_init(); 438 } 439