1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PPC4xx gpio driver 4 * 5 * Copyright (c) 2008 Harris Corporation 6 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix 7 * Copyright (c) MontaVista Software, Inc. 2008. 8 * 9 * Author: Steve Falco <sfalco@harris.com> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/spinlock.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/gpio/legacy-of-mm-gpiochip.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/types.h> 20 #include <linux/slab.h> 21 22 #define GPIO_MASK(gpio) (0x80000000 >> (gpio)) 23 #define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2)) 24 25 /* Physical GPIO register layout */ 26 struct ppc4xx_gpio { 27 __be32 or; 28 __be32 tcr; 29 __be32 osrl; 30 __be32 osrh; 31 __be32 tsrl; 32 __be32 tsrh; 33 __be32 odr; 34 __be32 ir; 35 __be32 rr1; 36 __be32 rr2; 37 __be32 rr3; 38 __be32 reserved1; 39 __be32 isr1l; 40 __be32 isr1h; 41 __be32 isr2l; 42 __be32 isr2h; 43 __be32 isr3l; 44 __be32 isr3h; 45 }; 46 47 struct ppc4xx_gpio_chip { 48 struct of_mm_gpio_chip mm_gc; 49 spinlock_t lock; 50 }; 51 52 /* 53 * GPIO LIB API implementation for GPIOs 54 * 55 * There are a maximum of 32 gpios in each gpio controller. 56 */ 57 58 static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio) 59 { 60 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 61 struct ppc4xx_gpio __iomem *regs = mm_gc->regs; 62 63 return !!(in_be32(®s->ir) & GPIO_MASK(gpio)); 64 } 65 66 static inline void 67 __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 68 { 69 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 70 struct ppc4xx_gpio __iomem *regs = mm_gc->regs; 71 72 if (val) 73 setbits32(®s->or, GPIO_MASK(gpio)); 74 else 75 clrbits32(®s->or, GPIO_MASK(gpio)); 76 } 77 78 static int ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 79 { 80 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc); 81 unsigned long flags; 82 83 spin_lock_irqsave(&chip->lock, flags); 84 85 __ppc4xx_gpio_set(gc, gpio, val); 86 87 spin_unlock_irqrestore(&chip->lock, flags); 88 89 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); 90 91 return 0; 92 } 93 94 static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 95 { 96 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 97 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc); 98 struct ppc4xx_gpio __iomem *regs = mm_gc->regs; 99 unsigned long flags; 100 101 spin_lock_irqsave(&chip->lock, flags); 102 103 /* Disable open-drain function */ 104 clrbits32(®s->odr, GPIO_MASK(gpio)); 105 106 /* Float the pin */ 107 clrbits32(®s->tcr, GPIO_MASK(gpio)); 108 109 /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ 110 if (gpio < 16) { 111 clrbits32(®s->osrl, GPIO_MASK2(gpio)); 112 clrbits32(®s->tsrl, GPIO_MASK2(gpio)); 113 } else { 114 clrbits32(®s->osrh, GPIO_MASK2(gpio)); 115 clrbits32(®s->tsrh, GPIO_MASK2(gpio)); 116 } 117 118 spin_unlock_irqrestore(&chip->lock, flags); 119 120 return 0; 121 } 122 123 static int 124 ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 125 { 126 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 127 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc); 128 struct ppc4xx_gpio __iomem *regs = mm_gc->regs; 129 unsigned long flags; 130 131 spin_lock_irqsave(&chip->lock, flags); 132 133 /* First set initial value */ 134 __ppc4xx_gpio_set(gc, gpio, val); 135 136 /* Disable open-drain function */ 137 clrbits32(®s->odr, GPIO_MASK(gpio)); 138 139 /* Drive the pin */ 140 setbits32(®s->tcr, GPIO_MASK(gpio)); 141 142 /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ 143 if (gpio < 16) { 144 clrbits32(®s->osrl, GPIO_MASK2(gpio)); 145 clrbits32(®s->tsrl, GPIO_MASK2(gpio)); 146 } else { 147 clrbits32(®s->osrh, GPIO_MASK2(gpio)); 148 clrbits32(®s->tsrh, GPIO_MASK2(gpio)); 149 } 150 151 spin_unlock_irqrestore(&chip->lock, flags); 152 153 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); 154 155 return 0; 156 } 157 158 static int __init ppc4xx_add_gpiochips(void) 159 { 160 struct device_node *np; 161 162 for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") { 163 int ret; 164 struct ppc4xx_gpio_chip *ppc4xx_gc; 165 struct of_mm_gpio_chip *mm_gc; 166 struct gpio_chip *gc; 167 168 ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL); 169 if (!ppc4xx_gc) { 170 ret = -ENOMEM; 171 goto err; 172 } 173 174 spin_lock_init(&ppc4xx_gc->lock); 175 176 mm_gc = &ppc4xx_gc->mm_gc; 177 gc = &mm_gc->gc; 178 179 gc->ngpio = 32; 180 gc->direction_input = ppc4xx_gpio_dir_in; 181 gc->direction_output = ppc4xx_gpio_dir_out; 182 gc->get = ppc4xx_gpio_get; 183 gc->set = ppc4xx_gpio_set; 184 185 ret = of_mm_gpiochip_add_data(np, mm_gc, ppc4xx_gc); 186 if (ret) 187 goto err; 188 continue; 189 err: 190 pr_err("%pOF: registration failed with status %d\n", np, ret); 191 kfree(ppc4xx_gc); 192 /* try others anyway */ 193 } 194 return 0; 195 } 196 arch_initcall(ppc4xx_add_gpiochips); 197