1 /* 2 * Performance counter support for POWER9 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or later version. 12 */ 13 14 #define pr_fmt(fmt) "power9-pmu: " fmt 15 16 #include "isa207-common.h" 17 18 /* 19 * Raw event encoding for Power9: 20 * 21 * 60 56 52 48 44 40 36 32 22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 23 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] 24 * | | | | | 25 * | | *- IFM (Linux) | thresh start/stop -* 26 * | *- BHRB (Linux) *sm 27 * *- EBB (Linux) 28 * 29 * 28 24 20 16 12 8 4 0 30 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 31 * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ] 32 * | | | | | 33 * | | | | *- mark 34 * | | *- L1/L2/L3 cache_sel | 35 * | | | 36 * | *- sampling mode for marked events *- combine 37 * | 38 * *- thresh_sel 39 * 40 * Below uses IBM bit numbering. 41 * 42 * MMCR1[x:y] = unit (PMCxUNIT) 43 * MMCR1[24] = pmc1combine[0] 44 * MMCR1[25] = pmc1combine[1] 45 * MMCR1[26] = pmc2combine[0] 46 * MMCR1[27] = pmc2combine[1] 47 * MMCR1[28] = pmc3combine[0] 48 * MMCR1[29] = pmc3combine[1] 49 * MMCR1[30] = pmc4combine[0] 50 * MMCR1[31] = pmc4combine[1] 51 * 52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 53 * MMCR1[20:27] = thresh_ctl 54 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 55 * MMCR1[20:27] = thresh_ctl 56 * else 57 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 58 * 59 * if thresh_sel: 60 * MMCRA[45:47] = thresh_sel 61 * 62 * if thresh_cmp: 63 * MMCRA[9:11] = thresh_cmp[0:2] 64 * MMCRA[12:18] = thresh_cmp[3:9] 65 * 66 * MMCR1[16] = cache_sel[2] 67 * MMCR1[17] = cache_sel[3] 68 * 69 * if mark: 70 * MMCRA[63] = 1 (SAMPLE_ENABLE) 71 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 72 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 73 * 74 * if EBB and BHRB: 75 * MMCRA[32:33] = IFM 76 * 77 * MMCRA[SDAR_MODE] = sm 78 */ 79 80 /* 81 * Some power9 event codes. 82 */ 83 #define EVENT(_name, _code) _name = _code, 84 85 enum { 86 #include "power9-events-list.h" 87 }; 88 89 #undef EVENT 90 91 /* MMCRA IFM bits - POWER9 */ 92 #define POWER9_MMCRA_IFM1 0x0000000040000000UL 93 #define POWER9_MMCRA_IFM2 0x0000000080000000UL 94 #define POWER9_MMCRA_IFM3 0x00000000C0000000UL 95 96 /* Nasty Power9 specific hack */ 97 #define PVR_POWER9_CUMULUS 0x00002000 98 99 /* PowerISA v2.07 format attribute structure*/ 100 extern struct attribute_group isa207_pmu_format_group; 101 102 int p9_dd21_bl_ev[] = { 103 PM_MRK_ST_DONE_L2, 104 PM_RADIX_PWC_L1_HIT, 105 PM_FLOP_CMPL, 106 PM_MRK_NTF_FIN, 107 PM_RADIX_PWC_L2_HIT, 108 PM_IFETCH_THROTTLE, 109 PM_MRK_L2_TM_ST_ABORT_SISTER, 110 PM_RADIX_PWC_L3_HIT, 111 PM_RUN_CYC_SMT2_MODE, 112 PM_TM_TX_PASS_RUN_INST, 113 PM_DISP_HELD_SYNC_HOLD, 114 }; 115 116 int p9_dd22_bl_ev[] = { 117 PM_DTLB_MISS_16G, 118 PM_DERAT_MISS_2M, 119 PM_DTLB_MISS_2M, 120 PM_MRK_DTLB_MISS_1G, 121 PM_DTLB_MISS_4K, 122 PM_DERAT_MISS_1G, 123 PM_MRK_DERAT_MISS_2M, 124 PM_MRK_DTLB_MISS_4K, 125 PM_MRK_DTLB_MISS_16G, 126 PM_DTLB_MISS_64K, 127 PM_MRK_DERAT_MISS_1G, 128 PM_MRK_DTLB_MISS_64K, 129 PM_DISP_HELD_SYNC_HOLD, 130 PM_DTLB_MISS_16M, 131 PM_DTLB_MISS_1G, 132 PM_MRK_DTLB_MISS_16M, 133 }; 134 135 /* Table of alternatives, sorted by column 0 */ 136 static const unsigned int power9_event_alternatives[][MAX_ALT] = { 137 { PM_INST_DISP, PM_INST_DISP_ALT }, 138 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 139 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 140 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 141 { PM_BR_2PATH, PM_BR_2PATH_ALT }, 142 }; 143 144 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 145 { 146 int num_alt = 0; 147 148 num_alt = isa207_get_alternatives(event, alt, 149 ARRAY_SIZE(power9_event_alternatives), flags, 150 power9_event_alternatives); 151 152 return num_alt; 153 } 154 155 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 156 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC); 157 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 158 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 159 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 160 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 161 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 162 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN); 163 164 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); 165 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 166 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 167 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 168 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 169 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 170 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 171 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 172 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 173 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 174 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 175 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 176 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 177 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 178 179 static struct attribute *power9_events_attr[] = { 180 GENERIC_EVENT_PTR(PM_CYC), 181 GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC), 182 GENERIC_EVENT_PTR(PM_CMPLU_STALL), 183 GENERIC_EVENT_PTR(PM_INST_CMPL), 184 GENERIC_EVENT_PTR(PM_BR_CMPL), 185 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 186 GENERIC_EVENT_PTR(PM_LD_REF_L1), 187 GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN), 188 CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN), 189 CACHE_EVENT_PTR(PM_LD_REF_L1), 190 CACHE_EVENT_PTR(PM_L1_PREF), 191 CACHE_EVENT_PTR(PM_ST_MISS_L1), 192 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 193 CACHE_EVENT_PTR(PM_INST_FROM_L1), 194 CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 195 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 196 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 197 CACHE_EVENT_PTR(PM_L3_PREF_ALL), 198 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 199 CACHE_EVENT_PTR(PM_BR_CMPL), 200 CACHE_EVENT_PTR(PM_DTLB_MISS), 201 CACHE_EVENT_PTR(PM_ITLB_MISS), 202 NULL 203 }; 204 205 static struct attribute_group power9_pmu_events_group = { 206 .name = "events", 207 .attrs = power9_events_attr, 208 }; 209 210 PMU_FORMAT_ATTR(event, "config:0-51"); 211 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 212 PMU_FORMAT_ATTR(mark, "config:8"); 213 PMU_FORMAT_ATTR(combine, "config:10-11"); 214 PMU_FORMAT_ATTR(unit, "config:12-15"); 215 PMU_FORMAT_ATTR(pmc, "config:16-19"); 216 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 217 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 218 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 219 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 220 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 221 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 222 PMU_FORMAT_ATTR(sdar_mode, "config:50-51"); 223 224 static struct attribute *power9_pmu_format_attr[] = { 225 &format_attr_event.attr, 226 &format_attr_pmcxsel.attr, 227 &format_attr_mark.attr, 228 &format_attr_combine.attr, 229 &format_attr_unit.attr, 230 &format_attr_pmc.attr, 231 &format_attr_cache_sel.attr, 232 &format_attr_sample_mode.attr, 233 &format_attr_thresh_sel.attr, 234 &format_attr_thresh_stop.attr, 235 &format_attr_thresh_start.attr, 236 &format_attr_thresh_cmp.attr, 237 &format_attr_sdar_mode.attr, 238 NULL, 239 }; 240 241 static struct attribute_group power9_pmu_format_group = { 242 .name = "format", 243 .attrs = power9_pmu_format_attr, 244 }; 245 246 static const struct attribute_group *power9_pmu_attr_groups[] = { 247 &power9_pmu_format_group, 248 &power9_pmu_events_group, 249 NULL, 250 }; 251 252 static int power9_generic_events[] = { 253 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 254 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 255 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 256 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 257 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 258 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 259 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 260 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 261 }; 262 263 static u64 power9_bhrb_filter_map(u64 branch_sample_type) 264 { 265 u64 pmu_bhrb_filter = 0; 266 267 /* BHRB and regular PMU events share the same privilege state 268 * filter configuration. BHRB is always recorded along with a 269 * regular PMU event. As the privilege state filter is handled 270 * in the basic PMC configuration of the accompanying regular 271 * PMU event, we ignore any separate BHRB specific request. 272 */ 273 274 /* No branch filter requested */ 275 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 276 return pmu_bhrb_filter; 277 278 /* Invalid branch filter options - HW does not support */ 279 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 280 return -1; 281 282 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 283 return -1; 284 285 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 286 return -1; 287 288 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 289 pmu_bhrb_filter |= POWER9_MMCRA_IFM1; 290 return pmu_bhrb_filter; 291 } 292 293 /* Every thing else is unsupported */ 294 return -1; 295 } 296 297 static void power9_config_bhrb(u64 pmu_bhrb_filter) 298 { 299 /* Enable BHRB filter in PMU */ 300 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 301 } 302 303 #define C(x) PERF_COUNT_HW_CACHE_##x 304 305 /* 306 * Table of generalized cache-related events. 307 * 0 means not supported, -1 means nonsensical, other values 308 * are event codes. 309 */ 310 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 311 [ C(L1D) ] = { 312 [ C(OP_READ) ] = { 313 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 314 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN, 315 }, 316 [ C(OP_WRITE) ] = { 317 [ C(RESULT_ACCESS) ] = 0, 318 [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 319 }, 320 [ C(OP_PREFETCH) ] = { 321 [ C(RESULT_ACCESS) ] = PM_L1_PREF, 322 [ C(RESULT_MISS) ] = 0, 323 }, 324 }, 325 [ C(L1I) ] = { 326 [ C(OP_READ) ] = { 327 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 328 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 329 }, 330 [ C(OP_WRITE) ] = { 331 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 332 [ C(RESULT_MISS) ] = -1, 333 }, 334 [ C(OP_PREFETCH) ] = { 335 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 336 [ C(RESULT_MISS) ] = 0, 337 }, 338 }, 339 [ C(LL) ] = { 340 [ C(OP_READ) ] = { 341 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 342 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 343 }, 344 [ C(OP_WRITE) ] = { 345 [ C(RESULT_ACCESS) ] = 0, 346 [ C(RESULT_MISS) ] = 0, 347 }, 348 [ C(OP_PREFETCH) ] = { 349 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 350 [ C(RESULT_MISS) ] = 0, 351 }, 352 }, 353 [ C(DTLB) ] = { 354 [ C(OP_READ) ] = { 355 [ C(RESULT_ACCESS) ] = 0, 356 [ C(RESULT_MISS) ] = PM_DTLB_MISS, 357 }, 358 [ C(OP_WRITE) ] = { 359 [ C(RESULT_ACCESS) ] = -1, 360 [ C(RESULT_MISS) ] = -1, 361 }, 362 [ C(OP_PREFETCH) ] = { 363 [ C(RESULT_ACCESS) ] = -1, 364 [ C(RESULT_MISS) ] = -1, 365 }, 366 }, 367 [ C(ITLB) ] = { 368 [ C(OP_READ) ] = { 369 [ C(RESULT_ACCESS) ] = 0, 370 [ C(RESULT_MISS) ] = PM_ITLB_MISS, 371 }, 372 [ C(OP_WRITE) ] = { 373 [ C(RESULT_ACCESS) ] = -1, 374 [ C(RESULT_MISS) ] = -1, 375 }, 376 [ C(OP_PREFETCH) ] = { 377 [ C(RESULT_ACCESS) ] = -1, 378 [ C(RESULT_MISS) ] = -1, 379 }, 380 }, 381 [ C(BPU) ] = { 382 [ C(OP_READ) ] = { 383 [ C(RESULT_ACCESS) ] = PM_BR_CMPL, 384 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 385 }, 386 [ C(OP_WRITE) ] = { 387 [ C(RESULT_ACCESS) ] = -1, 388 [ C(RESULT_MISS) ] = -1, 389 }, 390 [ C(OP_PREFETCH) ] = { 391 [ C(RESULT_ACCESS) ] = -1, 392 [ C(RESULT_MISS) ] = -1, 393 }, 394 }, 395 [ C(NODE) ] = { 396 [ C(OP_READ) ] = { 397 [ C(RESULT_ACCESS) ] = -1, 398 [ C(RESULT_MISS) ] = -1, 399 }, 400 [ C(OP_WRITE) ] = { 401 [ C(RESULT_ACCESS) ] = -1, 402 [ C(RESULT_MISS) ] = -1, 403 }, 404 [ C(OP_PREFETCH) ] = { 405 [ C(RESULT_ACCESS) ] = -1, 406 [ C(RESULT_MISS) ] = -1, 407 }, 408 }, 409 }; 410 411 #undef C 412 413 static struct power_pmu power9_pmu = { 414 .name = "POWER9", 415 .n_counter = MAX_PMU_COUNTERS, 416 .add_fields = ISA207_ADD_FIELDS, 417 .test_adder = ISA207_TEST_ADDER, 418 .group_constraint_mask = CNST_CACHE_PMC4_MASK, 419 .group_constraint_val = CNST_CACHE_PMC4_VAL, 420 .compute_mmcr = isa207_compute_mmcr, 421 .config_bhrb = power9_config_bhrb, 422 .bhrb_filter_map = power9_bhrb_filter_map, 423 .get_constraint = isa207_get_constraint, 424 .get_alternatives = power9_get_alternatives, 425 .get_mem_data_src = isa207_get_mem_data_src, 426 .get_mem_weight = isa207_get_mem_weight, 427 .disable_pmc = isa207_disable_pmc, 428 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 429 .n_generic = ARRAY_SIZE(power9_generic_events), 430 .generic_events = power9_generic_events, 431 .cache_events = &power9_cache_events, 432 .attr_groups = power9_pmu_attr_groups, 433 .bhrb_nr = 32, 434 }; 435 436 static int __init init_power9_pmu(void) 437 { 438 int rc = 0; 439 unsigned int pvr = mfspr(SPRN_PVR); 440 441 /* Comes from cpu_specs[] */ 442 if (!cur_cpu_spec->oprofile_cpu_type || 443 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9")) 444 return -ENODEV; 445 446 /* Blacklist events */ 447 if (!(pvr & PVR_POWER9_CUMULUS)) { 448 if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) { 449 power9_pmu.blacklist_ev = p9_dd21_bl_ev; 450 power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev); 451 } else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) { 452 power9_pmu.blacklist_ev = p9_dd22_bl_ev; 453 power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev); 454 } 455 } 456 457 rc = register_power_pmu(&power9_pmu); 458 if (rc) 459 return rc; 460 461 /* Tell userspace that EBB is supported */ 462 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 463 464 return 0; 465 } 466 early_initcall(init_power9_pmu); 467