1 /* 2 * Performance counter support for POWER7 processors. 3 * 4 * Copyright 2013 Runzhen Wang, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 EVENT(PM_IC_DEMAND_L2_BR_ALL, 0x04898) 13 EVENT(PM_GCT_UTIL_7_TO_10_SLOTS, 0x020a0) 14 EVENT(PM_PMC2_SAVED, 0x10022) 15 EVENT(PM_CMPLU_STALL_DFU, 0x2003c) 16 EVENT(PM_VSU0_16FLOP, 0x0a0a4) 17 EVENT(PM_MRK_LSU_DERAT_MISS, 0x3d05a) 18 EVENT(PM_MRK_ST_CMPL, 0x10034) 19 EVENT(PM_NEST_PAIR3_ADD, 0x40881) 20 EVENT(PM_L2_ST_DISP, 0x46180) 21 EVENT(PM_L2_CASTOUT_MOD, 0x16180) 22 EVENT(PM_ISEG, 0x020a4) 23 EVENT(PM_MRK_INST_TIMEO, 0x40034) 24 EVENT(PM_L2_RCST_DISP_FAIL_ADDR, 0x36282) 25 EVENT(PM_LSU1_DC_PREF_STREAM_CONFIRM, 0x0d0b6) 26 EVENT(PM_IERAT_WR_64K, 0x040be) 27 EVENT(PM_MRK_DTLB_MISS_16M, 0x4d05e) 28 EVENT(PM_IERAT_MISS, 0x100f6) 29 EVENT(PM_MRK_PTEG_FROM_LMEM, 0x4d052) 30 EVENT(PM_FLOP, 0x100f4) 31 EVENT(PM_THRD_PRIO_4_5_CYC, 0x040b4) 32 EVENT(PM_BR_PRED_TA, 0x040aa) 33 EVENT(PM_CMPLU_STALL_FXU, 0x20014) 34 EVENT(PM_EXT_INT, 0x200f8) 35 EVENT(PM_VSU_FSQRT_FDIV, 0x0a888) 36 EVENT(PM_MRK_LD_MISS_EXPOSED_CYC, 0x1003e) 37 EVENT(PM_LSU1_LDF, 0x0c086) 38 EVENT(PM_IC_WRITE_ALL, 0x0488c) 39 EVENT(PM_LSU0_SRQ_STFWD, 0x0c0a0) 40 EVENT(PM_PTEG_FROM_RL2L3_MOD, 0x1c052) 41 EVENT(PM_MRK_DATA_FROM_L31_SHR, 0x1d04e) 42 EVENT(PM_DATA_FROM_L21_MOD, 0x3c046) 43 EVENT(PM_VSU1_SCAL_DOUBLE_ISSUED, 0x0b08a) 44 EVENT(PM_VSU0_8FLOP, 0x0a0a0) 45 EVENT(PM_POWER_EVENT1, 0x1006e) 46 EVENT(PM_DISP_CLB_HELD_BAL, 0x02092) 47 EVENT(PM_VSU1_2FLOP, 0x0a09a) 48 EVENT(PM_LWSYNC_HELD, 0x0209a) 49 EVENT(PM_PTEG_FROM_DL2L3_SHR, 0x3c054) 50 EVENT(PM_INST_FROM_L21_MOD, 0x34046) 51 EVENT(PM_IERAT_XLATE_WR_16MPLUS, 0x040bc) 52 EVENT(PM_IC_REQ_ALL, 0x04888) 53 EVENT(PM_DSLB_MISS, 0x0d090) 54 EVENT(PM_L3_MISS, 0x1f082) 55 EVENT(PM_LSU0_L1_PREF, 0x0d0b8) 56 EVENT(PM_VSU_SCALAR_SINGLE_ISSUED, 0x0b884) 57 EVENT(PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE, 0x0d0be) 58 EVENT(PM_L2_INST, 0x36080) 59 EVENT(PM_VSU0_FRSP, 0x0a0b4) 60 EVENT(PM_FLUSH_DISP, 0x02082) 61 EVENT(PM_PTEG_FROM_L2MISS, 0x4c058) 62 EVENT(PM_VSU1_DQ_ISSUED, 0x0b09a) 63 EVENT(PM_CMPLU_STALL_LSU, 0x20012) 64 EVENT(PM_MRK_DATA_FROM_DMEM, 0x1d04a) 65 EVENT(PM_LSU_FLUSH_ULD, 0x0c8b0) 66 EVENT(PM_PTEG_FROM_LMEM, 0x4c052) 67 EVENT(PM_MRK_DERAT_MISS_16M, 0x3d05c) 68 EVENT(PM_THRD_ALL_RUN_CYC, 0x2000c) 69 EVENT(PM_MEM0_PREFETCH_DISP, 0x20083) 70 EVENT(PM_MRK_STALL_CMPLU_CYC_COUNT, 0x3003f) 71 EVENT(PM_DATA_FROM_DL2L3_MOD, 0x3c04c) 72 EVENT(PM_VSU_FRSP, 0x0a8b4) 73 EVENT(PM_MRK_DATA_FROM_L21_MOD, 0x3d046) 74 EVENT(PM_PMC1_OVERFLOW, 0x20010) 75 EVENT(PM_VSU0_SINGLE, 0x0a0a8) 76 EVENT(PM_MRK_PTEG_FROM_L3MISS, 0x2d058) 77 EVENT(PM_MRK_PTEG_FROM_L31_SHR, 0x2d056) 78 EVENT(PM_VSU0_VECTOR_SP_ISSUED, 0x0b090) 79 EVENT(PM_VSU1_FEST, 0x0a0ba) 80 EVENT(PM_MRK_INST_DISP, 0x20030) 81 EVENT(PM_VSU0_COMPLEX_ISSUED, 0x0b096) 82 EVENT(PM_LSU1_FLUSH_UST, 0x0c0b6) 83 EVENT(PM_INST_CMPL, 0x00002) 84 EVENT(PM_FXU_IDLE, 0x1000e) 85 EVENT(PM_LSU0_FLUSH_ULD, 0x0c0b0) 86 EVENT(PM_MRK_DATA_FROM_DL2L3_MOD, 0x3d04c) 87 EVENT(PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC, 0x3001c) 88 EVENT(PM_LSU1_REJECT_LMQ_FULL, 0x0c0a6) 89 EVENT(PM_INST_PTEG_FROM_L21_MOD, 0x3e056) 90 EVENT(PM_INST_FROM_RL2L3_MOD, 0x14042) 91 EVENT(PM_SHL_CREATED, 0x05082) 92 EVENT(PM_L2_ST_HIT, 0x46182) 93 EVENT(PM_DATA_FROM_DMEM, 0x1c04a) 94 EVENT(PM_L3_LD_MISS, 0x2f082) 95 EVENT(PM_FXU1_BUSY_FXU0_IDLE, 0x4000e) 96 EVENT(PM_DISP_CLB_HELD_RES, 0x02094) 97 EVENT(PM_L2_SN_SX_I_DONE, 0x36382) 98 EVENT(PM_GRP_CMPL, 0x30004) 99 EVENT(PM_STCX_CMPL, 0x0c098) 100 EVENT(PM_VSU0_2FLOP, 0x0a098) 101 EVENT(PM_L3_PREF_MISS, 0x3f082) 102 EVENT(PM_LSU_SRQ_SYNC_CYC, 0x0d096) 103 EVENT(PM_LSU_REJECT_ERAT_MISS, 0x20064) 104 EVENT(PM_L1_ICACHE_MISS, 0x200fc) 105 EVENT(PM_LSU1_FLUSH_SRQ, 0x0c0be) 106 EVENT(PM_LD_REF_L1_LSU0, 0x0c080) 107 EVENT(PM_VSU0_FEST, 0x0a0b8) 108 EVENT(PM_VSU_VECTOR_SINGLE_ISSUED, 0x0b890) 109 EVENT(PM_FREQ_UP, 0x4000c) 110 EVENT(PM_DATA_FROM_LMEM, 0x3c04a) 111 EVENT(PM_LSU1_LDX, 0x0c08a) 112 EVENT(PM_PMC3_OVERFLOW, 0x40010) 113 EVENT(PM_MRK_BR_MPRED, 0x30036) 114 EVENT(PM_SHL_MATCH, 0x05086) 115 EVENT(PM_MRK_BR_TAKEN, 0x10036) 116 EVENT(PM_CMPLU_STALL_BRU, 0x4004e) 117 EVENT(PM_ISLB_MISS, 0x0d092) 118 EVENT(PM_CYC, 0x0001e) 119 EVENT(PM_DISP_HELD_THERMAL, 0x30006) 120 EVENT(PM_INST_PTEG_FROM_RL2L3_SHR, 0x2e054) 121 EVENT(PM_LSU1_SRQ_STFWD, 0x0c0a2) 122 EVENT(PM_GCT_NOSLOT_BR_MPRED, 0x4001a) 123 EVENT(PM_1PLUS_PPC_CMPL, 0x100f2) 124 EVENT(PM_PTEG_FROM_DMEM, 0x2c052) 125 EVENT(PM_VSU_2FLOP, 0x0a898) 126 EVENT(PM_GCT_FULL_CYC, 0x04086) 127 EVENT(PM_MRK_DATA_FROM_L3_CYC, 0x40020) 128 EVENT(PM_LSU_SRQ_S0_ALLOC, 0x0d09d) 129 EVENT(PM_MRK_DERAT_MISS_4K, 0x1d05c) 130 EVENT(PM_BR_MPRED_TA, 0x040ae) 131 EVENT(PM_INST_PTEG_FROM_L2MISS, 0x4e058) 132 EVENT(PM_DPU_HELD_POWER, 0x20006) 133 EVENT(PM_RUN_INST_CMPL, 0x400fa) 134 EVENT(PM_MRK_VSU_FIN, 0x30032) 135 EVENT(PM_LSU_SRQ_S0_VALID, 0x0d09c) 136 EVENT(PM_GCT_EMPTY_CYC, 0x20008) 137 EVENT(PM_IOPS_DISP, 0x30014) 138 EVENT(PM_RUN_SPURR, 0x10008) 139 EVENT(PM_PTEG_FROM_L21_MOD, 0x3c056) 140 EVENT(PM_VSU0_1FLOP, 0x0a080) 141 EVENT(PM_SNOOP_TLBIE, 0x0d0b2) 142 EVENT(PM_DATA_FROM_L3MISS, 0x2c048) 143 EVENT(PM_VSU_SINGLE, 0x0a8a8) 144 EVENT(PM_DTLB_MISS_16G, 0x1c05e) 145 EVENT(PM_CMPLU_STALL_VECTOR, 0x2001c) 146 EVENT(PM_FLUSH, 0x400f8) 147 EVENT(PM_L2_LD_HIT, 0x36182) 148 EVENT(PM_NEST_PAIR2_AND, 0x30883) 149 EVENT(PM_VSU1_1FLOP, 0x0a082) 150 EVENT(PM_IC_PREF_REQ, 0x0408a) 151 EVENT(PM_L3_LD_HIT, 0x2f080) 152 EVENT(PM_GCT_NOSLOT_IC_MISS, 0x2001a) 153 EVENT(PM_DISP_HELD, 0x10006) 154 EVENT(PM_L2_LD, 0x16080) 155 EVENT(PM_LSU_FLUSH_SRQ, 0x0c8bc) 156 EVENT(PM_BC_PLUS_8_CONV, 0x040b8) 157 EVENT(PM_MRK_DATA_FROM_L31_MOD_CYC, 0x40026) 158 EVENT(PM_CMPLU_STALL_VECTOR_LONG, 0x4004a) 159 EVENT(PM_L2_RCST_BUSY_RC_FULL, 0x26282) 160 EVENT(PM_TB_BIT_TRANS, 0x300f8) 161 EVENT(PM_THERMAL_MAX, 0x40006) 162 EVENT(PM_LSU1_FLUSH_ULD, 0x0c0b2) 163 EVENT(PM_LSU1_REJECT_LHS, 0x0c0ae) 164 EVENT(PM_LSU_LRQ_S0_ALLOC, 0x0d09f) 165 EVENT(PM_L3_CO_L31, 0x4f080) 166 EVENT(PM_POWER_EVENT4, 0x4006e) 167 EVENT(PM_DATA_FROM_L31_SHR, 0x1c04e) 168 EVENT(PM_BR_UNCOND, 0x0409e) 169 EVENT(PM_LSU1_DC_PREF_STREAM_ALLOC, 0x0d0aa) 170 EVENT(PM_PMC4_REWIND, 0x10020) 171 EVENT(PM_L2_RCLD_DISP, 0x16280) 172 EVENT(PM_THRD_PRIO_2_3_CYC, 0x040b2) 173 EVENT(PM_MRK_PTEG_FROM_L2MISS, 0x4d058) 174 EVENT(PM_IC_DEMAND_L2_BHT_REDIRECT, 0x04098) 175 EVENT(PM_LSU_DERAT_MISS, 0x200f6) 176 EVENT(PM_IC_PREF_CANCEL_L2, 0x04094) 177 EVENT(PM_MRK_FIN_STALL_CYC_COUNT, 0x1003d) 178 EVENT(PM_BR_PRED_CCACHE, 0x040a0) 179 EVENT(PM_GCT_UTIL_1_TO_2_SLOTS, 0x0209c) 180 EVENT(PM_MRK_ST_CMPL_INT, 0x30034) 181 EVENT(PM_LSU_TWO_TABLEWALK_CYC, 0x0d0a6) 182 EVENT(PM_MRK_DATA_FROM_L3MISS, 0x2d048) 183 EVENT(PM_GCT_NOSLOT_CYC, 0x100f8) 184 EVENT(PM_LSU_SET_MPRED, 0x0c0a8) 185 EVENT(PM_FLUSH_DISP_TLBIE, 0x0208a) 186 EVENT(PM_VSU1_FCONV, 0x0a0b2) 187 EVENT(PM_DERAT_MISS_16G, 0x4c05c) 188 EVENT(PM_INST_FROM_LMEM, 0x3404a) 189 EVENT(PM_IC_DEMAND_L2_BR_REDIRECT, 0x0409a) 190 EVENT(PM_CMPLU_STALL_SCALAR_LONG, 0x20018) 191 EVENT(PM_INST_PTEG_FROM_L2, 0x1e050) 192 EVENT(PM_PTEG_FROM_L2, 0x1c050) 193 EVENT(PM_MRK_DATA_FROM_L21_SHR_CYC, 0x20024) 194 EVENT(PM_MRK_DTLB_MISS_4K, 0x2d05a) 195 EVENT(PM_VSU0_FPSCR, 0x0b09c) 196 EVENT(PM_VSU1_VECT_DOUBLE_ISSUED, 0x0b082) 197 EVENT(PM_MRK_PTEG_FROM_RL2L3_MOD, 0x1d052) 198 EVENT(PM_MEM0_RQ_DISP, 0x10083) 199 EVENT(PM_L2_LD_MISS, 0x26080) 200 EVENT(PM_VMX_RESULT_SAT_1, 0x0b0a0) 201 EVENT(PM_L1_PREF, 0x0d8b8) 202 EVENT(PM_MRK_DATA_FROM_LMEM_CYC, 0x2002c) 203 EVENT(PM_GRP_IC_MISS_NONSPEC, 0x1000c) 204 EVENT(PM_PB_NODE_PUMP, 0x10081) 205 EVENT(PM_SHL_MERGED, 0x05084) 206 EVENT(PM_NEST_PAIR1_ADD, 0x20881) 207 EVENT(PM_DATA_FROM_L3, 0x1c048) 208 EVENT(PM_LSU_FLUSH, 0x0208e) 209 EVENT(PM_LSU_SRQ_SYNC_COUNT, 0x0d097) 210 EVENT(PM_PMC2_OVERFLOW, 0x30010) 211 EVENT(PM_LSU_LDF, 0x0c884) 212 EVENT(PM_POWER_EVENT3, 0x3006e) 213 EVENT(PM_DISP_WT, 0x30008) 214 EVENT(PM_CMPLU_STALL_REJECT, 0x40016) 215 EVENT(PM_IC_BANK_CONFLICT, 0x04082) 216 EVENT(PM_BR_MPRED_CR_TA, 0x048ae) 217 EVENT(PM_L2_INST_MISS, 0x36082) 218 EVENT(PM_CMPLU_STALL_ERAT_MISS, 0x40018) 219 EVENT(PM_NEST_PAIR2_ADD, 0x30881) 220 EVENT(PM_MRK_LSU_FLUSH, 0x0d08c) 221 EVENT(PM_L2_LDST, 0x16880) 222 EVENT(PM_INST_FROM_L31_SHR, 0x1404e) 223 EVENT(PM_VSU0_FIN, 0x0a0bc) 224 EVENT(PM_LARX_LSU, 0x0c894) 225 EVENT(PM_INST_FROM_RMEM, 0x34042) 226 EVENT(PM_DISP_CLB_HELD_TLBIE, 0x02096) 227 EVENT(PM_MRK_DATA_FROM_DMEM_CYC, 0x2002e) 228 EVENT(PM_BR_PRED_CR, 0x040a8) 229 EVENT(PM_LSU_REJECT, 0x10064) 230 EVENT(PM_GCT_UTIL_3_TO_6_SLOTS, 0x0209e) 231 EVENT(PM_CMPLU_STALL_END_GCT_NOSLOT, 0x10028) 232 EVENT(PM_LSU0_REJECT_LMQ_FULL, 0x0c0a4) 233 EVENT(PM_VSU_FEST, 0x0a8b8) 234 EVENT(PM_NEST_PAIR0_AND, 0x10883) 235 EVENT(PM_PTEG_FROM_L3, 0x2c050) 236 EVENT(PM_POWER_EVENT2, 0x2006e) 237 EVENT(PM_IC_PREF_CANCEL_PAGE, 0x04090) 238 EVENT(PM_VSU0_FSQRT_FDIV, 0x0a088) 239 EVENT(PM_MRK_GRP_CMPL, 0x40030) 240 EVENT(PM_VSU0_SCAL_DOUBLE_ISSUED, 0x0b088) 241 EVENT(PM_GRP_DISP, 0x3000a) 242 EVENT(PM_LSU0_LDX, 0x0c088) 243 EVENT(PM_DATA_FROM_L2, 0x1c040) 244 EVENT(PM_MRK_DATA_FROM_RL2L3_MOD, 0x1d042) 245 EVENT(PM_LD_REF_L1, 0x0c880) 246 EVENT(PM_VSU0_VECT_DOUBLE_ISSUED, 0x0b080) 247 EVENT(PM_VSU1_2FLOP_DOUBLE, 0x0a08e) 248 EVENT(PM_THRD_PRIO_6_7_CYC, 0x040b6) 249 EVENT(PM_BC_PLUS_8_RSLV_TAKEN, 0x040ba) 250 EVENT(PM_BR_MPRED_CR, 0x040ac) 251 EVENT(PM_L3_CO_MEM, 0x4f082) 252 EVENT(PM_LD_MISS_L1, 0x400f0) 253 EVENT(PM_DATA_FROM_RL2L3_MOD, 0x1c042) 254 EVENT(PM_LSU_SRQ_FULL_CYC, 0x1001a) 255 EVENT(PM_TABLEWALK_CYC, 0x10026) 256 EVENT(PM_MRK_PTEG_FROM_RMEM, 0x3d052) 257 EVENT(PM_LSU_SRQ_STFWD, 0x0c8a0) 258 EVENT(PM_INST_PTEG_FROM_RMEM, 0x3e052) 259 EVENT(PM_FXU0_FIN, 0x10004) 260 EVENT(PM_LSU1_L1_SW_PREF, 0x0c09e) 261 EVENT(PM_PTEG_FROM_L31_MOD, 0x1c054) 262 EVENT(PM_PMC5_OVERFLOW, 0x10024) 263 EVENT(PM_LD_REF_L1_LSU1, 0x0c082) 264 EVENT(PM_INST_PTEG_FROM_L21_SHR, 0x4e056) 265 EVENT(PM_CMPLU_STALL_THRD, 0x1001c) 266 EVENT(PM_DATA_FROM_RMEM, 0x3c042) 267 EVENT(PM_VSU0_SCAL_SINGLE_ISSUED, 0x0b084) 268 EVENT(PM_BR_MPRED_LSTACK, 0x040a6) 269 EVENT(PM_MRK_DATA_FROM_RL2L3_MOD_CYC, 0x40028) 270 EVENT(PM_LSU0_FLUSH_UST, 0x0c0b4) 271 EVENT(PM_LSU_NCST, 0x0c090) 272 EVENT(PM_BR_TAKEN, 0x20004) 273 EVENT(PM_INST_PTEG_FROM_LMEM, 0x4e052) 274 EVENT(PM_GCT_NOSLOT_BR_MPRED_IC_MISS, 0x4001c) 275 EVENT(PM_DTLB_MISS_4K, 0x2c05a) 276 EVENT(PM_PMC4_SAVED, 0x30022) 277 EVENT(PM_VSU1_PERMUTE_ISSUED, 0x0b092) 278 EVENT(PM_SLB_MISS, 0x0d890) 279 EVENT(PM_LSU1_FLUSH_LRQ, 0x0c0ba) 280 EVENT(PM_DTLB_MISS, 0x300fc) 281 EVENT(PM_VSU1_FRSP, 0x0a0b6) 282 EVENT(PM_VSU_VECTOR_DOUBLE_ISSUED, 0x0b880) 283 EVENT(PM_L2_CASTOUT_SHR, 0x16182) 284 EVENT(PM_DATA_FROM_DL2L3_SHR, 0x3c044) 285 EVENT(PM_VSU1_STF, 0x0b08e) 286 EVENT(PM_ST_FIN, 0x200f0) 287 EVENT(PM_PTEG_FROM_L21_SHR, 0x4c056) 288 EVENT(PM_L2_LOC_GUESS_WRONG, 0x26480) 289 EVENT(PM_MRK_STCX_FAIL, 0x0d08e) 290 EVENT(PM_LSU0_REJECT_LHS, 0x0c0ac) 291 EVENT(PM_IC_PREF_CANCEL_HIT, 0x04092) 292 EVENT(PM_L3_PREF_BUSY, 0x4f080) 293 EVENT(PM_MRK_BRU_FIN, 0x2003a) 294 EVENT(PM_LSU1_NCLD, 0x0c08e) 295 EVENT(PM_INST_PTEG_FROM_L31_MOD, 0x1e054) 296 EVENT(PM_LSU_NCLD, 0x0c88c) 297 EVENT(PM_LSU_LDX, 0x0c888) 298 EVENT(PM_L2_LOC_GUESS_CORRECT, 0x16480) 299 EVENT(PM_THRESH_TIMEO, 0x10038) 300 EVENT(PM_L3_PREF_ST, 0x0d0ae) 301 EVENT(PM_DISP_CLB_HELD_SYNC, 0x02098) 302 EVENT(PM_VSU_SIMPLE_ISSUED, 0x0b894) 303 EVENT(PM_VSU1_SINGLE, 0x0a0aa) 304 EVENT(PM_DATA_TABLEWALK_CYC, 0x3001a) 305 EVENT(PM_L2_RC_ST_DONE, 0x36380) 306 EVENT(PM_MRK_PTEG_FROM_L21_MOD, 0x3d056) 307 EVENT(PM_LARX_LSU1, 0x0c096) 308 EVENT(PM_MRK_DATA_FROM_RMEM, 0x3d042) 309 EVENT(PM_DISP_CLB_HELD, 0x02090) 310 EVENT(PM_DERAT_MISS_4K, 0x1c05c) 311 EVENT(PM_L2_RCLD_DISP_FAIL_ADDR, 0x16282) 312 EVENT(PM_SEG_EXCEPTION, 0x028a4) 313 EVENT(PM_FLUSH_DISP_SB, 0x0208c) 314 EVENT(PM_L2_DC_INV, 0x26182) 315 EVENT(PM_PTEG_FROM_DL2L3_MOD, 0x4c054) 316 EVENT(PM_DSEG, 0x020a6) 317 EVENT(PM_BR_PRED_LSTACK, 0x040a2) 318 EVENT(PM_VSU0_STF, 0x0b08c) 319 EVENT(PM_LSU_FX_FIN, 0x10066) 320 EVENT(PM_DERAT_MISS_16M, 0x3c05c) 321 EVENT(PM_MRK_PTEG_FROM_DL2L3_MOD, 0x4d054) 322 EVENT(PM_GCT_UTIL_11_PLUS_SLOTS, 0x020a2) 323 EVENT(PM_INST_FROM_L3, 0x14048) 324 EVENT(PM_MRK_IFU_FIN, 0x3003a) 325 EVENT(PM_ITLB_MISS, 0x400fc) 326 EVENT(PM_VSU_STF, 0x0b88c) 327 EVENT(PM_LSU_FLUSH_UST, 0x0c8b4) 328 EVENT(PM_L2_LDST_MISS, 0x26880) 329 EVENT(PM_FXU1_FIN, 0x40004) 330 EVENT(PM_SHL_DEALLOCATED, 0x05080) 331 EVENT(PM_L2_SN_M_WR_DONE, 0x46382) 332 EVENT(PM_LSU_REJECT_SET_MPRED, 0x0c8a8) 333 EVENT(PM_L3_PREF_LD, 0x0d0ac) 334 EVENT(PM_L2_SN_M_RD_DONE, 0x46380) 335 EVENT(PM_MRK_DERAT_MISS_16G, 0x4d05c) 336 EVENT(PM_VSU_FCONV, 0x0a8b0) 337 EVENT(PM_ANY_THRD_RUN_CYC, 0x100fa) 338 EVENT(PM_LSU_LMQ_FULL_CYC, 0x0d0a4) 339 EVENT(PM_MRK_LSU_REJECT_LHS, 0x0d082) 340 EVENT(PM_MRK_LD_MISS_L1_CYC, 0x4003e) 341 EVENT(PM_MRK_DATA_FROM_L2_CYC, 0x20020) 342 EVENT(PM_INST_IMC_MATCH_DISP, 0x30016) 343 EVENT(PM_MRK_DATA_FROM_RMEM_CYC, 0x4002c) 344 EVENT(PM_VSU0_SIMPLE_ISSUED, 0x0b094) 345 EVENT(PM_CMPLU_STALL_DIV, 0x40014) 346 EVENT(PM_MRK_PTEG_FROM_RL2L3_SHR, 0x2d054) 347 EVENT(PM_VSU_FMA_DOUBLE, 0x0a890) 348 EVENT(PM_VSU_4FLOP, 0x0a89c) 349 EVENT(PM_VSU1_FIN, 0x0a0be) 350 EVENT(PM_NEST_PAIR1_AND, 0x20883) 351 EVENT(PM_INST_PTEG_FROM_RL2L3_MOD, 0x1e052) 352 EVENT(PM_RUN_CYC, 0x200f4) 353 EVENT(PM_PTEG_FROM_RMEM, 0x3c052) 354 EVENT(PM_LSU_LRQ_S0_VALID, 0x0d09e) 355 EVENT(PM_LSU0_LDF, 0x0c084) 356 EVENT(PM_FLUSH_COMPLETION, 0x30012) 357 EVENT(PM_ST_MISS_L1, 0x300f0) 358 EVENT(PM_L2_NODE_PUMP, 0x36480) 359 EVENT(PM_INST_FROM_DL2L3_SHR, 0x34044) 360 EVENT(PM_MRK_STALL_CMPLU_CYC, 0x3003e) 361 EVENT(PM_VSU1_DENORM, 0x0a0ae) 362 EVENT(PM_MRK_DATA_FROM_L31_SHR_CYC, 0x20026) 363 EVENT(PM_NEST_PAIR0_ADD, 0x10881) 364 EVENT(PM_INST_FROM_L3MISS, 0x24048) 365 EVENT(PM_EE_OFF_EXT_INT, 0x02080) 366 EVENT(PM_INST_PTEG_FROM_DMEM, 0x2e052) 367 EVENT(PM_INST_FROM_DL2L3_MOD, 0x3404c) 368 EVENT(PM_PMC6_OVERFLOW, 0x30024) 369 EVENT(PM_VSU_2FLOP_DOUBLE, 0x0a88c) 370 EVENT(PM_TLB_MISS, 0x20066) 371 EVENT(PM_FXU_BUSY, 0x2000e) 372 EVENT(PM_L2_RCLD_DISP_FAIL_OTHER, 0x26280) 373 EVENT(PM_LSU_REJECT_LMQ_FULL, 0x0c8a4) 374 EVENT(PM_IC_RELOAD_SHR, 0x04096) 375 EVENT(PM_GRP_MRK, 0x10031) 376 EVENT(PM_MRK_ST_NEST, 0x20034) 377 EVENT(PM_VSU1_FSQRT_FDIV, 0x0a08a) 378 EVENT(PM_LSU0_FLUSH_LRQ, 0x0c0b8) 379 EVENT(PM_LARX_LSU0, 0x0c094) 380 EVENT(PM_IBUF_FULL_CYC, 0x04084) 381 EVENT(PM_MRK_DATA_FROM_DL2L3_SHR_CYC, 0x2002a) 382 EVENT(PM_LSU_DC_PREF_STREAM_ALLOC, 0x0d8a8) 383 EVENT(PM_GRP_MRK_CYC, 0x10030) 384 EVENT(PM_MRK_DATA_FROM_RL2L3_SHR_CYC, 0x20028) 385 EVENT(PM_L2_GLOB_GUESS_CORRECT, 0x16482) 386 EVENT(PM_LSU_REJECT_LHS, 0x0c8ac) 387 EVENT(PM_MRK_DATA_FROM_LMEM, 0x3d04a) 388 EVENT(PM_INST_PTEG_FROM_L3, 0x2e050) 389 EVENT(PM_FREQ_DOWN, 0x3000c) 390 EVENT(PM_PB_RETRY_NODE_PUMP, 0x30081) 391 EVENT(PM_INST_FROM_RL2L3_SHR, 0x1404c) 392 EVENT(PM_MRK_INST_ISSUED, 0x10032) 393 EVENT(PM_PTEG_FROM_L3MISS, 0x2c058) 394 EVENT(PM_RUN_PURR, 0x400f4) 395 EVENT(PM_MRK_GRP_IC_MISS, 0x40038) 396 EVENT(PM_MRK_DATA_FROM_L3, 0x1d048) 397 EVENT(PM_CMPLU_STALL_DCACHE_MISS, 0x20016) 398 EVENT(PM_PTEG_FROM_RL2L3_SHR, 0x2c054) 399 EVENT(PM_LSU_FLUSH_LRQ, 0x0c8b8) 400 EVENT(PM_MRK_DERAT_MISS_64K, 0x2d05c) 401 EVENT(PM_INST_PTEG_FROM_DL2L3_MOD, 0x4e054) 402 EVENT(PM_L2_ST_MISS, 0x26082) 403 EVENT(PM_MRK_PTEG_FROM_L21_SHR, 0x4d056) 404 EVENT(PM_LWSYNC, 0x0d094) 405 EVENT(PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE, 0x0d0bc) 406 EVENT(PM_MRK_LSU_FLUSH_LRQ, 0x0d088) 407 EVENT(PM_INST_IMC_MATCH_CMPL, 0x100f0) 408 EVENT(PM_NEST_PAIR3_AND, 0x40883) 409 EVENT(PM_PB_RETRY_SYS_PUMP, 0x40081) 410 EVENT(PM_MRK_INST_FIN, 0x30030) 411 EVENT(PM_MRK_PTEG_FROM_DL2L3_SHR, 0x3d054) 412 EVENT(PM_INST_FROM_L31_MOD, 0x14044) 413 EVENT(PM_MRK_DTLB_MISS_64K, 0x3d05e) 414 EVENT(PM_LSU_FIN, 0x30066) 415 EVENT(PM_MRK_LSU_REJECT, 0x40064) 416 EVENT(PM_L2_CO_FAIL_BUSY, 0x16382) 417 EVENT(PM_MEM0_WQ_DISP, 0x40083) 418 EVENT(PM_DATA_FROM_L31_MOD, 0x1c044) 419 EVENT(PM_THERMAL_WARN, 0x10016) 420 EVENT(PM_VSU0_4FLOP, 0x0a09c) 421 EVENT(PM_BR_MPRED_CCACHE, 0x040a4) 422 EVENT(PM_CMPLU_STALL_IFU, 0x4004c) 423 EVENT(PM_L1_DEMAND_WRITE, 0x0408c) 424 EVENT(PM_FLUSH_BR_MPRED, 0x02084) 425 EVENT(PM_MRK_DTLB_MISS_16G, 0x1d05e) 426 EVENT(PM_MRK_PTEG_FROM_DMEM, 0x2d052) 427 EVENT(PM_L2_RCST_DISP, 0x36280) 428 EVENT(PM_CMPLU_STALL, 0x4000a) 429 EVENT(PM_LSU_PARTIAL_CDF, 0x0c0aa) 430 EVENT(PM_DISP_CLB_HELD_SB, 0x020a8) 431 EVENT(PM_VSU0_FMA_DOUBLE, 0x0a090) 432 EVENT(PM_FXU0_BUSY_FXU1_IDLE, 0x3000e) 433 EVENT(PM_IC_DEMAND_CYC, 0x10018) 434 EVENT(PM_MRK_DATA_FROM_L21_SHR, 0x3d04e) 435 EVENT(PM_MRK_LSU_FLUSH_UST, 0x0d086) 436 EVENT(PM_INST_PTEG_FROM_L3MISS, 0x2e058) 437 EVENT(PM_VSU_DENORM, 0x0a8ac) 438 EVENT(PM_MRK_LSU_PARTIAL_CDF, 0x0d080) 439 EVENT(PM_INST_FROM_L21_SHR, 0x3404e) 440 EVENT(PM_IC_PREF_WRITE, 0x0408e) 441 EVENT(PM_BR_PRED, 0x0409c) 442 EVENT(PM_INST_FROM_DMEM, 0x1404a) 443 EVENT(PM_IC_PREF_CANCEL_ALL, 0x04890) 444 EVENT(PM_LSU_DC_PREF_STREAM_CONFIRM, 0x0d8b4) 445 EVENT(PM_MRK_LSU_FLUSH_SRQ, 0x0d08a) 446 EVENT(PM_MRK_FIN_STALL_CYC, 0x1003c) 447 EVENT(PM_L2_RCST_DISP_FAIL_OTHER, 0x46280) 448 EVENT(PM_VSU1_DD_ISSUED, 0x0b098) 449 EVENT(PM_PTEG_FROM_L31_SHR, 0x2c056) 450 EVENT(PM_DATA_FROM_L21_SHR, 0x3c04e) 451 EVENT(PM_LSU0_NCLD, 0x0c08c) 452 EVENT(PM_VSU1_4FLOP, 0x0a09e) 453 EVENT(PM_VSU1_8FLOP, 0x0a0a2) 454 EVENT(PM_VSU_8FLOP, 0x0a8a0) 455 EVENT(PM_LSU_LMQ_SRQ_EMPTY_CYC, 0x2003e) 456 EVENT(PM_DTLB_MISS_64K, 0x3c05e) 457 EVENT(PM_THRD_CONC_RUN_INST, 0x300f4) 458 EVENT(PM_MRK_PTEG_FROM_L2, 0x1d050) 459 EVENT(PM_PB_SYS_PUMP, 0x20081) 460 EVENT(PM_VSU_FIN, 0x0a8bc) 461 EVENT(PM_MRK_DATA_FROM_L31_MOD, 0x1d044) 462 EVENT(PM_THRD_PRIO_0_1_CYC, 0x040b0) 463 EVENT(PM_DERAT_MISS_64K, 0x2c05c) 464 EVENT(PM_PMC2_REWIND, 0x30020) 465 EVENT(PM_INST_FROM_L2, 0x14040) 466 EVENT(PM_GRP_BR_MPRED_NONSPEC, 0x1000a) 467 EVENT(PM_INST_DISP, 0x200f2) 468 EVENT(PM_MEM0_RD_CANCEL_TOTAL, 0x30083) 469 EVENT(PM_LSU0_DC_PREF_STREAM_CONFIRM, 0x0d0b4) 470 EVENT(PM_L1_DCACHE_RELOAD_VALID, 0x300f6) 471 EVENT(PM_VSU_SCALAR_DOUBLE_ISSUED, 0x0b888) 472 EVENT(PM_L3_PREF_HIT, 0x3f080) 473 EVENT(PM_MRK_PTEG_FROM_L31_MOD, 0x1d054) 474 EVENT(PM_CMPLU_STALL_STORE, 0x2004a) 475 EVENT(PM_MRK_FXU_FIN, 0x20038) 476 EVENT(PM_PMC4_OVERFLOW, 0x10010) 477 EVENT(PM_MRK_PTEG_FROM_L3, 0x2d050) 478 EVENT(PM_LSU0_LMQ_LHR_MERGE, 0x0d098) 479 EVENT(PM_BTAC_HIT, 0x0508a) 480 EVENT(PM_L3_RD_BUSY, 0x4f082) 481 EVENT(PM_LSU0_L1_SW_PREF, 0x0c09c) 482 EVENT(PM_INST_FROM_L2MISS, 0x44048) 483 EVENT(PM_LSU0_DC_PREF_STREAM_ALLOC, 0x0d0a8) 484 EVENT(PM_L2_ST, 0x16082) 485 EVENT(PM_VSU0_DENORM, 0x0a0ac) 486 EVENT(PM_MRK_DATA_FROM_DL2L3_SHR, 0x3d044) 487 EVENT(PM_BR_PRED_CR_TA, 0x048aa) 488 EVENT(PM_VSU0_FCONV, 0x0a0b0) 489 EVENT(PM_MRK_LSU_FLUSH_ULD, 0x0d084) 490 EVENT(PM_BTAC_MISS, 0x05088) 491 EVENT(PM_MRK_LD_MISS_EXPOSED_CYC_COUNT, 0x1003f) 492 EVENT(PM_MRK_DATA_FROM_L2, 0x1d040) 493 EVENT(PM_LSU_DCACHE_RELOAD_VALID, 0x0d0a2) 494 EVENT(PM_VSU_FMA, 0x0a884) 495 EVENT(PM_LSU0_FLUSH_SRQ, 0x0c0bc) 496 EVENT(PM_LSU1_L1_PREF, 0x0d0ba) 497 EVENT(PM_IOPS_CMPL, 0x10014) 498 EVENT(PM_L2_SYS_PUMP, 0x36482) 499 EVENT(PM_L2_RCLD_BUSY_RC_FULL, 0x46282) 500 EVENT(PM_LSU_LMQ_S0_ALLOC, 0x0d0a1) 501 EVENT(PM_FLUSH_DISP_SYNC, 0x02088) 502 EVENT(PM_MRK_DATA_FROM_DL2L3_MOD_CYC, 0x4002a) 503 EVENT(PM_L2_IC_INV, 0x26180) 504 EVENT(PM_MRK_DATA_FROM_L21_MOD_CYC, 0x40024) 505 EVENT(PM_L3_PREF_LDST, 0x0d8ac) 506 EVENT(PM_LSU_SRQ_EMPTY_CYC, 0x40008) 507 EVENT(PM_LSU_LMQ_S0_VALID, 0x0d0a0) 508 EVENT(PM_FLUSH_PARTIAL, 0x02086) 509 EVENT(PM_VSU1_FMA_DOUBLE, 0x0a092) 510 EVENT(PM_1PLUS_PPC_DISP, 0x400f2) 511 EVENT(PM_DATA_FROM_L2MISS, 0x200fe) 512 EVENT(PM_SUSPENDED, 0x00000) 513 EVENT(PM_VSU0_FMA, 0x0a084) 514 EVENT(PM_CMPLU_STALL_SCALAR, 0x40012) 515 EVENT(PM_STCX_FAIL, 0x0c09a) 516 EVENT(PM_VSU0_FSQRT_FDIV_DOUBLE, 0x0a094) 517 EVENT(PM_DC_PREF_DST, 0x0d0b0) 518 EVENT(PM_VSU1_SCAL_SINGLE_ISSUED, 0x0b086) 519 EVENT(PM_L3_HIT, 0x1f080) 520 EVENT(PM_L2_GLOB_GUESS_WRONG, 0x26482) 521 EVENT(PM_MRK_DFU_FIN, 0x20032) 522 EVENT(PM_INST_FROM_L1, 0x04080) 523 EVENT(PM_BRU_FIN, 0x10068) 524 EVENT(PM_IC_DEMAND_REQ, 0x04088) 525 EVENT(PM_VSU1_FSQRT_FDIV_DOUBLE, 0x0a096) 526 EVENT(PM_VSU1_FMA, 0x0a086) 527 EVENT(PM_MRK_LD_MISS_L1, 0x20036) 528 EVENT(PM_VSU0_2FLOP_DOUBLE, 0x0a08c) 529 EVENT(PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM, 0x0d8bc) 530 EVENT(PM_INST_PTEG_FROM_L31_SHR, 0x2e056) 531 EVENT(PM_MRK_LSU_REJECT_ERAT_MISS, 0x30064) 532 EVENT(PM_MRK_DATA_FROM_L2MISS, 0x4d048) 533 EVENT(PM_DATA_FROM_RL2L3_SHR, 0x1c04c) 534 EVENT(PM_INST_FROM_PREF, 0x14046) 535 EVENT(PM_VSU1_SQ, 0x0b09e) 536 EVENT(PM_L2_LD_DISP, 0x36180) 537 EVENT(PM_L2_DISP_ALL, 0x46080) 538 EVENT(PM_THRD_GRP_CMPL_BOTH_CYC, 0x10012) 539 EVENT(PM_VSU_FSQRT_FDIV_DOUBLE, 0x0a894) 540 EVENT(PM_BR_MPRED, 0x400f6) 541 EVENT(PM_INST_PTEG_FROM_DL2L3_SHR, 0x3e054) 542 EVENT(PM_VSU_1FLOP, 0x0a880) 543 EVENT(PM_HV_CYC, 0x2000a) 544 EVENT(PM_MRK_LSU_FIN, 0x40032) 545 EVENT(PM_MRK_DATA_FROM_RL2L3_SHR, 0x1d04c) 546 EVENT(PM_DTLB_MISS_16M, 0x4c05e) 547 EVENT(PM_LSU1_LMQ_LHR_MERGE, 0x0d09a) 548 EVENT(PM_IFU_FIN, 0x40066) 549