1 /* 2 * Performance event support - powerpc architecture code 3 * 4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/sched.h> 13 #include <linux/perf_event.h> 14 #include <linux/percpu.h> 15 #include <linux/hardirq.h> 16 #include <linux/uaccess.h> 17 #include <asm/reg.h> 18 #include <asm/pmc.h> 19 #include <asm/machdep.h> 20 #include <asm/firmware.h> 21 #include <asm/ptrace.h> 22 #include <asm/code-patching.h> 23 24 #define BHRB_MAX_ENTRIES 32 25 #define BHRB_TARGET 0x0000000000000002 26 #define BHRB_PREDICTION 0x0000000000000001 27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 28 29 struct cpu_hw_events { 30 int n_events; 31 int n_percpu; 32 int disabled; 33 int n_added; 34 int n_limited; 35 u8 pmcs_enabled; 36 struct perf_event *event[MAX_HWEVENTS]; 37 u64 events[MAX_HWEVENTS]; 38 unsigned int flags[MAX_HWEVENTS]; 39 /* 40 * The order of the MMCR array is: 41 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 42 * - 32-bit, MMCR0, MMCR1, MMCR2 43 */ 44 unsigned long mmcr[4]; 45 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 46 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 47 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 48 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 49 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 50 51 unsigned int group_flag; 52 int n_txn_start; 53 54 /* BHRB bits */ 55 u64 bhrb_filter; /* BHRB HW branch filter */ 56 unsigned int bhrb_users; 57 void *bhrb_context; 58 struct perf_branch_stack bhrb_stack; 59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 60 }; 61 62 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 63 64 static struct power_pmu *ppmu; 65 66 /* 67 * Normally, to ignore kernel events we set the FCS (freeze counters 68 * in supervisor mode) bit in MMCR0, but if the kernel runs with the 69 * hypervisor bit set in the MSR, or if we are running on a processor 70 * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 71 * then we need to use the FCHV bit to ignore kernel events. 72 */ 73 static unsigned int freeze_events_kernel = MMCR0_FCS; 74 75 /* 76 * 32-bit doesn't have MMCRA but does have an MMCR2, 77 * and a few other names are different. 78 */ 79 #ifdef CONFIG_PPC32 80 81 #define MMCR0_FCHV 0 82 #define MMCR0_PMCjCE MMCR0_PMCnCE 83 #define MMCR0_FC56 0 84 #define MMCR0_PMAO 0 85 #define MMCR0_EBE 0 86 #define MMCR0_BHRBA 0 87 #define MMCR0_PMCC 0 88 #define MMCR0_PMCC_U6 0 89 90 #define SPRN_MMCRA SPRN_MMCR2 91 #define MMCRA_SAMPLE_ENABLE 0 92 93 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 94 { 95 return 0; 96 } 97 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 98 static inline u32 perf_get_misc_flags(struct pt_regs *regs) 99 { 100 return 0; 101 } 102 static inline void perf_read_regs(struct pt_regs *regs) 103 { 104 regs->result = 0; 105 } 106 static inline int perf_intr_is_nmi(struct pt_regs *regs) 107 { 108 return 0; 109 } 110 111 static inline int siar_valid(struct pt_regs *regs) 112 { 113 return 1; 114 } 115 116 static bool is_ebb_event(struct perf_event *event) { return false; } 117 static int ebb_event_check(struct perf_event *event) { return 0; } 118 static void ebb_event_add(struct perf_event *event) { } 119 static void ebb_switch_out(unsigned long mmcr0) { } 120 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 121 { 122 return cpuhw->mmcr[0]; 123 } 124 125 static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 126 static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 127 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 128 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 129 static void pmao_restore_workaround(bool ebb) { } 130 #endif /* CONFIG_PPC32 */ 131 132 static bool regs_use_siar(struct pt_regs *regs) 133 { 134 /* 135 * When we take a performance monitor exception the regs are setup 136 * using perf_read_regs() which overloads some fields, in particular 137 * regs->result to tell us whether to use SIAR. 138 * 139 * However if the regs are from another exception, eg. a syscall, then 140 * they have not been setup using perf_read_regs() and so regs->result 141 * is something random. 142 */ 143 return ((TRAP(regs) == 0xf00) && regs->result); 144 } 145 146 /* 147 * Things that are specific to 64-bit implementations. 148 */ 149 #ifdef CONFIG_PPC64 150 151 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 152 { 153 unsigned long mmcra = regs->dsisr; 154 155 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 156 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 157 if (slot > 1) 158 return 4 * (slot - 1); 159 } 160 161 return 0; 162 } 163 164 /* 165 * The user wants a data address recorded. 166 * If we're not doing instruction sampling, give them the SDAR 167 * (sampled data address). If we are doing instruction sampling, then 168 * only give them the SDAR if it corresponds to the instruction 169 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 170 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 171 */ 172 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 173 { 174 unsigned long mmcra = regs->dsisr; 175 bool sdar_valid; 176 177 if (ppmu->flags & PPMU_HAS_SIER) 178 sdar_valid = regs->dar & SIER_SDAR_VALID; 179 else { 180 unsigned long sdsync; 181 182 if (ppmu->flags & PPMU_SIAR_VALID) 183 sdsync = POWER7P_MMCRA_SDAR_VALID; 184 else if (ppmu->flags & PPMU_ALT_SIPR) 185 sdsync = POWER6_MMCRA_SDSYNC; 186 else 187 sdsync = MMCRA_SDSYNC; 188 189 sdar_valid = mmcra & sdsync; 190 } 191 192 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 193 *addrp = mfspr(SPRN_SDAR); 194 } 195 196 static bool regs_sihv(struct pt_regs *regs) 197 { 198 unsigned long sihv = MMCRA_SIHV; 199 200 if (ppmu->flags & PPMU_HAS_SIER) 201 return !!(regs->dar & SIER_SIHV); 202 203 if (ppmu->flags & PPMU_ALT_SIPR) 204 sihv = POWER6_MMCRA_SIHV; 205 206 return !!(regs->dsisr & sihv); 207 } 208 209 static bool regs_sipr(struct pt_regs *regs) 210 { 211 unsigned long sipr = MMCRA_SIPR; 212 213 if (ppmu->flags & PPMU_HAS_SIER) 214 return !!(regs->dar & SIER_SIPR); 215 216 if (ppmu->flags & PPMU_ALT_SIPR) 217 sipr = POWER6_MMCRA_SIPR; 218 219 return !!(regs->dsisr & sipr); 220 } 221 222 static inline u32 perf_flags_from_msr(struct pt_regs *regs) 223 { 224 if (regs->msr & MSR_PR) 225 return PERF_RECORD_MISC_USER; 226 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 227 return PERF_RECORD_MISC_HYPERVISOR; 228 return PERF_RECORD_MISC_KERNEL; 229 } 230 231 static inline u32 perf_get_misc_flags(struct pt_regs *regs) 232 { 233 bool use_siar = regs_use_siar(regs); 234 235 if (!use_siar) 236 return perf_flags_from_msr(regs); 237 238 /* 239 * If we don't have flags in MMCRA, rather than using 240 * the MSR, we intuit the flags from the address in 241 * SIAR which should give slightly more reliable 242 * results 243 */ 244 if (ppmu->flags & PPMU_NO_SIPR) { 245 unsigned long siar = mfspr(SPRN_SIAR); 246 if (siar >= PAGE_OFFSET) 247 return PERF_RECORD_MISC_KERNEL; 248 return PERF_RECORD_MISC_USER; 249 } 250 251 /* PR has priority over HV, so order below is important */ 252 if (regs_sipr(regs)) 253 return PERF_RECORD_MISC_USER; 254 255 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 256 return PERF_RECORD_MISC_HYPERVISOR; 257 258 return PERF_RECORD_MISC_KERNEL; 259 } 260 261 /* 262 * Overload regs->dsisr to store MMCRA so we only need to read it once 263 * on each interrupt. 264 * Overload regs->dar to store SIER if we have it. 265 * Overload regs->result to specify whether we should use the MSR (result 266 * is zero) or the SIAR (result is non zero). 267 */ 268 static inline void perf_read_regs(struct pt_regs *regs) 269 { 270 unsigned long mmcra = mfspr(SPRN_MMCRA); 271 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 272 int use_siar; 273 274 regs->dsisr = mmcra; 275 276 if (ppmu->flags & PPMU_HAS_SIER) 277 regs->dar = mfspr(SPRN_SIER); 278 279 /* 280 * If this isn't a PMU exception (eg a software event) the SIAR is 281 * not valid. Use pt_regs. 282 * 283 * If it is a marked event use the SIAR. 284 * 285 * If the PMU doesn't update the SIAR for non marked events use 286 * pt_regs. 287 * 288 * If the PMU has HV/PR flags then check to see if they 289 * place the exception in userspace. If so, use pt_regs. In 290 * continuous sampling mode the SIAR and the PMU exception are 291 * not synchronised, so they may be many instructions apart. 292 * This can result in confusing backtraces. We still want 293 * hypervisor samples as well as samples in the kernel with 294 * interrupts off hence the userspace check. 295 */ 296 if (TRAP(regs) != 0xf00) 297 use_siar = 0; 298 else if (marked) 299 use_siar = 1; 300 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 301 use_siar = 0; 302 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 303 use_siar = 0; 304 else 305 use_siar = 1; 306 307 regs->result = use_siar; 308 } 309 310 /* 311 * If interrupts were soft-disabled when a PMU interrupt occurs, treat 312 * it as an NMI. 313 */ 314 static inline int perf_intr_is_nmi(struct pt_regs *regs) 315 { 316 return !regs->softe; 317 } 318 319 /* 320 * On processors like P7+ that have the SIAR-Valid bit, marked instructions 321 * must be sampled only if the SIAR-valid bit is set. 322 * 323 * For unmarked instructions and for processors that don't have the SIAR-Valid 324 * bit, assume that SIAR is valid. 325 */ 326 static inline int siar_valid(struct pt_regs *regs) 327 { 328 unsigned long mmcra = regs->dsisr; 329 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 330 331 if (marked) { 332 if (ppmu->flags & PPMU_HAS_SIER) 333 return regs->dar & SIER_SIAR_VALID; 334 335 if (ppmu->flags & PPMU_SIAR_VALID) 336 return mmcra & POWER7P_MMCRA_SIAR_VALID; 337 } 338 339 return 1; 340 } 341 342 343 /* Reset all possible BHRB entries */ 344 static void power_pmu_bhrb_reset(void) 345 { 346 asm volatile(PPC_CLRBHRB); 347 } 348 349 static void power_pmu_bhrb_enable(struct perf_event *event) 350 { 351 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 352 353 if (!ppmu->bhrb_nr) 354 return; 355 356 /* Clear BHRB if we changed task context to avoid data leaks */ 357 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 358 power_pmu_bhrb_reset(); 359 cpuhw->bhrb_context = event->ctx; 360 } 361 cpuhw->bhrb_users++; 362 perf_sched_cb_inc(event->ctx->pmu); 363 } 364 365 static void power_pmu_bhrb_disable(struct perf_event *event) 366 { 367 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 368 369 if (!ppmu->bhrb_nr) 370 return; 371 372 WARN_ON_ONCE(!cpuhw->bhrb_users); 373 cpuhw->bhrb_users--; 374 perf_sched_cb_dec(event->ctx->pmu); 375 376 if (!cpuhw->disabled && !cpuhw->bhrb_users) { 377 /* BHRB cannot be turned off when other 378 * events are active on the PMU. 379 */ 380 381 /* avoid stale pointer */ 382 cpuhw->bhrb_context = NULL; 383 } 384 } 385 386 /* Called from ctxsw to prevent one process's branch entries to 387 * mingle with the other process's entries during context switch. 388 */ 389 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 390 { 391 if (!ppmu->bhrb_nr) 392 return; 393 394 if (sched_in) 395 power_pmu_bhrb_reset(); 396 } 397 /* Calculate the to address for a branch */ 398 static __u64 power_pmu_bhrb_to(u64 addr) 399 { 400 unsigned int instr; 401 int ret; 402 __u64 target; 403 404 if (is_kernel_addr(addr)) 405 return branch_target((unsigned int *)addr); 406 407 /* Userspace: need copy instruction here then translate it */ 408 pagefault_disable(); 409 ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 410 if (ret) { 411 pagefault_enable(); 412 return 0; 413 } 414 pagefault_enable(); 415 416 target = branch_target(&instr); 417 if ((!target) || (instr & BRANCH_ABSOLUTE)) 418 return target; 419 420 /* Translate relative branch target from kernel to user address */ 421 return target - (unsigned long)&instr + addr; 422 } 423 424 /* Processing BHRB entries */ 425 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 426 { 427 u64 val; 428 u64 addr; 429 int r_index, u_index, pred; 430 431 r_index = 0; 432 u_index = 0; 433 while (r_index < ppmu->bhrb_nr) { 434 /* Assembly read function */ 435 val = read_bhrb(r_index++); 436 if (!val) 437 /* Terminal marker: End of valid BHRB entries */ 438 break; 439 else { 440 addr = val & BHRB_EA; 441 pred = val & BHRB_PREDICTION; 442 443 if (!addr) 444 /* invalid entry */ 445 continue; 446 447 /* Branches are read most recent first (ie. mfbhrb 0 is 448 * the most recent branch). 449 * There are two types of valid entries: 450 * 1) a target entry which is the to address of a 451 * computed goto like a blr,bctr,btar. The next 452 * entry read from the bhrb will be branch 453 * corresponding to this target (ie. the actual 454 * blr/bctr/btar instruction). 455 * 2) a from address which is an actual branch. If a 456 * target entry proceeds this, then this is the 457 * matching branch for that target. If this is not 458 * following a target entry, then this is a branch 459 * where the target is given as an immediate field 460 * in the instruction (ie. an i or b form branch). 461 * In this case we need to read the instruction from 462 * memory to determine the target/to address. 463 */ 464 465 if (val & BHRB_TARGET) { 466 /* Target branches use two entries 467 * (ie. computed gotos/XL form) 468 */ 469 cpuhw->bhrb_entries[u_index].to = addr; 470 cpuhw->bhrb_entries[u_index].mispred = pred; 471 cpuhw->bhrb_entries[u_index].predicted = ~pred; 472 473 /* Get from address in next entry */ 474 val = read_bhrb(r_index++); 475 addr = val & BHRB_EA; 476 if (val & BHRB_TARGET) { 477 /* Shouldn't have two targets in a 478 row.. Reset index and try again */ 479 r_index--; 480 addr = 0; 481 } 482 cpuhw->bhrb_entries[u_index].from = addr; 483 } else { 484 /* Branches to immediate field 485 (ie I or B form) */ 486 cpuhw->bhrb_entries[u_index].from = addr; 487 cpuhw->bhrb_entries[u_index].to = 488 power_pmu_bhrb_to(addr); 489 cpuhw->bhrb_entries[u_index].mispred = pred; 490 cpuhw->bhrb_entries[u_index].predicted = ~pred; 491 } 492 u_index++; 493 494 } 495 } 496 cpuhw->bhrb_stack.nr = u_index; 497 return; 498 } 499 500 static bool is_ebb_event(struct perf_event *event) 501 { 502 /* 503 * This could be a per-PMU callback, but we'd rather avoid the cost. We 504 * check that the PMU supports EBB, meaning those that don't can still 505 * use bit 63 of the event code for something else if they wish. 506 */ 507 return (ppmu->flags & PPMU_ARCH_207S) && 508 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 509 } 510 511 static int ebb_event_check(struct perf_event *event) 512 { 513 struct perf_event *leader = event->group_leader; 514 515 /* Event and group leader must agree on EBB */ 516 if (is_ebb_event(leader) != is_ebb_event(event)) 517 return -EINVAL; 518 519 if (is_ebb_event(event)) { 520 if (!(event->attach_state & PERF_ATTACH_TASK)) 521 return -EINVAL; 522 523 if (!leader->attr.pinned || !leader->attr.exclusive) 524 return -EINVAL; 525 526 if (event->attr.freq || 527 event->attr.inherit || 528 event->attr.sample_type || 529 event->attr.sample_period || 530 event->attr.enable_on_exec) 531 return -EINVAL; 532 } 533 534 return 0; 535 } 536 537 static void ebb_event_add(struct perf_event *event) 538 { 539 if (!is_ebb_event(event) || current->thread.used_ebb) 540 return; 541 542 /* 543 * IFF this is the first time we've added an EBB event, set 544 * PMXE in the user MMCR0 so we can detect when it's cleared by 545 * userspace. We need this so that we can context switch while 546 * userspace is in the EBB handler (where PMXE is 0). 547 */ 548 current->thread.used_ebb = 1; 549 current->thread.mmcr0 |= MMCR0_PMXE; 550 } 551 552 static void ebb_switch_out(unsigned long mmcr0) 553 { 554 if (!(mmcr0 & MMCR0_EBE)) 555 return; 556 557 current->thread.siar = mfspr(SPRN_SIAR); 558 current->thread.sier = mfspr(SPRN_SIER); 559 current->thread.sdar = mfspr(SPRN_SDAR); 560 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 561 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 562 } 563 564 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 565 { 566 unsigned long mmcr0 = cpuhw->mmcr[0]; 567 568 if (!ebb) 569 goto out; 570 571 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 572 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 573 574 /* 575 * Add any bits from the user MMCR0, FC or PMAO. This is compatible 576 * with pmao_restore_workaround() because we may add PMAO but we never 577 * clear it here. 578 */ 579 mmcr0 |= current->thread.mmcr0; 580 581 /* 582 * Be careful not to set PMXE if userspace had it cleared. This is also 583 * compatible with pmao_restore_workaround() because it has already 584 * cleared PMXE and we leave PMAO alone. 585 */ 586 if (!(current->thread.mmcr0 & MMCR0_PMXE)) 587 mmcr0 &= ~MMCR0_PMXE; 588 589 mtspr(SPRN_SIAR, current->thread.siar); 590 mtspr(SPRN_SIER, current->thread.sier); 591 mtspr(SPRN_SDAR, current->thread.sdar); 592 593 /* 594 * Merge the kernel & user values of MMCR2. The semantics we implement 595 * are that the user MMCR2 can set bits, ie. cause counters to freeze, 596 * but not clear bits. If a task wants to be able to clear bits, ie. 597 * unfreeze counters, it should not set exclude_xxx in its events and 598 * instead manage the MMCR2 entirely by itself. 599 */ 600 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); 601 out: 602 return mmcr0; 603 } 604 605 static void pmao_restore_workaround(bool ebb) 606 { 607 unsigned pmcs[6]; 608 609 if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 610 return; 611 612 /* 613 * On POWER8E there is a hardware defect which affects the PMU context 614 * switch logic, ie. power_pmu_disable/enable(). 615 * 616 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 617 * by the hardware. Sometime later the actual PMU exception is 618 * delivered. 619 * 620 * If we context switch, or simply disable/enable, the PMU prior to the 621 * exception arriving, the exception will be lost when we clear PMAO. 622 * 623 * When we reenable the PMU, we will write the saved MMCR0 with PMAO 624 * set, and this _should_ generate an exception. However because of the 625 * defect no exception is generated when we write PMAO, and we get 626 * stuck with no counters counting but no exception delivered. 627 * 628 * The workaround is to detect this case and tweak the hardware to 629 * create another pending PMU exception. 630 * 631 * We do that by setting up PMC6 (cycles) for an imminent overflow and 632 * enabling the PMU. That causes a new exception to be generated in the 633 * chip, but we don't take it yet because we have interrupts hard 634 * disabled. We then write back the PMU state as we want it to be seen 635 * by the exception handler. When we reenable interrupts the exception 636 * handler will be called and see the correct state. 637 * 638 * The logic is the same for EBB, except that the exception is gated by 639 * us having interrupts hard disabled as well as the fact that we are 640 * not in userspace. The exception is finally delivered when we return 641 * to userspace. 642 */ 643 644 /* Only if PMAO is set and PMAO_SYNC is clear */ 645 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 646 return; 647 648 /* If we're doing EBB, only if BESCR[GE] is set */ 649 if (ebb && !(current->thread.bescr & BESCR_GE)) 650 return; 651 652 /* 653 * We are already soft-disabled in power_pmu_enable(). We need to hard 654 * enable to actually prevent the PMU exception from firing. 655 */ 656 hard_irq_disable(); 657 658 /* 659 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 660 * Using read/write_pmc() in a for loop adds 12 function calls and 661 * almost doubles our code size. 662 */ 663 pmcs[0] = mfspr(SPRN_PMC1); 664 pmcs[1] = mfspr(SPRN_PMC2); 665 pmcs[2] = mfspr(SPRN_PMC3); 666 pmcs[3] = mfspr(SPRN_PMC4); 667 pmcs[4] = mfspr(SPRN_PMC5); 668 pmcs[5] = mfspr(SPRN_PMC6); 669 670 /* Ensure all freeze bits are unset */ 671 mtspr(SPRN_MMCR2, 0); 672 673 /* Set up PMC6 to overflow in one cycle */ 674 mtspr(SPRN_PMC6, 0x7FFFFFFE); 675 676 /* Enable exceptions and unfreeze PMC6 */ 677 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 678 679 /* Now we need to refreeze and restore the PMCs */ 680 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 681 682 mtspr(SPRN_PMC1, pmcs[0]); 683 mtspr(SPRN_PMC2, pmcs[1]); 684 mtspr(SPRN_PMC3, pmcs[2]); 685 mtspr(SPRN_PMC4, pmcs[3]); 686 mtspr(SPRN_PMC5, pmcs[4]); 687 mtspr(SPRN_PMC6, pmcs[5]); 688 } 689 #endif /* CONFIG_PPC64 */ 690 691 static void perf_event_interrupt(struct pt_regs *regs); 692 693 /* 694 * Read one performance monitor counter (PMC). 695 */ 696 static unsigned long read_pmc(int idx) 697 { 698 unsigned long val; 699 700 switch (idx) { 701 case 1: 702 val = mfspr(SPRN_PMC1); 703 break; 704 case 2: 705 val = mfspr(SPRN_PMC2); 706 break; 707 case 3: 708 val = mfspr(SPRN_PMC3); 709 break; 710 case 4: 711 val = mfspr(SPRN_PMC4); 712 break; 713 case 5: 714 val = mfspr(SPRN_PMC5); 715 break; 716 case 6: 717 val = mfspr(SPRN_PMC6); 718 break; 719 #ifdef CONFIG_PPC64 720 case 7: 721 val = mfspr(SPRN_PMC7); 722 break; 723 case 8: 724 val = mfspr(SPRN_PMC8); 725 break; 726 #endif /* CONFIG_PPC64 */ 727 default: 728 printk(KERN_ERR "oops trying to read PMC%d\n", idx); 729 val = 0; 730 } 731 return val; 732 } 733 734 /* 735 * Write one PMC. 736 */ 737 static void write_pmc(int idx, unsigned long val) 738 { 739 switch (idx) { 740 case 1: 741 mtspr(SPRN_PMC1, val); 742 break; 743 case 2: 744 mtspr(SPRN_PMC2, val); 745 break; 746 case 3: 747 mtspr(SPRN_PMC3, val); 748 break; 749 case 4: 750 mtspr(SPRN_PMC4, val); 751 break; 752 case 5: 753 mtspr(SPRN_PMC5, val); 754 break; 755 case 6: 756 mtspr(SPRN_PMC6, val); 757 break; 758 #ifdef CONFIG_PPC64 759 case 7: 760 mtspr(SPRN_PMC7, val); 761 break; 762 case 8: 763 mtspr(SPRN_PMC8, val); 764 break; 765 #endif /* CONFIG_PPC64 */ 766 default: 767 printk(KERN_ERR "oops trying to write PMC%d\n", idx); 768 } 769 } 770 771 /* Called from sysrq_handle_showregs() */ 772 void perf_event_print_debug(void) 773 { 774 unsigned long sdar, sier, flags; 775 u32 pmcs[MAX_HWEVENTS]; 776 int i; 777 778 if (!ppmu->n_counter) 779 return; 780 781 local_irq_save(flags); 782 783 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 784 smp_processor_id(), ppmu->name, ppmu->n_counter); 785 786 for (i = 0; i < ppmu->n_counter; i++) 787 pmcs[i] = read_pmc(i + 1); 788 789 for (; i < MAX_HWEVENTS; i++) 790 pmcs[i] = 0xdeadbeef; 791 792 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 793 pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 794 795 if (ppmu->n_counter > 4) 796 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 797 pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 798 799 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 800 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 801 802 sdar = sier = 0; 803 #ifdef CONFIG_PPC64 804 sdar = mfspr(SPRN_SDAR); 805 806 if (ppmu->flags & PPMU_HAS_SIER) 807 sier = mfspr(SPRN_SIER); 808 809 if (ppmu->flags & PPMU_ARCH_207S) { 810 pr_info("MMCR2: %016lx EBBHR: %016lx\n", 811 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 812 pr_info("EBBRR: %016lx BESCR: %016lx\n", 813 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 814 } 815 #endif 816 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 817 mfspr(SPRN_SIAR), sdar, sier); 818 819 local_irq_restore(flags); 820 } 821 822 /* 823 * Check if a set of events can all go on the PMU at once. 824 * If they can't, this will look at alternative codes for the events 825 * and see if any combination of alternative codes is feasible. 826 * The feasible set is returned in event_id[]. 827 */ 828 static int power_check_constraints(struct cpu_hw_events *cpuhw, 829 u64 event_id[], unsigned int cflags[], 830 int n_ev) 831 { 832 unsigned long mask, value, nv; 833 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 834 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 835 int i, j; 836 unsigned long addf = ppmu->add_fields; 837 unsigned long tadd = ppmu->test_adder; 838 839 if (n_ev > ppmu->n_counter) 840 return -1; 841 842 /* First see if the events will go on as-is */ 843 for (i = 0; i < n_ev; ++i) { 844 if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 845 && !ppmu->limited_pmc_event(event_id[i])) { 846 ppmu->get_alternatives(event_id[i], cflags[i], 847 cpuhw->alternatives[i]); 848 event_id[i] = cpuhw->alternatives[i][0]; 849 } 850 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 851 &cpuhw->avalues[i][0])) 852 return -1; 853 } 854 value = mask = 0; 855 for (i = 0; i < n_ev; ++i) { 856 nv = (value | cpuhw->avalues[i][0]) + 857 (value & cpuhw->avalues[i][0] & addf); 858 if ((((nv + tadd) ^ value) & mask) != 0 || 859 (((nv + tadd) ^ cpuhw->avalues[i][0]) & 860 cpuhw->amasks[i][0]) != 0) 861 break; 862 value = nv; 863 mask |= cpuhw->amasks[i][0]; 864 } 865 if (i == n_ev) 866 return 0; /* all OK */ 867 868 /* doesn't work, gather alternatives... */ 869 if (!ppmu->get_alternatives) 870 return -1; 871 for (i = 0; i < n_ev; ++i) { 872 choice[i] = 0; 873 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 874 cpuhw->alternatives[i]); 875 for (j = 1; j < n_alt[i]; ++j) 876 ppmu->get_constraint(cpuhw->alternatives[i][j], 877 &cpuhw->amasks[i][j], 878 &cpuhw->avalues[i][j]); 879 } 880 881 /* enumerate all possibilities and see if any will work */ 882 i = 0; 883 j = -1; 884 value = mask = nv = 0; 885 while (i < n_ev) { 886 if (j >= 0) { 887 /* we're backtracking, restore context */ 888 value = svalues[i]; 889 mask = smasks[i]; 890 j = choice[i]; 891 } 892 /* 893 * See if any alternative k for event_id i, 894 * where k > j, will satisfy the constraints. 895 */ 896 while (++j < n_alt[i]) { 897 nv = (value | cpuhw->avalues[i][j]) + 898 (value & cpuhw->avalues[i][j] & addf); 899 if ((((nv + tadd) ^ value) & mask) == 0 && 900 (((nv + tadd) ^ cpuhw->avalues[i][j]) 901 & cpuhw->amasks[i][j]) == 0) 902 break; 903 } 904 if (j >= n_alt[i]) { 905 /* 906 * No feasible alternative, backtrack 907 * to event_id i-1 and continue enumerating its 908 * alternatives from where we got up to. 909 */ 910 if (--i < 0) 911 return -1; 912 } else { 913 /* 914 * Found a feasible alternative for event_id i, 915 * remember where we got up to with this event_id, 916 * go on to the next event_id, and start with 917 * the first alternative for it. 918 */ 919 choice[i] = j; 920 svalues[i] = value; 921 smasks[i] = mask; 922 value = nv; 923 mask |= cpuhw->amasks[i][j]; 924 ++i; 925 j = -1; 926 } 927 } 928 929 /* OK, we have a feasible combination, tell the caller the solution */ 930 for (i = 0; i < n_ev; ++i) 931 event_id[i] = cpuhw->alternatives[i][choice[i]]; 932 return 0; 933 } 934 935 /* 936 * Check if newly-added events have consistent settings for 937 * exclude_{user,kernel,hv} with each other and any previously 938 * added events. 939 */ 940 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 941 int n_prev, int n_new) 942 { 943 int eu = 0, ek = 0, eh = 0; 944 int i, n, first; 945 struct perf_event *event; 946 947 /* 948 * If the PMU we're on supports per event exclude settings then we 949 * don't need to do any of this logic. NB. This assumes no PMU has both 950 * per event exclude and limited PMCs. 951 */ 952 if (ppmu->flags & PPMU_ARCH_207S) 953 return 0; 954 955 n = n_prev + n_new; 956 if (n <= 1) 957 return 0; 958 959 first = 1; 960 for (i = 0; i < n; ++i) { 961 if (cflags[i] & PPMU_LIMITED_PMC_OK) { 962 cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 963 continue; 964 } 965 event = ctrs[i]; 966 if (first) { 967 eu = event->attr.exclude_user; 968 ek = event->attr.exclude_kernel; 969 eh = event->attr.exclude_hv; 970 first = 0; 971 } else if (event->attr.exclude_user != eu || 972 event->attr.exclude_kernel != ek || 973 event->attr.exclude_hv != eh) { 974 return -EAGAIN; 975 } 976 } 977 978 if (eu || ek || eh) 979 for (i = 0; i < n; ++i) 980 if (cflags[i] & PPMU_LIMITED_PMC_OK) 981 cflags[i] |= PPMU_LIMITED_PMC_REQD; 982 983 return 0; 984 } 985 986 static u64 check_and_compute_delta(u64 prev, u64 val) 987 { 988 u64 delta = (val - prev) & 0xfffffffful; 989 990 /* 991 * POWER7 can roll back counter values, if the new value is smaller 992 * than the previous value it will cause the delta and the counter to 993 * have bogus values unless we rolled a counter over. If a coutner is 994 * rolled back, it will be smaller, but within 256, which is the maximum 995 * number of events to rollback at once. If we dectect a rollback 996 * return 0. This can lead to a small lack of precision in the 997 * counters. 998 */ 999 if (prev > val && (prev - val) < 256) 1000 delta = 0; 1001 1002 return delta; 1003 } 1004 1005 static void power_pmu_read(struct perf_event *event) 1006 { 1007 s64 val, delta, prev; 1008 1009 if (event->hw.state & PERF_HES_STOPPED) 1010 return; 1011 1012 if (!event->hw.idx) 1013 return; 1014 1015 if (is_ebb_event(event)) { 1016 val = read_pmc(event->hw.idx); 1017 local64_set(&event->hw.prev_count, val); 1018 return; 1019 } 1020 1021 /* 1022 * Performance monitor interrupts come even when interrupts 1023 * are soft-disabled, as long as interrupts are hard-enabled. 1024 * Therefore we treat them like NMIs. 1025 */ 1026 do { 1027 prev = local64_read(&event->hw.prev_count); 1028 barrier(); 1029 val = read_pmc(event->hw.idx); 1030 delta = check_and_compute_delta(prev, val); 1031 if (!delta) 1032 return; 1033 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1034 1035 local64_add(delta, &event->count); 1036 1037 /* 1038 * A number of places program the PMC with (0x80000000 - period_left). 1039 * We never want period_left to be less than 1 because we will program 1040 * the PMC with a value >= 0x800000000 and an edge detected PMC will 1041 * roll around to 0 before taking an exception. We have seen this 1042 * on POWER8. 1043 * 1044 * To fix this, clamp the minimum value of period_left to 1. 1045 */ 1046 do { 1047 prev = local64_read(&event->hw.period_left); 1048 val = prev - delta; 1049 if (val < 1) 1050 val = 1; 1051 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1052 } 1053 1054 /* 1055 * On some machines, PMC5 and PMC6 can't be written, don't respect 1056 * the freeze conditions, and don't generate interrupts. This tells 1057 * us if `event' is using such a PMC. 1058 */ 1059 static int is_limited_pmc(int pmcnum) 1060 { 1061 return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1062 && (pmcnum == 5 || pmcnum == 6); 1063 } 1064 1065 static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1066 unsigned long pmc5, unsigned long pmc6) 1067 { 1068 struct perf_event *event; 1069 u64 val, prev, delta; 1070 int i; 1071 1072 for (i = 0; i < cpuhw->n_limited; ++i) { 1073 event = cpuhw->limited_counter[i]; 1074 if (!event->hw.idx) 1075 continue; 1076 val = (event->hw.idx == 5) ? pmc5 : pmc6; 1077 prev = local64_read(&event->hw.prev_count); 1078 event->hw.idx = 0; 1079 delta = check_and_compute_delta(prev, val); 1080 if (delta) 1081 local64_add(delta, &event->count); 1082 } 1083 } 1084 1085 static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1086 unsigned long pmc5, unsigned long pmc6) 1087 { 1088 struct perf_event *event; 1089 u64 val, prev; 1090 int i; 1091 1092 for (i = 0; i < cpuhw->n_limited; ++i) { 1093 event = cpuhw->limited_counter[i]; 1094 event->hw.idx = cpuhw->limited_hwidx[i]; 1095 val = (event->hw.idx == 5) ? pmc5 : pmc6; 1096 prev = local64_read(&event->hw.prev_count); 1097 if (check_and_compute_delta(prev, val)) 1098 local64_set(&event->hw.prev_count, val); 1099 perf_event_update_userpage(event); 1100 } 1101 } 1102 1103 /* 1104 * Since limited events don't respect the freeze conditions, we 1105 * have to read them immediately after freezing or unfreezing the 1106 * other events. We try to keep the values from the limited 1107 * events as consistent as possible by keeping the delay (in 1108 * cycles and instructions) between freezing/unfreezing and reading 1109 * the limited events as small and consistent as possible. 1110 * Therefore, if any limited events are in use, we read them 1111 * both, and always in the same order, to minimize variability, 1112 * and do it inside the same asm that writes MMCR0. 1113 */ 1114 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1115 { 1116 unsigned long pmc5, pmc6; 1117 1118 if (!cpuhw->n_limited) { 1119 mtspr(SPRN_MMCR0, mmcr0); 1120 return; 1121 } 1122 1123 /* 1124 * Write MMCR0, then read PMC5 and PMC6 immediately. 1125 * To ensure we don't get a performance monitor interrupt 1126 * between writing MMCR0 and freezing/thawing the limited 1127 * events, we first write MMCR0 with the event overflow 1128 * interrupt enable bits turned off. 1129 */ 1130 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1131 : "=&r" (pmc5), "=&r" (pmc6) 1132 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1133 "i" (SPRN_MMCR0), 1134 "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1135 1136 if (mmcr0 & MMCR0_FC) 1137 freeze_limited_counters(cpuhw, pmc5, pmc6); 1138 else 1139 thaw_limited_counters(cpuhw, pmc5, pmc6); 1140 1141 /* 1142 * Write the full MMCR0 including the event overflow interrupt 1143 * enable bits, if necessary. 1144 */ 1145 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1146 mtspr(SPRN_MMCR0, mmcr0); 1147 } 1148 1149 /* 1150 * Disable all events to prevent PMU interrupts and to allow 1151 * events to be added or removed. 1152 */ 1153 static void power_pmu_disable(struct pmu *pmu) 1154 { 1155 struct cpu_hw_events *cpuhw; 1156 unsigned long flags, mmcr0, val; 1157 1158 if (!ppmu) 1159 return; 1160 local_irq_save(flags); 1161 cpuhw = this_cpu_ptr(&cpu_hw_events); 1162 1163 if (!cpuhw->disabled) { 1164 /* 1165 * Check if we ever enabled the PMU on this cpu. 1166 */ 1167 if (!cpuhw->pmcs_enabled) { 1168 ppc_enable_pmcs(); 1169 cpuhw->pmcs_enabled = 1; 1170 } 1171 1172 /* 1173 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1174 */ 1175 val = mmcr0 = mfspr(SPRN_MMCR0); 1176 val |= MMCR0_FC; 1177 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 1178 MMCR0_FC56); 1179 1180 /* 1181 * The barrier is to make sure the mtspr has been 1182 * executed and the PMU has frozen the events etc. 1183 * before we return. 1184 */ 1185 write_mmcr0(cpuhw, val); 1186 mb(); 1187 1188 /* 1189 * Disable instruction sampling if it was enabled 1190 */ 1191 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1192 mtspr(SPRN_MMCRA, 1193 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1194 mb(); 1195 } 1196 1197 cpuhw->disabled = 1; 1198 cpuhw->n_added = 0; 1199 1200 ebb_switch_out(mmcr0); 1201 } 1202 1203 local_irq_restore(flags); 1204 } 1205 1206 /* 1207 * Re-enable all events if disable == 0. 1208 * If we were previously disabled and events were added, then 1209 * put the new config on the PMU. 1210 */ 1211 static void power_pmu_enable(struct pmu *pmu) 1212 { 1213 struct perf_event *event; 1214 struct cpu_hw_events *cpuhw; 1215 unsigned long flags; 1216 long i; 1217 unsigned long val, mmcr0; 1218 s64 left; 1219 unsigned int hwc_index[MAX_HWEVENTS]; 1220 int n_lim; 1221 int idx; 1222 bool ebb; 1223 1224 if (!ppmu) 1225 return; 1226 local_irq_save(flags); 1227 1228 cpuhw = this_cpu_ptr(&cpu_hw_events); 1229 if (!cpuhw->disabled) 1230 goto out; 1231 1232 if (cpuhw->n_events == 0) { 1233 ppc_set_pmu_inuse(0); 1234 goto out; 1235 } 1236 1237 cpuhw->disabled = 0; 1238 1239 /* 1240 * EBB requires an exclusive group and all events must have the EBB 1241 * flag set, or not set, so we can just check a single event. Also we 1242 * know we have at least one event. 1243 */ 1244 ebb = is_ebb_event(cpuhw->event[0]); 1245 1246 /* 1247 * If we didn't change anything, or only removed events, 1248 * no need to recalculate MMCR* settings and reset the PMCs. 1249 * Just reenable the PMU with the current MMCR* settings 1250 * (possibly updated for removal of events). 1251 */ 1252 if (!cpuhw->n_added) { 1253 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1254 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1255 goto out_enable; 1256 } 1257 1258 /* 1259 * Clear all MMCR settings and recompute them for the new set of events. 1260 */ 1261 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 1262 1263 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 1264 cpuhw->mmcr, cpuhw->event)) { 1265 /* shouldn't ever get here */ 1266 printk(KERN_ERR "oops compute_mmcr failed\n"); 1267 goto out; 1268 } 1269 1270 if (!(ppmu->flags & PPMU_ARCH_207S)) { 1271 /* 1272 * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 1273 * bits for the first event. We have already checked that all 1274 * events have the same value for these bits as the first event. 1275 */ 1276 event = cpuhw->event[0]; 1277 if (event->attr.exclude_user) 1278 cpuhw->mmcr[0] |= MMCR0_FCP; 1279 if (event->attr.exclude_kernel) 1280 cpuhw->mmcr[0] |= freeze_events_kernel; 1281 if (event->attr.exclude_hv) 1282 cpuhw->mmcr[0] |= MMCR0_FCHV; 1283 } 1284 1285 /* 1286 * Write the new configuration to MMCR* with the freeze 1287 * bit set and set the hardware events to their initial values. 1288 * Then unfreeze the events. 1289 */ 1290 ppc_set_pmu_inuse(1); 1291 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1292 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1293 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1294 | MMCR0_FC); 1295 if (ppmu->flags & PPMU_ARCH_207S) 1296 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); 1297 1298 /* 1299 * Read off any pre-existing events that need to move 1300 * to another PMC. 1301 */ 1302 for (i = 0; i < cpuhw->n_events; ++i) { 1303 event = cpuhw->event[i]; 1304 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1305 power_pmu_read(event); 1306 write_pmc(event->hw.idx, 0); 1307 event->hw.idx = 0; 1308 } 1309 } 1310 1311 /* 1312 * Initialize the PMCs for all the new and moved events. 1313 */ 1314 cpuhw->n_limited = n_lim = 0; 1315 for (i = 0; i < cpuhw->n_events; ++i) { 1316 event = cpuhw->event[i]; 1317 if (event->hw.idx) 1318 continue; 1319 idx = hwc_index[i] + 1; 1320 if (is_limited_pmc(idx)) { 1321 cpuhw->limited_counter[n_lim] = event; 1322 cpuhw->limited_hwidx[n_lim] = idx; 1323 ++n_lim; 1324 continue; 1325 } 1326 1327 if (ebb) 1328 val = local64_read(&event->hw.prev_count); 1329 else { 1330 val = 0; 1331 if (event->hw.sample_period) { 1332 left = local64_read(&event->hw.period_left); 1333 if (left < 0x80000000L) 1334 val = 0x80000000L - left; 1335 } 1336 local64_set(&event->hw.prev_count, val); 1337 } 1338 1339 event->hw.idx = idx; 1340 if (event->hw.state & PERF_HES_STOPPED) 1341 val = 0; 1342 write_pmc(idx, val); 1343 1344 perf_event_update_userpage(event); 1345 } 1346 cpuhw->n_limited = n_lim; 1347 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1348 1349 out_enable: 1350 pmao_restore_workaround(ebb); 1351 1352 mmcr0 = ebb_switch_in(ebb, cpuhw); 1353 1354 mb(); 1355 if (cpuhw->bhrb_users) 1356 ppmu->config_bhrb(cpuhw->bhrb_filter); 1357 1358 write_mmcr0(cpuhw, mmcr0); 1359 1360 /* 1361 * Enable instruction sampling if necessary 1362 */ 1363 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1364 mb(); 1365 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1366 } 1367 1368 out: 1369 1370 local_irq_restore(flags); 1371 } 1372 1373 static int collect_events(struct perf_event *group, int max_count, 1374 struct perf_event *ctrs[], u64 *events, 1375 unsigned int *flags) 1376 { 1377 int n = 0; 1378 struct perf_event *event; 1379 1380 if (!is_software_event(group)) { 1381 if (n >= max_count) 1382 return -1; 1383 ctrs[n] = group; 1384 flags[n] = group->hw.event_base; 1385 events[n++] = group->hw.config; 1386 } 1387 list_for_each_entry(event, &group->sibling_list, group_entry) { 1388 if (!is_software_event(event) && 1389 event->state != PERF_EVENT_STATE_OFF) { 1390 if (n >= max_count) 1391 return -1; 1392 ctrs[n] = event; 1393 flags[n] = event->hw.event_base; 1394 events[n++] = event->hw.config; 1395 } 1396 } 1397 return n; 1398 } 1399 1400 /* 1401 * Add a event to the PMU. 1402 * If all events are not already frozen, then we disable and 1403 * re-enable the PMU in order to get hw_perf_enable to do the 1404 * actual work of reconfiguring the PMU. 1405 */ 1406 static int power_pmu_add(struct perf_event *event, int ef_flags) 1407 { 1408 struct cpu_hw_events *cpuhw; 1409 unsigned long flags; 1410 int n0; 1411 int ret = -EAGAIN; 1412 1413 local_irq_save(flags); 1414 perf_pmu_disable(event->pmu); 1415 1416 /* 1417 * Add the event to the list (if there is room) 1418 * and check whether the total set is still feasible. 1419 */ 1420 cpuhw = this_cpu_ptr(&cpu_hw_events); 1421 n0 = cpuhw->n_events; 1422 if (n0 >= ppmu->n_counter) 1423 goto out; 1424 cpuhw->event[n0] = event; 1425 cpuhw->events[n0] = event->hw.config; 1426 cpuhw->flags[n0] = event->hw.event_base; 1427 1428 /* 1429 * This event may have been disabled/stopped in record_and_restart() 1430 * because we exceeded the ->event_limit. If re-starting the event, 1431 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1432 * notification is re-enabled. 1433 */ 1434 if (!(ef_flags & PERF_EF_START)) 1435 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1436 else 1437 event->hw.state = 0; 1438 1439 /* 1440 * If group events scheduling transaction was started, 1441 * skip the schedulability test here, it will be performed 1442 * at commit time(->commit_txn) as a whole 1443 */ 1444 if (cpuhw->group_flag & PERF_EVENT_TXN) 1445 goto nocheck; 1446 1447 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1448 goto out; 1449 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1450 goto out; 1451 event->hw.config = cpuhw->events[n0]; 1452 1453 nocheck: 1454 ebb_event_add(event); 1455 1456 ++cpuhw->n_events; 1457 ++cpuhw->n_added; 1458 1459 ret = 0; 1460 out: 1461 if (has_branch_stack(event)) { 1462 power_pmu_bhrb_enable(event); 1463 cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1464 event->attr.branch_sample_type); 1465 } 1466 1467 perf_pmu_enable(event->pmu); 1468 local_irq_restore(flags); 1469 return ret; 1470 } 1471 1472 /* 1473 * Remove a event from the PMU. 1474 */ 1475 static void power_pmu_del(struct perf_event *event, int ef_flags) 1476 { 1477 struct cpu_hw_events *cpuhw; 1478 long i; 1479 unsigned long flags; 1480 1481 local_irq_save(flags); 1482 perf_pmu_disable(event->pmu); 1483 1484 power_pmu_read(event); 1485 1486 cpuhw = this_cpu_ptr(&cpu_hw_events); 1487 for (i = 0; i < cpuhw->n_events; ++i) { 1488 if (event == cpuhw->event[i]) { 1489 while (++i < cpuhw->n_events) { 1490 cpuhw->event[i-1] = cpuhw->event[i]; 1491 cpuhw->events[i-1] = cpuhw->events[i]; 1492 cpuhw->flags[i-1] = cpuhw->flags[i]; 1493 } 1494 --cpuhw->n_events; 1495 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1496 if (event->hw.idx) { 1497 write_pmc(event->hw.idx, 0); 1498 event->hw.idx = 0; 1499 } 1500 perf_event_update_userpage(event); 1501 break; 1502 } 1503 } 1504 for (i = 0; i < cpuhw->n_limited; ++i) 1505 if (event == cpuhw->limited_counter[i]) 1506 break; 1507 if (i < cpuhw->n_limited) { 1508 while (++i < cpuhw->n_limited) { 1509 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1510 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1511 } 1512 --cpuhw->n_limited; 1513 } 1514 if (cpuhw->n_events == 0) { 1515 /* disable exceptions if no events are running */ 1516 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1517 } 1518 1519 if (has_branch_stack(event)) 1520 power_pmu_bhrb_disable(event); 1521 1522 perf_pmu_enable(event->pmu); 1523 local_irq_restore(flags); 1524 } 1525 1526 /* 1527 * POWER-PMU does not support disabling individual counters, hence 1528 * program their cycle counter to their max value and ignore the interrupts. 1529 */ 1530 1531 static void power_pmu_start(struct perf_event *event, int ef_flags) 1532 { 1533 unsigned long flags; 1534 s64 left; 1535 unsigned long val; 1536 1537 if (!event->hw.idx || !event->hw.sample_period) 1538 return; 1539 1540 if (!(event->hw.state & PERF_HES_STOPPED)) 1541 return; 1542 1543 if (ef_flags & PERF_EF_RELOAD) 1544 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1545 1546 local_irq_save(flags); 1547 perf_pmu_disable(event->pmu); 1548 1549 event->hw.state = 0; 1550 left = local64_read(&event->hw.period_left); 1551 1552 val = 0; 1553 if (left < 0x80000000L) 1554 val = 0x80000000L - left; 1555 1556 write_pmc(event->hw.idx, val); 1557 1558 perf_event_update_userpage(event); 1559 perf_pmu_enable(event->pmu); 1560 local_irq_restore(flags); 1561 } 1562 1563 static void power_pmu_stop(struct perf_event *event, int ef_flags) 1564 { 1565 unsigned long flags; 1566 1567 if (!event->hw.idx || !event->hw.sample_period) 1568 return; 1569 1570 if (event->hw.state & PERF_HES_STOPPED) 1571 return; 1572 1573 local_irq_save(flags); 1574 perf_pmu_disable(event->pmu); 1575 1576 power_pmu_read(event); 1577 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1578 write_pmc(event->hw.idx, 0); 1579 1580 perf_event_update_userpage(event); 1581 perf_pmu_enable(event->pmu); 1582 local_irq_restore(flags); 1583 } 1584 1585 /* 1586 * Start group events scheduling transaction 1587 * Set the flag to make pmu::enable() not perform the 1588 * schedulability test, it will be performed at commit time 1589 */ 1590 static void power_pmu_start_txn(struct pmu *pmu) 1591 { 1592 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1593 1594 perf_pmu_disable(pmu); 1595 cpuhw->group_flag |= PERF_EVENT_TXN; 1596 cpuhw->n_txn_start = cpuhw->n_events; 1597 } 1598 1599 /* 1600 * Stop group events scheduling transaction 1601 * Clear the flag and pmu::enable() will perform the 1602 * schedulability test. 1603 */ 1604 static void power_pmu_cancel_txn(struct pmu *pmu) 1605 { 1606 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1607 1608 cpuhw->group_flag &= ~PERF_EVENT_TXN; 1609 perf_pmu_enable(pmu); 1610 } 1611 1612 /* 1613 * Commit group events scheduling transaction 1614 * Perform the group schedulability test as a whole 1615 * Return 0 if success 1616 */ 1617 static int power_pmu_commit_txn(struct pmu *pmu) 1618 { 1619 struct cpu_hw_events *cpuhw; 1620 long i, n; 1621 1622 if (!ppmu) 1623 return -EAGAIN; 1624 cpuhw = this_cpu_ptr(&cpu_hw_events); 1625 n = cpuhw->n_events; 1626 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1627 return -EAGAIN; 1628 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1629 if (i < 0) 1630 return -EAGAIN; 1631 1632 for (i = cpuhw->n_txn_start; i < n; ++i) 1633 cpuhw->event[i]->hw.config = cpuhw->events[i]; 1634 1635 cpuhw->group_flag &= ~PERF_EVENT_TXN; 1636 perf_pmu_enable(pmu); 1637 return 0; 1638 } 1639 1640 /* 1641 * Return 1 if we might be able to put event on a limited PMC, 1642 * or 0 if not. 1643 * A event can only go on a limited PMC if it counts something 1644 * that a limited PMC can count, doesn't require interrupts, and 1645 * doesn't exclude any processor mode. 1646 */ 1647 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1648 unsigned int flags) 1649 { 1650 int n; 1651 u64 alt[MAX_EVENT_ALTERNATIVES]; 1652 1653 if (event->attr.exclude_user 1654 || event->attr.exclude_kernel 1655 || event->attr.exclude_hv 1656 || event->attr.sample_period) 1657 return 0; 1658 1659 if (ppmu->limited_pmc_event(ev)) 1660 return 1; 1661 1662 /* 1663 * The requested event_id isn't on a limited PMC already; 1664 * see if any alternative code goes on a limited PMC. 1665 */ 1666 if (!ppmu->get_alternatives) 1667 return 0; 1668 1669 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1670 n = ppmu->get_alternatives(ev, flags, alt); 1671 1672 return n > 0; 1673 } 1674 1675 /* 1676 * Find an alternative event_id that goes on a normal PMC, if possible, 1677 * and return the event_id code, or 0 if there is no such alternative. 1678 * (Note: event_id code 0 is "don't count" on all machines.) 1679 */ 1680 static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1681 { 1682 u64 alt[MAX_EVENT_ALTERNATIVES]; 1683 int n; 1684 1685 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1686 n = ppmu->get_alternatives(ev, flags, alt); 1687 if (!n) 1688 return 0; 1689 return alt[0]; 1690 } 1691 1692 /* Number of perf_events counting hardware events */ 1693 static atomic_t num_events; 1694 /* Used to avoid races in calling reserve/release_pmc_hardware */ 1695 static DEFINE_MUTEX(pmc_reserve_mutex); 1696 1697 /* 1698 * Release the PMU if this is the last perf_event. 1699 */ 1700 static void hw_perf_event_destroy(struct perf_event *event) 1701 { 1702 if (!atomic_add_unless(&num_events, -1, 1)) { 1703 mutex_lock(&pmc_reserve_mutex); 1704 if (atomic_dec_return(&num_events) == 0) 1705 release_pmc_hardware(); 1706 mutex_unlock(&pmc_reserve_mutex); 1707 } 1708 } 1709 1710 /* 1711 * Translate a generic cache event_id config to a raw event_id code. 1712 */ 1713 static int hw_perf_cache_event(u64 config, u64 *eventp) 1714 { 1715 unsigned long type, op, result; 1716 int ev; 1717 1718 if (!ppmu->cache_events) 1719 return -EINVAL; 1720 1721 /* unpack config */ 1722 type = config & 0xff; 1723 op = (config >> 8) & 0xff; 1724 result = (config >> 16) & 0xff; 1725 1726 if (type >= PERF_COUNT_HW_CACHE_MAX || 1727 op >= PERF_COUNT_HW_CACHE_OP_MAX || 1728 result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1729 return -EINVAL; 1730 1731 ev = (*ppmu->cache_events)[type][op][result]; 1732 if (ev == 0) 1733 return -EOPNOTSUPP; 1734 if (ev == -1) 1735 return -EINVAL; 1736 *eventp = ev; 1737 return 0; 1738 } 1739 1740 static int power_pmu_event_init(struct perf_event *event) 1741 { 1742 u64 ev; 1743 unsigned long flags; 1744 struct perf_event *ctrs[MAX_HWEVENTS]; 1745 u64 events[MAX_HWEVENTS]; 1746 unsigned int cflags[MAX_HWEVENTS]; 1747 int n; 1748 int err; 1749 struct cpu_hw_events *cpuhw; 1750 1751 if (!ppmu) 1752 return -ENOENT; 1753 1754 if (has_branch_stack(event)) { 1755 /* PMU has BHRB enabled */ 1756 if (!(ppmu->flags & PPMU_ARCH_207S)) 1757 return -EOPNOTSUPP; 1758 } 1759 1760 switch (event->attr.type) { 1761 case PERF_TYPE_HARDWARE: 1762 ev = event->attr.config; 1763 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1764 return -EOPNOTSUPP; 1765 ev = ppmu->generic_events[ev]; 1766 break; 1767 case PERF_TYPE_HW_CACHE: 1768 err = hw_perf_cache_event(event->attr.config, &ev); 1769 if (err) 1770 return err; 1771 break; 1772 case PERF_TYPE_RAW: 1773 ev = event->attr.config; 1774 break; 1775 default: 1776 return -ENOENT; 1777 } 1778 1779 event->hw.config_base = ev; 1780 event->hw.idx = 0; 1781 1782 /* 1783 * If we are not running on a hypervisor, force the 1784 * exclude_hv bit to 0 so that we don't care what 1785 * the user set it to. 1786 */ 1787 if (!firmware_has_feature(FW_FEATURE_LPAR)) 1788 event->attr.exclude_hv = 0; 1789 1790 /* 1791 * If this is a per-task event, then we can use 1792 * PM_RUN_* events interchangeably with their non RUN_* 1793 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1794 * XXX we should check if the task is an idle task. 1795 */ 1796 flags = 0; 1797 if (event->attach_state & PERF_ATTACH_TASK) 1798 flags |= PPMU_ONLY_COUNT_RUN; 1799 1800 /* 1801 * If this machine has limited events, check whether this 1802 * event_id could go on a limited event. 1803 */ 1804 if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1805 if (can_go_on_limited_pmc(event, ev, flags)) { 1806 flags |= PPMU_LIMITED_PMC_OK; 1807 } else if (ppmu->limited_pmc_event(ev)) { 1808 /* 1809 * The requested event_id is on a limited PMC, 1810 * but we can't use a limited PMC; see if any 1811 * alternative goes on a normal PMC. 1812 */ 1813 ev = normal_pmc_alternative(ev, flags); 1814 if (!ev) 1815 return -EINVAL; 1816 } 1817 } 1818 1819 /* Extra checks for EBB */ 1820 err = ebb_event_check(event); 1821 if (err) 1822 return err; 1823 1824 /* 1825 * If this is in a group, check if it can go on with all the 1826 * other hardware events in the group. We assume the event 1827 * hasn't been linked into its leader's sibling list at this point. 1828 */ 1829 n = 0; 1830 if (event->group_leader != event) { 1831 n = collect_events(event->group_leader, ppmu->n_counter - 1, 1832 ctrs, events, cflags); 1833 if (n < 0) 1834 return -EINVAL; 1835 } 1836 events[n] = ev; 1837 ctrs[n] = event; 1838 cflags[n] = flags; 1839 if (check_excludes(ctrs, cflags, n, 1)) 1840 return -EINVAL; 1841 1842 cpuhw = &get_cpu_var(cpu_hw_events); 1843 err = power_check_constraints(cpuhw, events, cflags, n + 1); 1844 1845 if (has_branch_stack(event)) { 1846 cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1847 event->attr.branch_sample_type); 1848 1849 if (cpuhw->bhrb_filter == -1) { 1850 put_cpu_var(cpu_hw_events); 1851 return -EOPNOTSUPP; 1852 } 1853 } 1854 1855 put_cpu_var(cpu_hw_events); 1856 if (err) 1857 return -EINVAL; 1858 1859 event->hw.config = events[n]; 1860 event->hw.event_base = cflags[n]; 1861 event->hw.last_period = event->hw.sample_period; 1862 local64_set(&event->hw.period_left, event->hw.last_period); 1863 1864 /* 1865 * For EBB events we just context switch the PMC value, we don't do any 1866 * of the sample_period logic. We use hw.prev_count for this. 1867 */ 1868 if (is_ebb_event(event)) 1869 local64_set(&event->hw.prev_count, 0); 1870 1871 /* 1872 * See if we need to reserve the PMU. 1873 * If no events are currently in use, then we have to take a 1874 * mutex to ensure that we don't race with another task doing 1875 * reserve_pmc_hardware or release_pmc_hardware. 1876 */ 1877 err = 0; 1878 if (!atomic_inc_not_zero(&num_events)) { 1879 mutex_lock(&pmc_reserve_mutex); 1880 if (atomic_read(&num_events) == 0 && 1881 reserve_pmc_hardware(perf_event_interrupt)) 1882 err = -EBUSY; 1883 else 1884 atomic_inc(&num_events); 1885 mutex_unlock(&pmc_reserve_mutex); 1886 } 1887 event->destroy = hw_perf_event_destroy; 1888 1889 return err; 1890 } 1891 1892 static int power_pmu_event_idx(struct perf_event *event) 1893 { 1894 return event->hw.idx; 1895 } 1896 1897 ssize_t power_events_sysfs_show(struct device *dev, 1898 struct device_attribute *attr, char *page) 1899 { 1900 struct perf_pmu_events_attr *pmu_attr; 1901 1902 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 1903 1904 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 1905 } 1906 1907 static struct pmu power_pmu = { 1908 .pmu_enable = power_pmu_enable, 1909 .pmu_disable = power_pmu_disable, 1910 .event_init = power_pmu_event_init, 1911 .add = power_pmu_add, 1912 .del = power_pmu_del, 1913 .start = power_pmu_start, 1914 .stop = power_pmu_stop, 1915 .read = power_pmu_read, 1916 .start_txn = power_pmu_start_txn, 1917 .cancel_txn = power_pmu_cancel_txn, 1918 .commit_txn = power_pmu_commit_txn, 1919 .event_idx = power_pmu_event_idx, 1920 .sched_task = power_pmu_sched_task, 1921 }; 1922 1923 /* 1924 * A counter has overflowed; update its count and record 1925 * things if requested. Note that interrupts are hard-disabled 1926 * here so there is no possibility of being interrupted. 1927 */ 1928 static void record_and_restart(struct perf_event *event, unsigned long val, 1929 struct pt_regs *regs) 1930 { 1931 u64 period = event->hw.sample_period; 1932 s64 prev, delta, left; 1933 int record = 0; 1934 1935 if (event->hw.state & PERF_HES_STOPPED) { 1936 write_pmc(event->hw.idx, 0); 1937 return; 1938 } 1939 1940 /* we don't have to worry about interrupts here */ 1941 prev = local64_read(&event->hw.prev_count); 1942 delta = check_and_compute_delta(prev, val); 1943 local64_add(delta, &event->count); 1944 1945 /* 1946 * See if the total period for this event has expired, 1947 * and update for the next period. 1948 */ 1949 val = 0; 1950 left = local64_read(&event->hw.period_left) - delta; 1951 if (delta == 0) 1952 left++; 1953 if (period) { 1954 if (left <= 0) { 1955 left += period; 1956 if (left <= 0) 1957 left = period; 1958 record = siar_valid(regs); 1959 event->hw.last_period = event->hw.sample_period; 1960 } 1961 if (left < 0x80000000LL) 1962 val = 0x80000000LL - left; 1963 } 1964 1965 write_pmc(event->hw.idx, val); 1966 local64_set(&event->hw.prev_count, val); 1967 local64_set(&event->hw.period_left, left); 1968 perf_event_update_userpage(event); 1969 1970 /* 1971 * Finally record data if requested. 1972 */ 1973 if (record) { 1974 struct perf_sample_data data; 1975 1976 perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 1977 1978 if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1979 perf_get_data_addr(regs, &data.addr); 1980 1981 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 1982 struct cpu_hw_events *cpuhw; 1983 cpuhw = this_cpu_ptr(&cpu_hw_events); 1984 power_pmu_bhrb_read(cpuhw); 1985 data.br_stack = &cpuhw->bhrb_stack; 1986 } 1987 1988 if (perf_event_overflow(event, &data, regs)) 1989 power_pmu_stop(event, 0); 1990 } 1991 } 1992 1993 /* 1994 * Called from generic code to get the misc flags (i.e. processor mode) 1995 * for an event_id. 1996 */ 1997 unsigned long perf_misc_flags(struct pt_regs *regs) 1998 { 1999 u32 flags = perf_get_misc_flags(regs); 2000 2001 if (flags) 2002 return flags; 2003 return user_mode(regs) ? PERF_RECORD_MISC_USER : 2004 PERF_RECORD_MISC_KERNEL; 2005 } 2006 2007 /* 2008 * Called from generic code to get the instruction pointer 2009 * for an event_id. 2010 */ 2011 unsigned long perf_instruction_pointer(struct pt_regs *regs) 2012 { 2013 bool use_siar = regs_use_siar(regs); 2014 2015 if (use_siar && siar_valid(regs)) 2016 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2017 else if (use_siar) 2018 return 0; // no valid instruction pointer 2019 else 2020 return regs->nip; 2021 } 2022 2023 static bool pmc_overflow_power7(unsigned long val) 2024 { 2025 /* 2026 * Events on POWER7 can roll back if a speculative event doesn't 2027 * eventually complete. Unfortunately in some rare cases they will 2028 * raise a performance monitor exception. We need to catch this to 2029 * ensure we reset the PMC. In all cases the PMC will be 256 or less 2030 * cycles from overflow. 2031 * 2032 * We only do this if the first pass fails to find any overflowing 2033 * PMCs because a user might set a period of less than 256 and we 2034 * don't want to mistakenly reset them. 2035 */ 2036 if ((0x80000000 - val) <= 256) 2037 return true; 2038 2039 return false; 2040 } 2041 2042 static bool pmc_overflow(unsigned long val) 2043 { 2044 if ((int)val < 0) 2045 return true; 2046 2047 return false; 2048 } 2049 2050 /* 2051 * Performance monitor interrupt stuff 2052 */ 2053 static void perf_event_interrupt(struct pt_regs *regs) 2054 { 2055 int i, j; 2056 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2057 struct perf_event *event; 2058 unsigned long val[8]; 2059 int found, active; 2060 int nmi; 2061 2062 if (cpuhw->n_limited) 2063 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2064 mfspr(SPRN_PMC6)); 2065 2066 perf_read_regs(regs); 2067 2068 nmi = perf_intr_is_nmi(regs); 2069 if (nmi) 2070 nmi_enter(); 2071 else 2072 irq_enter(); 2073 2074 /* Read all the PMCs since we'll need them a bunch of times */ 2075 for (i = 0; i < ppmu->n_counter; ++i) 2076 val[i] = read_pmc(i + 1); 2077 2078 /* Try to find what caused the IRQ */ 2079 found = 0; 2080 for (i = 0; i < ppmu->n_counter; ++i) { 2081 if (!pmc_overflow(val[i])) 2082 continue; 2083 if (is_limited_pmc(i + 1)) 2084 continue; /* these won't generate IRQs */ 2085 /* 2086 * We've found one that's overflowed. For active 2087 * counters we need to log this. For inactive 2088 * counters, we need to reset it anyway 2089 */ 2090 found = 1; 2091 active = 0; 2092 for (j = 0; j < cpuhw->n_events; ++j) { 2093 event = cpuhw->event[j]; 2094 if (event->hw.idx == (i + 1)) { 2095 active = 1; 2096 record_and_restart(event, val[i], regs); 2097 break; 2098 } 2099 } 2100 if (!active) 2101 /* reset non active counters that have overflowed */ 2102 write_pmc(i + 1, 0); 2103 } 2104 if (!found && pvr_version_is(PVR_POWER7)) { 2105 /* check active counters for special buggy p7 overflow */ 2106 for (i = 0; i < cpuhw->n_events; ++i) { 2107 event = cpuhw->event[i]; 2108 if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2109 continue; 2110 if (pmc_overflow_power7(val[event->hw.idx - 1])) { 2111 /* event has overflowed in a buggy way*/ 2112 found = 1; 2113 record_and_restart(event, 2114 val[event->hw.idx - 1], 2115 regs); 2116 } 2117 } 2118 } 2119 if (!found && !nmi && printk_ratelimit()) 2120 printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2121 2122 /* 2123 * Reset MMCR0 to its normal value. This will set PMXE and 2124 * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2125 * and thus allow interrupts to occur again. 2126 * XXX might want to use MSR.PM to keep the events frozen until 2127 * we get back out of this interrupt. 2128 */ 2129 write_mmcr0(cpuhw, cpuhw->mmcr[0]); 2130 2131 if (nmi) 2132 nmi_exit(); 2133 else 2134 irq_exit(); 2135 } 2136 2137 static void power_pmu_setup(int cpu) 2138 { 2139 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2140 2141 if (!ppmu) 2142 return; 2143 memset(cpuhw, 0, sizeof(*cpuhw)); 2144 cpuhw->mmcr[0] = MMCR0_FC; 2145 } 2146 2147 static int 2148 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) 2149 { 2150 unsigned int cpu = (long)hcpu; 2151 2152 switch (action & ~CPU_TASKS_FROZEN) { 2153 case CPU_UP_PREPARE: 2154 power_pmu_setup(cpu); 2155 break; 2156 2157 default: 2158 break; 2159 } 2160 2161 return NOTIFY_OK; 2162 } 2163 2164 int register_power_pmu(struct power_pmu *pmu) 2165 { 2166 if (ppmu) 2167 return -EBUSY; /* something's already registered */ 2168 2169 ppmu = pmu; 2170 pr_info("%s performance monitor hardware support registered\n", 2171 pmu->name); 2172 2173 power_pmu.attr_groups = ppmu->attr_groups; 2174 2175 #ifdef MSR_HV 2176 /* 2177 * Use FCHV to ignore kernel events if MSR.HV is set. 2178 */ 2179 if (mfmsr() & MSR_HV) 2180 freeze_events_kernel = MMCR0_FCHV; 2181 #endif /* CONFIG_PPC64 */ 2182 2183 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 2184 perf_cpu_notifier(power_pmu_notifier); 2185 2186 return 0; 2187 } 2188