1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance event support - powerpc architecture code 4 * 5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/perf_event.h> 11 #include <linux/percpu.h> 12 #include <linux/hardirq.h> 13 #include <linux/uaccess.h> 14 #include <asm/reg.h> 15 #include <asm/pmc.h> 16 #include <asm/machdep.h> 17 #include <asm/firmware.h> 18 #include <asm/ptrace.h> 19 #include <asm/code-patching.h> 20 #include <asm/hw_irq.h> 21 #include <asm/interrupt.h> 22 23 #ifdef CONFIG_PPC64 24 #include "internal.h" 25 #endif 26 27 #define BHRB_MAX_ENTRIES 32 28 #define BHRB_TARGET 0x0000000000000002 29 #define BHRB_PREDICTION 0x0000000000000001 30 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 31 32 struct cpu_hw_events { 33 int n_events; 34 int n_percpu; 35 int disabled; 36 int n_added; 37 int n_limited; 38 u8 pmcs_enabled; 39 struct perf_event *event[MAX_HWEVENTS]; 40 u64 events[MAX_HWEVENTS]; 41 unsigned int flags[MAX_HWEVENTS]; 42 struct mmcr_regs mmcr; 43 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 44 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 45 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 46 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 47 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 48 49 unsigned int txn_flags; 50 int n_txn_start; 51 52 /* BHRB bits */ 53 u64 bhrb_filter; /* BHRB HW branch filter */ 54 unsigned int bhrb_users; 55 void *bhrb_context; 56 struct perf_branch_stack bhrb_stack; 57 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 58 u64 ic_init; 59 60 /* Store the PMC values */ 61 unsigned long pmcs[MAX_HWEVENTS]; 62 }; 63 64 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 65 66 static struct power_pmu *ppmu; 67 68 /* 69 * Normally, to ignore kernel events we set the FCS (freeze counters 70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the 71 * hypervisor bit set in the MSR, or if we are running on a processor 72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 73 * then we need to use the FCHV bit to ignore kernel events. 74 */ 75 static unsigned int freeze_events_kernel = MMCR0_FCS; 76 77 /* 78 * 32-bit doesn't have MMCRA but does have an MMCR2, 79 * and a few other names are different. 80 * Also 32-bit doesn't have MMCR3, SIER2 and SIER3. 81 * Define them as zero knowing that any code path accessing 82 * these registers (via mtspr/mfspr) are done under ppmu flag 83 * check for PPMU_ARCH_31 and we will not enter that code path 84 * for 32-bit. 85 */ 86 #ifdef CONFIG_PPC32 87 88 #define MMCR0_FCHV 0 89 #define MMCR0_PMCjCE MMCR0_PMCnCE 90 #define MMCR0_FC56 0 91 #define MMCR0_PMAO 0 92 #define MMCR0_EBE 0 93 #define MMCR0_BHRBA 0 94 #define MMCR0_PMCC 0 95 #define MMCR0_PMCC_U6 0 96 97 #define SPRN_MMCRA SPRN_MMCR2 98 #define SPRN_MMCR3 0 99 #define SPRN_SIER2 0 100 #define SPRN_SIER3 0 101 #define MMCRA_SAMPLE_ENABLE 0 102 #define MMCRA_BHRB_DISABLE 0 103 #define MMCR0_PMCCEXT 0 104 105 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 106 { 107 return 0; 108 } 109 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { } 110 static inline u32 perf_get_misc_flags(struct pt_regs *regs) 111 { 112 return 0; 113 } 114 static inline void perf_read_regs(struct pt_regs *regs) 115 { 116 regs->result = 0; 117 } 118 119 static inline int siar_valid(struct pt_regs *regs) 120 { 121 return 1; 122 } 123 124 static bool is_ebb_event(struct perf_event *event) { return false; } 125 static int ebb_event_check(struct perf_event *event) { return 0; } 126 static void ebb_event_add(struct perf_event *event) { } 127 static void ebb_switch_out(unsigned long mmcr0) { } 128 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 129 { 130 return cpuhw->mmcr.mmcr0; 131 } 132 133 static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 134 static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 135 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 136 static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {} 137 static void pmao_restore_workaround(bool ebb) { } 138 #endif /* CONFIG_PPC32 */ 139 140 bool is_sier_available(void) 141 { 142 if (!ppmu) 143 return false; 144 145 if (ppmu->flags & PPMU_HAS_SIER) 146 return true; 147 148 return false; 149 } 150 151 /* 152 * Return PMC value corresponding to the 153 * index passed. 154 */ 155 unsigned long get_pmcs_ext_regs(int idx) 156 { 157 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 158 159 return cpuhw->pmcs[idx]; 160 } 161 162 static bool regs_use_siar(struct pt_regs *regs) 163 { 164 /* 165 * When we take a performance monitor exception the regs are setup 166 * using perf_read_regs() which overloads some fields, in particular 167 * regs->result to tell us whether to use SIAR. 168 * 169 * However if the regs are from another exception, eg. a syscall, then 170 * they have not been setup using perf_read_regs() and so regs->result 171 * is something random. 172 */ 173 return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result); 174 } 175 176 /* 177 * Things that are specific to 64-bit implementations. 178 */ 179 #ifdef CONFIG_PPC64 180 181 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 182 { 183 unsigned long mmcra = regs->dsisr; 184 185 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 186 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 187 if (slot > 1) 188 return 4 * (slot - 1); 189 } 190 191 return 0; 192 } 193 194 /* 195 * The user wants a data address recorded. 196 * If we're not doing instruction sampling, give them the SDAR 197 * (sampled data address). If we are doing instruction sampling, then 198 * only give them the SDAR if it corresponds to the instruction 199 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 200 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 201 */ 202 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) 203 { 204 unsigned long mmcra = regs->dsisr; 205 bool sdar_valid; 206 207 if (ppmu->flags & PPMU_HAS_SIER) 208 sdar_valid = regs->dar & SIER_SDAR_VALID; 209 else { 210 unsigned long sdsync; 211 212 if (ppmu->flags & PPMU_SIAR_VALID) 213 sdsync = POWER7P_MMCRA_SDAR_VALID; 214 else if (ppmu->flags & PPMU_ALT_SIPR) 215 sdsync = POWER6_MMCRA_SDSYNC; 216 else if (ppmu->flags & PPMU_NO_SIAR) 217 sdsync = MMCRA_SAMPLE_ENABLE; 218 else 219 sdsync = MMCRA_SDSYNC; 220 221 sdar_valid = mmcra & sdsync; 222 } 223 224 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 225 *addrp = mfspr(SPRN_SDAR); 226 227 if (is_kernel_addr(mfspr(SPRN_SDAR)) && event->attr.exclude_kernel) 228 *addrp = 0; 229 } 230 231 static bool regs_sihv(struct pt_regs *regs) 232 { 233 unsigned long sihv = MMCRA_SIHV; 234 235 if (ppmu->flags & PPMU_HAS_SIER) 236 return !!(regs->dar & SIER_SIHV); 237 238 if (ppmu->flags & PPMU_ALT_SIPR) 239 sihv = POWER6_MMCRA_SIHV; 240 241 return !!(regs->dsisr & sihv); 242 } 243 244 static bool regs_sipr(struct pt_regs *regs) 245 { 246 unsigned long sipr = MMCRA_SIPR; 247 248 if (ppmu->flags & PPMU_HAS_SIER) 249 return !!(regs->dar & SIER_SIPR); 250 251 if (ppmu->flags & PPMU_ALT_SIPR) 252 sipr = POWER6_MMCRA_SIPR; 253 254 return !!(regs->dsisr & sipr); 255 } 256 257 static inline u32 perf_flags_from_msr(struct pt_regs *regs) 258 { 259 if (regs->msr & MSR_PR) 260 return PERF_RECORD_MISC_USER; 261 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 262 return PERF_RECORD_MISC_HYPERVISOR; 263 return PERF_RECORD_MISC_KERNEL; 264 } 265 266 static inline u32 perf_get_misc_flags(struct pt_regs *regs) 267 { 268 bool use_siar = regs_use_siar(regs); 269 unsigned long mmcra = regs->dsisr; 270 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 271 272 if (!use_siar) 273 return perf_flags_from_msr(regs); 274 275 /* 276 * Check the address in SIAR to identify the 277 * privilege levels since the SIER[MSR_HV, MSR_PR] 278 * bits are not set for marked events in power10 279 * DD1. 280 */ 281 if (marked && (ppmu->flags & PPMU_P10_DD1)) { 282 unsigned long siar = mfspr(SPRN_SIAR); 283 if (siar) { 284 if (is_kernel_addr(siar)) 285 return PERF_RECORD_MISC_KERNEL; 286 return PERF_RECORD_MISC_USER; 287 } else { 288 if (is_kernel_addr(regs->nip)) 289 return PERF_RECORD_MISC_KERNEL; 290 return PERF_RECORD_MISC_USER; 291 } 292 } 293 294 /* 295 * If we don't have flags in MMCRA, rather than using 296 * the MSR, we intuit the flags from the address in 297 * SIAR which should give slightly more reliable 298 * results 299 */ 300 if (ppmu->flags & PPMU_NO_SIPR) { 301 unsigned long siar = mfspr(SPRN_SIAR); 302 if (is_kernel_addr(siar)) 303 return PERF_RECORD_MISC_KERNEL; 304 return PERF_RECORD_MISC_USER; 305 } 306 307 /* PR has priority over HV, so order below is important */ 308 if (regs_sipr(regs)) 309 return PERF_RECORD_MISC_USER; 310 311 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 312 return PERF_RECORD_MISC_HYPERVISOR; 313 314 return PERF_RECORD_MISC_KERNEL; 315 } 316 317 /* 318 * Overload regs->dsisr to store MMCRA so we only need to read it once 319 * on each interrupt. 320 * Overload regs->dar to store SIER if we have it. 321 * Overload regs->result to specify whether we should use the MSR (result 322 * is zero) or the SIAR (result is non zero). 323 */ 324 static inline void perf_read_regs(struct pt_regs *regs) 325 { 326 unsigned long mmcra = mfspr(SPRN_MMCRA); 327 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 328 int use_siar; 329 330 regs->dsisr = mmcra; 331 332 if (ppmu->flags & PPMU_HAS_SIER) 333 regs->dar = mfspr(SPRN_SIER); 334 335 /* 336 * If this isn't a PMU exception (eg a software event) the SIAR is 337 * not valid. Use pt_regs. 338 * 339 * If it is a marked event use the SIAR. 340 * 341 * If the PMU doesn't update the SIAR for non marked events use 342 * pt_regs. 343 * 344 * If regs is a kernel interrupt, always use SIAR. Some PMUs have an 345 * issue with regs_sipr not being in synch with SIAR in interrupt entry 346 * and return sequences, which can result in regs_sipr being true for 347 * kernel interrupts and SIAR, which has the effect of causing samples 348 * to pile up at mtmsrd MSR[EE] 0->1 or pending irq replay around 349 * interrupt entry/exit. 350 * 351 * If the PMU has HV/PR flags then check to see if they 352 * place the exception in userspace. If so, use pt_regs. In 353 * continuous sampling mode the SIAR and the PMU exception are 354 * not synchronised, so they may be many instructions apart. 355 * This can result in confusing backtraces. We still want 356 * hypervisor samples as well as samples in the kernel with 357 * interrupts off hence the userspace check. 358 */ 359 if (TRAP(regs) != INTERRUPT_PERFMON) 360 use_siar = 0; 361 else if ((ppmu->flags & PPMU_NO_SIAR)) 362 use_siar = 0; 363 else if (marked) 364 use_siar = 1; 365 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 366 use_siar = 0; 367 else if (!user_mode(regs)) 368 use_siar = 1; 369 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 370 use_siar = 0; 371 else 372 use_siar = 1; 373 374 regs->result = use_siar; 375 } 376 377 /* 378 * On processors like P7+ that have the SIAR-Valid bit, marked instructions 379 * must be sampled only if the SIAR-valid bit is set. 380 * 381 * For unmarked instructions and for processors that don't have the SIAR-Valid 382 * bit, assume that SIAR is valid. 383 */ 384 static inline int siar_valid(struct pt_regs *regs) 385 { 386 unsigned long mmcra = regs->dsisr; 387 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 388 389 if (marked) { 390 /* 391 * SIER[SIAR_VALID] is not set for some 392 * marked events on power10 DD1, so drop 393 * the check for SIER[SIAR_VALID] and return true. 394 */ 395 if (ppmu->flags & PPMU_P10_DD1) 396 return 0x1; 397 else if (ppmu->flags & PPMU_HAS_SIER) 398 return regs->dar & SIER_SIAR_VALID; 399 400 if (ppmu->flags & PPMU_SIAR_VALID) 401 return mmcra & POWER7P_MMCRA_SIAR_VALID; 402 } 403 404 return 1; 405 } 406 407 408 /* Reset all possible BHRB entries */ 409 static void power_pmu_bhrb_reset(void) 410 { 411 asm volatile(PPC_CLRBHRB); 412 } 413 414 static void power_pmu_bhrb_enable(struct perf_event *event) 415 { 416 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 417 418 if (!ppmu->bhrb_nr) 419 return; 420 421 /* Clear BHRB if we changed task context to avoid data leaks */ 422 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 423 power_pmu_bhrb_reset(); 424 cpuhw->bhrb_context = event->ctx; 425 } 426 cpuhw->bhrb_users++; 427 perf_sched_cb_inc(event->ctx->pmu); 428 } 429 430 static void power_pmu_bhrb_disable(struct perf_event *event) 431 { 432 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 433 434 if (!ppmu->bhrb_nr) 435 return; 436 437 WARN_ON_ONCE(!cpuhw->bhrb_users); 438 cpuhw->bhrb_users--; 439 perf_sched_cb_dec(event->ctx->pmu); 440 441 if (!cpuhw->disabled && !cpuhw->bhrb_users) { 442 /* BHRB cannot be turned off when other 443 * events are active on the PMU. 444 */ 445 446 /* avoid stale pointer */ 447 cpuhw->bhrb_context = NULL; 448 } 449 } 450 451 /* Called from ctxsw to prevent one process's branch entries to 452 * mingle with the other process's entries during context switch. 453 */ 454 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 455 { 456 if (!ppmu->bhrb_nr) 457 return; 458 459 if (sched_in) 460 power_pmu_bhrb_reset(); 461 } 462 /* Calculate the to address for a branch */ 463 static __u64 power_pmu_bhrb_to(u64 addr) 464 { 465 unsigned int instr; 466 __u64 target; 467 468 if (is_kernel_addr(addr)) { 469 if (copy_from_kernel_nofault(&instr, (void *)addr, 470 sizeof(instr))) 471 return 0; 472 473 return branch_target(&instr); 474 } 475 476 /* Userspace: need copy instruction here then translate it */ 477 if (copy_from_user_nofault(&instr, (unsigned int __user *)addr, 478 sizeof(instr))) 479 return 0; 480 481 target = branch_target(&instr); 482 if ((!target) || (instr & BRANCH_ABSOLUTE)) 483 return target; 484 485 /* Translate relative branch target from kernel to user address */ 486 return target - (unsigned long)&instr + addr; 487 } 488 489 /* Processing BHRB entries */ 490 static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) 491 { 492 u64 val; 493 u64 addr; 494 int r_index, u_index, pred; 495 496 r_index = 0; 497 u_index = 0; 498 while (r_index < ppmu->bhrb_nr) { 499 /* Assembly read function */ 500 val = read_bhrb(r_index++); 501 if (!val) 502 /* Terminal marker: End of valid BHRB entries */ 503 break; 504 else { 505 addr = val & BHRB_EA; 506 pred = val & BHRB_PREDICTION; 507 508 if (!addr) 509 /* invalid entry */ 510 continue; 511 512 /* 513 * BHRB rolling buffer could very much contain the kernel 514 * addresses at this point. Check the privileges before 515 * exporting it to userspace (avoid exposure of regions 516 * where we could have speculative execution) 517 * Incase of ISA v3.1, BHRB will capture only user-space 518 * addresses, hence include a check before filtering code 519 */ 520 if (!(ppmu->flags & PPMU_ARCH_31) && 521 is_kernel_addr(addr) && event->attr.exclude_kernel) 522 continue; 523 524 /* Branches are read most recent first (ie. mfbhrb 0 is 525 * the most recent branch). 526 * There are two types of valid entries: 527 * 1) a target entry which is the to address of a 528 * computed goto like a blr,bctr,btar. The next 529 * entry read from the bhrb will be branch 530 * corresponding to this target (ie. the actual 531 * blr/bctr/btar instruction). 532 * 2) a from address which is an actual branch. If a 533 * target entry proceeds this, then this is the 534 * matching branch for that target. If this is not 535 * following a target entry, then this is a branch 536 * where the target is given as an immediate field 537 * in the instruction (ie. an i or b form branch). 538 * In this case we need to read the instruction from 539 * memory to determine the target/to address. 540 */ 541 542 if (val & BHRB_TARGET) { 543 /* Target branches use two entries 544 * (ie. computed gotos/XL form) 545 */ 546 cpuhw->bhrb_entries[u_index].to = addr; 547 cpuhw->bhrb_entries[u_index].mispred = pred; 548 cpuhw->bhrb_entries[u_index].predicted = ~pred; 549 550 /* Get from address in next entry */ 551 val = read_bhrb(r_index++); 552 addr = val & BHRB_EA; 553 if (val & BHRB_TARGET) { 554 /* Shouldn't have two targets in a 555 row.. Reset index and try again */ 556 r_index--; 557 addr = 0; 558 } 559 cpuhw->bhrb_entries[u_index].from = addr; 560 } else { 561 /* Branches to immediate field 562 (ie I or B form) */ 563 cpuhw->bhrb_entries[u_index].from = addr; 564 cpuhw->bhrb_entries[u_index].to = 565 power_pmu_bhrb_to(addr); 566 cpuhw->bhrb_entries[u_index].mispred = pred; 567 cpuhw->bhrb_entries[u_index].predicted = ~pred; 568 } 569 u_index++; 570 571 } 572 } 573 cpuhw->bhrb_stack.nr = u_index; 574 cpuhw->bhrb_stack.hw_idx = -1ULL; 575 return; 576 } 577 578 static bool is_ebb_event(struct perf_event *event) 579 { 580 /* 581 * This could be a per-PMU callback, but we'd rather avoid the cost. We 582 * check that the PMU supports EBB, meaning those that don't can still 583 * use bit 63 of the event code for something else if they wish. 584 */ 585 return (ppmu->flags & PPMU_ARCH_207S) && 586 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 587 } 588 589 static int ebb_event_check(struct perf_event *event) 590 { 591 struct perf_event *leader = event->group_leader; 592 593 /* Event and group leader must agree on EBB */ 594 if (is_ebb_event(leader) != is_ebb_event(event)) 595 return -EINVAL; 596 597 if (is_ebb_event(event)) { 598 if (!(event->attach_state & PERF_ATTACH_TASK)) 599 return -EINVAL; 600 601 if (!leader->attr.pinned || !leader->attr.exclusive) 602 return -EINVAL; 603 604 if (event->attr.freq || 605 event->attr.inherit || 606 event->attr.sample_type || 607 event->attr.sample_period || 608 event->attr.enable_on_exec) 609 return -EINVAL; 610 } 611 612 return 0; 613 } 614 615 static void ebb_event_add(struct perf_event *event) 616 { 617 if (!is_ebb_event(event) || current->thread.used_ebb) 618 return; 619 620 /* 621 * IFF this is the first time we've added an EBB event, set 622 * PMXE in the user MMCR0 so we can detect when it's cleared by 623 * userspace. We need this so that we can context switch while 624 * userspace is in the EBB handler (where PMXE is 0). 625 */ 626 current->thread.used_ebb = 1; 627 current->thread.mmcr0 |= MMCR0_PMXE; 628 } 629 630 static void ebb_switch_out(unsigned long mmcr0) 631 { 632 if (!(mmcr0 & MMCR0_EBE)) 633 return; 634 635 current->thread.siar = mfspr(SPRN_SIAR); 636 current->thread.sier = mfspr(SPRN_SIER); 637 current->thread.sdar = mfspr(SPRN_SDAR); 638 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 639 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 640 if (ppmu->flags & PPMU_ARCH_31) { 641 current->thread.mmcr3 = mfspr(SPRN_MMCR3); 642 current->thread.sier2 = mfspr(SPRN_SIER2); 643 current->thread.sier3 = mfspr(SPRN_SIER3); 644 } 645 } 646 647 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 648 { 649 unsigned long mmcr0 = cpuhw->mmcr.mmcr0; 650 651 if (!ebb) 652 goto out; 653 654 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 655 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 656 657 /* 658 * Add any bits from the user MMCR0, FC or PMAO. This is compatible 659 * with pmao_restore_workaround() because we may add PMAO but we never 660 * clear it here. 661 */ 662 mmcr0 |= current->thread.mmcr0; 663 664 /* 665 * Be careful not to set PMXE if userspace had it cleared. This is also 666 * compatible with pmao_restore_workaround() because it has already 667 * cleared PMXE and we leave PMAO alone. 668 */ 669 if (!(current->thread.mmcr0 & MMCR0_PMXE)) 670 mmcr0 &= ~MMCR0_PMXE; 671 672 mtspr(SPRN_SIAR, current->thread.siar); 673 mtspr(SPRN_SIER, current->thread.sier); 674 mtspr(SPRN_SDAR, current->thread.sdar); 675 676 /* 677 * Merge the kernel & user values of MMCR2. The semantics we implement 678 * are that the user MMCR2 can set bits, ie. cause counters to freeze, 679 * but not clear bits. If a task wants to be able to clear bits, ie. 680 * unfreeze counters, it should not set exclude_xxx in its events and 681 * instead manage the MMCR2 entirely by itself. 682 */ 683 mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2); 684 685 if (ppmu->flags & PPMU_ARCH_31) { 686 mtspr(SPRN_MMCR3, current->thread.mmcr3); 687 mtspr(SPRN_SIER2, current->thread.sier2); 688 mtspr(SPRN_SIER3, current->thread.sier3); 689 } 690 out: 691 return mmcr0; 692 } 693 694 static void pmao_restore_workaround(bool ebb) 695 { 696 unsigned pmcs[6]; 697 698 if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 699 return; 700 701 /* 702 * On POWER8E there is a hardware defect which affects the PMU context 703 * switch logic, ie. power_pmu_disable/enable(). 704 * 705 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 706 * by the hardware. Sometime later the actual PMU exception is 707 * delivered. 708 * 709 * If we context switch, or simply disable/enable, the PMU prior to the 710 * exception arriving, the exception will be lost when we clear PMAO. 711 * 712 * When we reenable the PMU, we will write the saved MMCR0 with PMAO 713 * set, and this _should_ generate an exception. However because of the 714 * defect no exception is generated when we write PMAO, and we get 715 * stuck with no counters counting but no exception delivered. 716 * 717 * The workaround is to detect this case and tweak the hardware to 718 * create another pending PMU exception. 719 * 720 * We do that by setting up PMC6 (cycles) for an imminent overflow and 721 * enabling the PMU. That causes a new exception to be generated in the 722 * chip, but we don't take it yet because we have interrupts hard 723 * disabled. We then write back the PMU state as we want it to be seen 724 * by the exception handler. When we reenable interrupts the exception 725 * handler will be called and see the correct state. 726 * 727 * The logic is the same for EBB, except that the exception is gated by 728 * us having interrupts hard disabled as well as the fact that we are 729 * not in userspace. The exception is finally delivered when we return 730 * to userspace. 731 */ 732 733 /* Only if PMAO is set and PMAO_SYNC is clear */ 734 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 735 return; 736 737 /* If we're doing EBB, only if BESCR[GE] is set */ 738 if (ebb && !(current->thread.bescr & BESCR_GE)) 739 return; 740 741 /* 742 * We are already soft-disabled in power_pmu_enable(). We need to hard 743 * disable to actually prevent the PMU exception from firing. 744 */ 745 hard_irq_disable(); 746 747 /* 748 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 749 * Using read/write_pmc() in a for loop adds 12 function calls and 750 * almost doubles our code size. 751 */ 752 pmcs[0] = mfspr(SPRN_PMC1); 753 pmcs[1] = mfspr(SPRN_PMC2); 754 pmcs[2] = mfspr(SPRN_PMC3); 755 pmcs[3] = mfspr(SPRN_PMC4); 756 pmcs[4] = mfspr(SPRN_PMC5); 757 pmcs[5] = mfspr(SPRN_PMC6); 758 759 /* Ensure all freeze bits are unset */ 760 mtspr(SPRN_MMCR2, 0); 761 762 /* Set up PMC6 to overflow in one cycle */ 763 mtspr(SPRN_PMC6, 0x7FFFFFFE); 764 765 /* Enable exceptions and unfreeze PMC6 */ 766 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 767 768 /* Now we need to refreeze and restore the PMCs */ 769 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 770 771 mtspr(SPRN_PMC1, pmcs[0]); 772 mtspr(SPRN_PMC2, pmcs[1]); 773 mtspr(SPRN_PMC3, pmcs[2]); 774 mtspr(SPRN_PMC4, pmcs[3]); 775 mtspr(SPRN_PMC5, pmcs[4]); 776 mtspr(SPRN_PMC6, pmcs[5]); 777 } 778 779 /* 780 * If the perf subsystem wants performance monitor interrupts as soon as 781 * possible (e.g., to sample the instruction address and stack chain), 782 * this should return true. The IRQ masking code can then enable MSR[EE] 783 * in some places (e.g., interrupt handlers) that allows PMI interrupts 784 * through to improve accuracy of profiles, at the cost of some performance. 785 * 786 * The PMU counters can be enabled by other means (e.g., sysfs raw SPR 787 * access), but in that case there is no need for prompt PMI handling. 788 * 789 * This currently returns true if any perf counter is being used. It 790 * could possibly return false if only events are being counted rather than 791 * samples being taken, but for now this is good enough. 792 */ 793 bool power_pmu_wants_prompt_pmi(void) 794 { 795 struct cpu_hw_events *cpuhw; 796 797 /* 798 * This could simply test local_paca->pmcregs_in_use if that were not 799 * under ifdef KVM. 800 */ 801 if (!ppmu) 802 return false; 803 804 cpuhw = this_cpu_ptr(&cpu_hw_events); 805 return cpuhw->n_events; 806 } 807 #endif /* CONFIG_PPC64 */ 808 809 static void perf_event_interrupt(struct pt_regs *regs); 810 811 /* 812 * Read one performance monitor counter (PMC). 813 */ 814 static unsigned long read_pmc(int idx) 815 { 816 unsigned long val; 817 818 switch (idx) { 819 case 1: 820 val = mfspr(SPRN_PMC1); 821 break; 822 case 2: 823 val = mfspr(SPRN_PMC2); 824 break; 825 case 3: 826 val = mfspr(SPRN_PMC3); 827 break; 828 case 4: 829 val = mfspr(SPRN_PMC4); 830 break; 831 case 5: 832 val = mfspr(SPRN_PMC5); 833 break; 834 case 6: 835 val = mfspr(SPRN_PMC6); 836 break; 837 #ifdef CONFIG_PPC64 838 case 7: 839 val = mfspr(SPRN_PMC7); 840 break; 841 case 8: 842 val = mfspr(SPRN_PMC8); 843 break; 844 #endif /* CONFIG_PPC64 */ 845 default: 846 printk(KERN_ERR "oops trying to read PMC%d\n", idx); 847 val = 0; 848 } 849 return val; 850 } 851 852 /* 853 * Write one PMC. 854 */ 855 static void write_pmc(int idx, unsigned long val) 856 { 857 switch (idx) { 858 case 1: 859 mtspr(SPRN_PMC1, val); 860 break; 861 case 2: 862 mtspr(SPRN_PMC2, val); 863 break; 864 case 3: 865 mtspr(SPRN_PMC3, val); 866 break; 867 case 4: 868 mtspr(SPRN_PMC4, val); 869 break; 870 case 5: 871 mtspr(SPRN_PMC5, val); 872 break; 873 case 6: 874 mtspr(SPRN_PMC6, val); 875 break; 876 #ifdef CONFIG_PPC64 877 case 7: 878 mtspr(SPRN_PMC7, val); 879 break; 880 case 8: 881 mtspr(SPRN_PMC8, val); 882 break; 883 #endif /* CONFIG_PPC64 */ 884 default: 885 printk(KERN_ERR "oops trying to write PMC%d\n", idx); 886 } 887 } 888 889 static int any_pmc_overflown(struct cpu_hw_events *cpuhw) 890 { 891 int i, idx; 892 893 for (i = 0; i < cpuhw->n_events; i++) { 894 idx = cpuhw->event[i]->hw.idx; 895 if ((idx) && ((int)read_pmc(idx) < 0)) 896 return idx; 897 } 898 899 return 0; 900 } 901 902 /* Called from sysrq_handle_showregs() */ 903 void perf_event_print_debug(void) 904 { 905 unsigned long sdar, sier, flags; 906 u32 pmcs[MAX_HWEVENTS]; 907 int i; 908 909 if (!ppmu) { 910 pr_info("Performance monitor hardware not registered.\n"); 911 return; 912 } 913 914 if (!ppmu->n_counter) 915 return; 916 917 local_irq_save(flags); 918 919 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 920 smp_processor_id(), ppmu->name, ppmu->n_counter); 921 922 for (i = 0; i < ppmu->n_counter; i++) 923 pmcs[i] = read_pmc(i + 1); 924 925 for (; i < MAX_HWEVENTS; i++) 926 pmcs[i] = 0xdeadbeef; 927 928 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 929 pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 930 931 if (ppmu->n_counter > 4) 932 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 933 pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 934 935 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 936 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 937 938 sdar = sier = 0; 939 #ifdef CONFIG_PPC64 940 sdar = mfspr(SPRN_SDAR); 941 942 if (ppmu->flags & PPMU_HAS_SIER) 943 sier = mfspr(SPRN_SIER); 944 945 if (ppmu->flags & PPMU_ARCH_207S) { 946 pr_info("MMCR2: %016lx EBBHR: %016lx\n", 947 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 948 pr_info("EBBRR: %016lx BESCR: %016lx\n", 949 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 950 } 951 952 if (ppmu->flags & PPMU_ARCH_31) { 953 pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n", 954 mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3)); 955 } 956 #endif 957 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 958 mfspr(SPRN_SIAR), sdar, sier); 959 960 local_irq_restore(flags); 961 } 962 963 /* 964 * Check if a set of events can all go on the PMU at once. 965 * If they can't, this will look at alternative codes for the events 966 * and see if any combination of alternative codes is feasible. 967 * The feasible set is returned in event_id[]. 968 */ 969 static int power_check_constraints(struct cpu_hw_events *cpuhw, 970 u64 event_id[], unsigned int cflags[], 971 int n_ev, struct perf_event **event) 972 { 973 unsigned long mask, value, nv; 974 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 975 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 976 int i, j; 977 unsigned long addf = ppmu->add_fields; 978 unsigned long tadd = ppmu->test_adder; 979 unsigned long grp_mask = ppmu->group_constraint_mask; 980 unsigned long grp_val = ppmu->group_constraint_val; 981 982 if (n_ev > ppmu->n_counter) 983 return -1; 984 985 /* First see if the events will go on as-is */ 986 for (i = 0; i < n_ev; ++i) { 987 if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 988 && !ppmu->limited_pmc_event(event_id[i])) { 989 ppmu->get_alternatives(event_id[i], cflags[i], 990 cpuhw->alternatives[i]); 991 event_id[i] = cpuhw->alternatives[i][0]; 992 } 993 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 994 &cpuhw->avalues[i][0], event[i]->attr.config1)) 995 return -1; 996 } 997 value = mask = 0; 998 for (i = 0; i < n_ev; ++i) { 999 nv = (value | cpuhw->avalues[i][0]) + 1000 (value & cpuhw->avalues[i][0] & addf); 1001 1002 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0) 1003 break; 1004 1005 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0]) 1006 & (~grp_mask)) != 0) 1007 break; 1008 1009 value = nv; 1010 mask |= cpuhw->amasks[i][0]; 1011 } 1012 if (i == n_ev) { 1013 if ((value & mask & grp_mask) != (mask & grp_val)) 1014 return -1; 1015 else 1016 return 0; /* all OK */ 1017 } 1018 1019 /* doesn't work, gather alternatives... */ 1020 if (!ppmu->get_alternatives) 1021 return -1; 1022 for (i = 0; i < n_ev; ++i) { 1023 choice[i] = 0; 1024 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 1025 cpuhw->alternatives[i]); 1026 for (j = 1; j < n_alt[i]; ++j) 1027 ppmu->get_constraint(cpuhw->alternatives[i][j], 1028 &cpuhw->amasks[i][j], 1029 &cpuhw->avalues[i][j], 1030 event[i]->attr.config1); 1031 } 1032 1033 /* enumerate all possibilities and see if any will work */ 1034 i = 0; 1035 j = -1; 1036 value = mask = nv = 0; 1037 while (i < n_ev) { 1038 if (j >= 0) { 1039 /* we're backtracking, restore context */ 1040 value = svalues[i]; 1041 mask = smasks[i]; 1042 j = choice[i]; 1043 } 1044 /* 1045 * See if any alternative k for event_id i, 1046 * where k > j, will satisfy the constraints. 1047 */ 1048 while (++j < n_alt[i]) { 1049 nv = (value | cpuhw->avalues[i][j]) + 1050 (value & cpuhw->avalues[i][j] & addf); 1051 if ((((nv + tadd) ^ value) & mask) == 0 && 1052 (((nv + tadd) ^ cpuhw->avalues[i][j]) 1053 & cpuhw->amasks[i][j]) == 0) 1054 break; 1055 } 1056 if (j >= n_alt[i]) { 1057 /* 1058 * No feasible alternative, backtrack 1059 * to event_id i-1 and continue enumerating its 1060 * alternatives from where we got up to. 1061 */ 1062 if (--i < 0) 1063 return -1; 1064 } else { 1065 /* 1066 * Found a feasible alternative for event_id i, 1067 * remember where we got up to with this event_id, 1068 * go on to the next event_id, and start with 1069 * the first alternative for it. 1070 */ 1071 choice[i] = j; 1072 svalues[i] = value; 1073 smasks[i] = mask; 1074 value = nv; 1075 mask |= cpuhw->amasks[i][j]; 1076 ++i; 1077 j = -1; 1078 } 1079 } 1080 1081 /* OK, we have a feasible combination, tell the caller the solution */ 1082 for (i = 0; i < n_ev; ++i) 1083 event_id[i] = cpuhw->alternatives[i][choice[i]]; 1084 return 0; 1085 } 1086 1087 /* 1088 * Check if newly-added events have consistent settings for 1089 * exclude_{user,kernel,hv} with each other and any previously 1090 * added events. 1091 */ 1092 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 1093 int n_prev, int n_new) 1094 { 1095 int eu = 0, ek = 0, eh = 0; 1096 int i, n, first; 1097 struct perf_event *event; 1098 1099 /* 1100 * If the PMU we're on supports per event exclude settings then we 1101 * don't need to do any of this logic. NB. This assumes no PMU has both 1102 * per event exclude and limited PMCs. 1103 */ 1104 if (ppmu->flags & PPMU_ARCH_207S) 1105 return 0; 1106 1107 n = n_prev + n_new; 1108 if (n <= 1) 1109 return 0; 1110 1111 first = 1; 1112 for (i = 0; i < n; ++i) { 1113 if (cflags[i] & PPMU_LIMITED_PMC_OK) { 1114 cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 1115 continue; 1116 } 1117 event = ctrs[i]; 1118 if (first) { 1119 eu = event->attr.exclude_user; 1120 ek = event->attr.exclude_kernel; 1121 eh = event->attr.exclude_hv; 1122 first = 0; 1123 } else if (event->attr.exclude_user != eu || 1124 event->attr.exclude_kernel != ek || 1125 event->attr.exclude_hv != eh) { 1126 return -EAGAIN; 1127 } 1128 } 1129 1130 if (eu || ek || eh) 1131 for (i = 0; i < n; ++i) 1132 if (cflags[i] & PPMU_LIMITED_PMC_OK) 1133 cflags[i] |= PPMU_LIMITED_PMC_REQD; 1134 1135 return 0; 1136 } 1137 1138 static u64 check_and_compute_delta(u64 prev, u64 val) 1139 { 1140 u64 delta = (val - prev) & 0xfffffffful; 1141 1142 /* 1143 * POWER7 can roll back counter values, if the new value is smaller 1144 * than the previous value it will cause the delta and the counter to 1145 * have bogus values unless we rolled a counter over. If a coutner is 1146 * rolled back, it will be smaller, but within 256, which is the maximum 1147 * number of events to rollback at once. If we detect a rollback 1148 * return 0. This can lead to a small lack of precision in the 1149 * counters. 1150 */ 1151 if (prev > val && (prev - val) < 256) 1152 delta = 0; 1153 1154 return delta; 1155 } 1156 1157 static void power_pmu_read(struct perf_event *event) 1158 { 1159 s64 val, delta, prev; 1160 1161 if (event->hw.state & PERF_HES_STOPPED) 1162 return; 1163 1164 if (!event->hw.idx) 1165 return; 1166 1167 if (is_ebb_event(event)) { 1168 val = read_pmc(event->hw.idx); 1169 local64_set(&event->hw.prev_count, val); 1170 return; 1171 } 1172 1173 /* 1174 * Performance monitor interrupts come even when interrupts 1175 * are soft-disabled, as long as interrupts are hard-enabled. 1176 * Therefore we treat them like NMIs. 1177 */ 1178 do { 1179 prev = local64_read(&event->hw.prev_count); 1180 barrier(); 1181 val = read_pmc(event->hw.idx); 1182 delta = check_and_compute_delta(prev, val); 1183 if (!delta) 1184 return; 1185 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1186 1187 local64_add(delta, &event->count); 1188 1189 /* 1190 * A number of places program the PMC with (0x80000000 - period_left). 1191 * We never want period_left to be less than 1 because we will program 1192 * the PMC with a value >= 0x800000000 and an edge detected PMC will 1193 * roll around to 0 before taking an exception. We have seen this 1194 * on POWER8. 1195 * 1196 * To fix this, clamp the minimum value of period_left to 1. 1197 */ 1198 do { 1199 prev = local64_read(&event->hw.period_left); 1200 val = prev - delta; 1201 if (val < 1) 1202 val = 1; 1203 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1204 } 1205 1206 /* 1207 * On some machines, PMC5 and PMC6 can't be written, don't respect 1208 * the freeze conditions, and don't generate interrupts. This tells 1209 * us if `event' is using such a PMC. 1210 */ 1211 static int is_limited_pmc(int pmcnum) 1212 { 1213 return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1214 && (pmcnum == 5 || pmcnum == 6); 1215 } 1216 1217 static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1218 unsigned long pmc5, unsigned long pmc6) 1219 { 1220 struct perf_event *event; 1221 u64 val, prev, delta; 1222 int i; 1223 1224 for (i = 0; i < cpuhw->n_limited; ++i) { 1225 event = cpuhw->limited_counter[i]; 1226 if (!event->hw.idx) 1227 continue; 1228 val = (event->hw.idx == 5) ? pmc5 : pmc6; 1229 prev = local64_read(&event->hw.prev_count); 1230 event->hw.idx = 0; 1231 delta = check_and_compute_delta(prev, val); 1232 if (delta) 1233 local64_add(delta, &event->count); 1234 } 1235 } 1236 1237 static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1238 unsigned long pmc5, unsigned long pmc6) 1239 { 1240 struct perf_event *event; 1241 u64 val, prev; 1242 int i; 1243 1244 for (i = 0; i < cpuhw->n_limited; ++i) { 1245 event = cpuhw->limited_counter[i]; 1246 event->hw.idx = cpuhw->limited_hwidx[i]; 1247 val = (event->hw.idx == 5) ? pmc5 : pmc6; 1248 prev = local64_read(&event->hw.prev_count); 1249 if (check_and_compute_delta(prev, val)) 1250 local64_set(&event->hw.prev_count, val); 1251 perf_event_update_userpage(event); 1252 } 1253 } 1254 1255 /* 1256 * Since limited events don't respect the freeze conditions, we 1257 * have to read them immediately after freezing or unfreezing the 1258 * other events. We try to keep the values from the limited 1259 * events as consistent as possible by keeping the delay (in 1260 * cycles and instructions) between freezing/unfreezing and reading 1261 * the limited events as small and consistent as possible. 1262 * Therefore, if any limited events are in use, we read them 1263 * both, and always in the same order, to minimize variability, 1264 * and do it inside the same asm that writes MMCR0. 1265 */ 1266 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1267 { 1268 unsigned long pmc5, pmc6; 1269 1270 if (!cpuhw->n_limited) { 1271 mtspr(SPRN_MMCR0, mmcr0); 1272 return; 1273 } 1274 1275 /* 1276 * Write MMCR0, then read PMC5 and PMC6 immediately. 1277 * To ensure we don't get a performance monitor interrupt 1278 * between writing MMCR0 and freezing/thawing the limited 1279 * events, we first write MMCR0 with the event overflow 1280 * interrupt enable bits turned off. 1281 */ 1282 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1283 : "=&r" (pmc5), "=&r" (pmc6) 1284 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1285 "i" (SPRN_MMCR0), 1286 "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1287 1288 if (mmcr0 & MMCR0_FC) 1289 freeze_limited_counters(cpuhw, pmc5, pmc6); 1290 else 1291 thaw_limited_counters(cpuhw, pmc5, pmc6); 1292 1293 /* 1294 * Write the full MMCR0 including the event overflow interrupt 1295 * enable bits, if necessary. 1296 */ 1297 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1298 mtspr(SPRN_MMCR0, mmcr0); 1299 } 1300 1301 /* 1302 * Disable all events to prevent PMU interrupts and to allow 1303 * events to be added or removed. 1304 */ 1305 static void power_pmu_disable(struct pmu *pmu) 1306 { 1307 struct cpu_hw_events *cpuhw; 1308 unsigned long flags, mmcr0, val, mmcra; 1309 1310 if (!ppmu) 1311 return; 1312 local_irq_save(flags); 1313 cpuhw = this_cpu_ptr(&cpu_hw_events); 1314 1315 if (!cpuhw->disabled) { 1316 /* 1317 * Check if we ever enabled the PMU on this cpu. 1318 */ 1319 if (!cpuhw->pmcs_enabled) { 1320 ppc_enable_pmcs(); 1321 cpuhw->pmcs_enabled = 1; 1322 } 1323 1324 /* 1325 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1326 * Also clear PMXE to disable PMI's getting triggered in some 1327 * corner cases during PMU disable. 1328 */ 1329 val = mmcr0 = mfspr(SPRN_MMCR0); 1330 val |= MMCR0_FC; 1331 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 1332 MMCR0_PMXE | MMCR0_FC56); 1333 /* Set mmcr0 PMCCEXT for p10 */ 1334 if (ppmu->flags & PPMU_ARCH_31) 1335 val |= MMCR0_PMCCEXT; 1336 1337 /* 1338 * The barrier is to make sure the mtspr has been 1339 * executed and the PMU has frozen the events etc. 1340 * before we return. 1341 */ 1342 write_mmcr0(cpuhw, val); 1343 mb(); 1344 isync(); 1345 1346 /* 1347 * Some corner cases could clear the PMU counter overflow 1348 * while a masked PMI is pending. One such case is when 1349 * a PMI happens during interrupt replay and perf counter 1350 * values are cleared by PMU callbacks before replay. 1351 * 1352 * If any PMC corresponding to the active PMU events are 1353 * overflown, disable the interrupt by clearing the paca 1354 * bit for PMI since we are disabling the PMU now. 1355 * Otherwise provide a warning if there is PMI pending, but 1356 * no counter is found overflown. 1357 */ 1358 if (any_pmc_overflown(cpuhw)) 1359 clear_pmi_irq_pending(); 1360 else 1361 WARN_ON(pmi_irq_pending()); 1362 1363 val = mmcra = cpuhw->mmcr.mmcra; 1364 1365 /* 1366 * Disable instruction sampling if it was enabled 1367 */ 1368 if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) 1369 val &= ~MMCRA_SAMPLE_ENABLE; 1370 1371 /* Disable BHRB via mmcra (BHRBRD) for p10 */ 1372 if (ppmu->flags & PPMU_ARCH_31) 1373 val |= MMCRA_BHRB_DISABLE; 1374 1375 /* 1376 * Write SPRN_MMCRA if mmcra has either disabled 1377 * instruction sampling or BHRB. 1378 */ 1379 if (val != mmcra) { 1380 mtspr(SPRN_MMCRA, mmcra); 1381 mb(); 1382 isync(); 1383 } 1384 1385 cpuhw->disabled = 1; 1386 cpuhw->n_added = 0; 1387 1388 ebb_switch_out(mmcr0); 1389 1390 #ifdef CONFIG_PPC64 1391 /* 1392 * These are readable by userspace, may contain kernel 1393 * addresses and are not switched by context switch, so clear 1394 * them now to avoid leaking anything to userspace in general 1395 * including to another process. 1396 */ 1397 if (ppmu->flags & PPMU_ARCH_207S) { 1398 mtspr(SPRN_SDAR, 0); 1399 mtspr(SPRN_SIAR, 0); 1400 } 1401 #endif 1402 } 1403 1404 local_irq_restore(flags); 1405 } 1406 1407 /* 1408 * Re-enable all events if disable == 0. 1409 * If we were previously disabled and events were added, then 1410 * put the new config on the PMU. 1411 */ 1412 static void power_pmu_enable(struct pmu *pmu) 1413 { 1414 struct perf_event *event; 1415 struct cpu_hw_events *cpuhw; 1416 unsigned long flags; 1417 long i; 1418 unsigned long val, mmcr0; 1419 s64 left; 1420 unsigned int hwc_index[MAX_HWEVENTS]; 1421 int n_lim; 1422 int idx; 1423 bool ebb; 1424 1425 if (!ppmu) 1426 return; 1427 local_irq_save(flags); 1428 1429 cpuhw = this_cpu_ptr(&cpu_hw_events); 1430 if (!cpuhw->disabled) 1431 goto out; 1432 1433 if (cpuhw->n_events == 0) { 1434 ppc_set_pmu_inuse(0); 1435 goto out; 1436 } 1437 1438 cpuhw->disabled = 0; 1439 1440 /* 1441 * EBB requires an exclusive group and all events must have the EBB 1442 * flag set, or not set, so we can just check a single event. Also we 1443 * know we have at least one event. 1444 */ 1445 ebb = is_ebb_event(cpuhw->event[0]); 1446 1447 /* 1448 * If we didn't change anything, or only removed events, 1449 * no need to recalculate MMCR* settings and reset the PMCs. 1450 * Just reenable the PMU with the current MMCR* settings 1451 * (possibly updated for removal of events). 1452 */ 1453 if (!cpuhw->n_added) { 1454 /* 1455 * If there is any active event with an overflown PMC 1456 * value, set back PACA_IRQ_PMI which would have been 1457 * cleared in power_pmu_disable(). 1458 */ 1459 hard_irq_disable(); 1460 if (any_pmc_overflown(cpuhw)) 1461 set_pmi_irq_pending(); 1462 1463 mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 1464 mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 1465 if (ppmu->flags & PPMU_ARCH_31) 1466 mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1467 goto out_enable; 1468 } 1469 1470 /* 1471 * Clear all MMCR settings and recompute them for the new set of events. 1472 */ 1473 memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 1474 1475 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 1476 &cpuhw->mmcr, cpuhw->event, ppmu->flags)) { 1477 /* shouldn't ever get here */ 1478 printk(KERN_ERR "oops compute_mmcr failed\n"); 1479 goto out; 1480 } 1481 1482 if (!(ppmu->flags & PPMU_ARCH_207S)) { 1483 /* 1484 * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 1485 * bits for the first event. We have already checked that all 1486 * events have the same value for these bits as the first event. 1487 */ 1488 event = cpuhw->event[0]; 1489 if (event->attr.exclude_user) 1490 cpuhw->mmcr.mmcr0 |= MMCR0_FCP; 1491 if (event->attr.exclude_kernel) 1492 cpuhw->mmcr.mmcr0 |= freeze_events_kernel; 1493 if (event->attr.exclude_hv) 1494 cpuhw->mmcr.mmcr0 |= MMCR0_FCHV; 1495 } 1496 1497 /* 1498 * Write the new configuration to MMCR* with the freeze 1499 * bit set and set the hardware events to their initial values. 1500 * Then unfreeze the events. 1501 */ 1502 ppc_set_pmu_inuse(1); 1503 mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 1504 mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 1505 mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1506 | MMCR0_FC); 1507 if (ppmu->flags & PPMU_ARCH_207S) 1508 mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2); 1509 1510 if (ppmu->flags & PPMU_ARCH_31) 1511 mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1512 1513 /* 1514 * Read off any pre-existing events that need to move 1515 * to another PMC. 1516 */ 1517 for (i = 0; i < cpuhw->n_events; ++i) { 1518 event = cpuhw->event[i]; 1519 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1520 power_pmu_read(event); 1521 write_pmc(event->hw.idx, 0); 1522 event->hw.idx = 0; 1523 } 1524 } 1525 1526 /* 1527 * Initialize the PMCs for all the new and moved events. 1528 */ 1529 cpuhw->n_limited = n_lim = 0; 1530 for (i = 0; i < cpuhw->n_events; ++i) { 1531 event = cpuhw->event[i]; 1532 if (event->hw.idx) 1533 continue; 1534 idx = hwc_index[i] + 1; 1535 if (is_limited_pmc(idx)) { 1536 cpuhw->limited_counter[n_lim] = event; 1537 cpuhw->limited_hwidx[n_lim] = idx; 1538 ++n_lim; 1539 continue; 1540 } 1541 1542 if (ebb) 1543 val = local64_read(&event->hw.prev_count); 1544 else { 1545 val = 0; 1546 if (event->hw.sample_period) { 1547 left = local64_read(&event->hw.period_left); 1548 if (left < 0x80000000L) 1549 val = 0x80000000L - left; 1550 } 1551 local64_set(&event->hw.prev_count, val); 1552 } 1553 1554 event->hw.idx = idx; 1555 if (event->hw.state & PERF_HES_STOPPED) 1556 val = 0; 1557 write_pmc(idx, val); 1558 1559 perf_event_update_userpage(event); 1560 } 1561 cpuhw->n_limited = n_lim; 1562 cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE; 1563 1564 out_enable: 1565 pmao_restore_workaround(ebb); 1566 1567 mmcr0 = ebb_switch_in(ebb, cpuhw); 1568 1569 mb(); 1570 if (cpuhw->bhrb_users) 1571 ppmu->config_bhrb(cpuhw->bhrb_filter); 1572 1573 write_mmcr0(cpuhw, mmcr0); 1574 1575 /* 1576 * Enable instruction sampling if necessary 1577 */ 1578 if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) { 1579 mb(); 1580 mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra); 1581 } 1582 1583 out: 1584 1585 local_irq_restore(flags); 1586 } 1587 1588 static int collect_events(struct perf_event *group, int max_count, 1589 struct perf_event *ctrs[], u64 *events, 1590 unsigned int *flags) 1591 { 1592 int n = 0; 1593 struct perf_event *event; 1594 1595 if (group->pmu->task_ctx_nr == perf_hw_context) { 1596 if (n >= max_count) 1597 return -1; 1598 ctrs[n] = group; 1599 flags[n] = group->hw.event_base; 1600 events[n++] = group->hw.config; 1601 } 1602 for_each_sibling_event(event, group) { 1603 if (event->pmu->task_ctx_nr == perf_hw_context && 1604 event->state != PERF_EVENT_STATE_OFF) { 1605 if (n >= max_count) 1606 return -1; 1607 ctrs[n] = event; 1608 flags[n] = event->hw.event_base; 1609 events[n++] = event->hw.config; 1610 } 1611 } 1612 return n; 1613 } 1614 1615 /* 1616 * Add an event to the PMU. 1617 * If all events are not already frozen, then we disable and 1618 * re-enable the PMU in order to get hw_perf_enable to do the 1619 * actual work of reconfiguring the PMU. 1620 */ 1621 static int power_pmu_add(struct perf_event *event, int ef_flags) 1622 { 1623 struct cpu_hw_events *cpuhw; 1624 unsigned long flags; 1625 int n0; 1626 int ret = -EAGAIN; 1627 1628 local_irq_save(flags); 1629 perf_pmu_disable(event->pmu); 1630 1631 /* 1632 * Add the event to the list (if there is room) 1633 * and check whether the total set is still feasible. 1634 */ 1635 cpuhw = this_cpu_ptr(&cpu_hw_events); 1636 n0 = cpuhw->n_events; 1637 if (n0 >= ppmu->n_counter) 1638 goto out; 1639 cpuhw->event[n0] = event; 1640 cpuhw->events[n0] = event->hw.config; 1641 cpuhw->flags[n0] = event->hw.event_base; 1642 1643 /* 1644 * This event may have been disabled/stopped in record_and_restart() 1645 * because we exceeded the ->event_limit. If re-starting the event, 1646 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1647 * notification is re-enabled. 1648 */ 1649 if (!(ef_flags & PERF_EF_START)) 1650 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1651 else 1652 event->hw.state = 0; 1653 1654 /* 1655 * If group events scheduling transaction was started, 1656 * skip the schedulability test here, it will be performed 1657 * at commit time(->commit_txn) as a whole 1658 */ 1659 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1660 goto nocheck; 1661 1662 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1663 goto out; 1664 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1, cpuhw->event)) 1665 goto out; 1666 event->hw.config = cpuhw->events[n0]; 1667 1668 nocheck: 1669 ebb_event_add(event); 1670 1671 ++cpuhw->n_events; 1672 ++cpuhw->n_added; 1673 1674 ret = 0; 1675 out: 1676 if (has_branch_stack(event)) { 1677 u64 bhrb_filter = -1; 1678 1679 if (ppmu->bhrb_filter_map) 1680 bhrb_filter = ppmu->bhrb_filter_map( 1681 event->attr.branch_sample_type); 1682 1683 if (bhrb_filter != -1) { 1684 cpuhw->bhrb_filter = bhrb_filter; 1685 power_pmu_bhrb_enable(event); 1686 } 1687 } 1688 1689 perf_pmu_enable(event->pmu); 1690 local_irq_restore(flags); 1691 return ret; 1692 } 1693 1694 /* 1695 * Remove an event from the PMU. 1696 */ 1697 static void power_pmu_del(struct perf_event *event, int ef_flags) 1698 { 1699 struct cpu_hw_events *cpuhw; 1700 long i; 1701 unsigned long flags; 1702 1703 local_irq_save(flags); 1704 perf_pmu_disable(event->pmu); 1705 1706 power_pmu_read(event); 1707 1708 cpuhw = this_cpu_ptr(&cpu_hw_events); 1709 for (i = 0; i < cpuhw->n_events; ++i) { 1710 if (event == cpuhw->event[i]) { 1711 while (++i < cpuhw->n_events) { 1712 cpuhw->event[i-1] = cpuhw->event[i]; 1713 cpuhw->events[i-1] = cpuhw->events[i]; 1714 cpuhw->flags[i-1] = cpuhw->flags[i]; 1715 } 1716 --cpuhw->n_events; 1717 ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr); 1718 if (event->hw.idx) { 1719 write_pmc(event->hw.idx, 0); 1720 event->hw.idx = 0; 1721 } 1722 perf_event_update_userpage(event); 1723 break; 1724 } 1725 } 1726 for (i = 0; i < cpuhw->n_limited; ++i) 1727 if (event == cpuhw->limited_counter[i]) 1728 break; 1729 if (i < cpuhw->n_limited) { 1730 while (++i < cpuhw->n_limited) { 1731 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1732 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1733 } 1734 --cpuhw->n_limited; 1735 } 1736 if (cpuhw->n_events == 0) { 1737 /* disable exceptions if no events are running */ 1738 cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE); 1739 } 1740 1741 if (has_branch_stack(event)) 1742 power_pmu_bhrb_disable(event); 1743 1744 perf_pmu_enable(event->pmu); 1745 local_irq_restore(flags); 1746 } 1747 1748 /* 1749 * POWER-PMU does not support disabling individual counters, hence 1750 * program their cycle counter to their max value and ignore the interrupts. 1751 */ 1752 1753 static void power_pmu_start(struct perf_event *event, int ef_flags) 1754 { 1755 unsigned long flags; 1756 s64 left; 1757 unsigned long val; 1758 1759 if (!event->hw.idx || !event->hw.sample_period) 1760 return; 1761 1762 if (!(event->hw.state & PERF_HES_STOPPED)) 1763 return; 1764 1765 if (ef_flags & PERF_EF_RELOAD) 1766 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1767 1768 local_irq_save(flags); 1769 perf_pmu_disable(event->pmu); 1770 1771 event->hw.state = 0; 1772 left = local64_read(&event->hw.period_left); 1773 1774 val = 0; 1775 if (left < 0x80000000L) 1776 val = 0x80000000L - left; 1777 1778 write_pmc(event->hw.idx, val); 1779 1780 perf_event_update_userpage(event); 1781 perf_pmu_enable(event->pmu); 1782 local_irq_restore(flags); 1783 } 1784 1785 static void power_pmu_stop(struct perf_event *event, int ef_flags) 1786 { 1787 unsigned long flags; 1788 1789 if (!event->hw.idx || !event->hw.sample_period) 1790 return; 1791 1792 if (event->hw.state & PERF_HES_STOPPED) 1793 return; 1794 1795 local_irq_save(flags); 1796 perf_pmu_disable(event->pmu); 1797 1798 power_pmu_read(event); 1799 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1800 write_pmc(event->hw.idx, 0); 1801 1802 perf_event_update_userpage(event); 1803 perf_pmu_enable(event->pmu); 1804 local_irq_restore(flags); 1805 } 1806 1807 /* 1808 * Start group events scheduling transaction 1809 * Set the flag to make pmu::enable() not perform the 1810 * schedulability test, it will be performed at commit time 1811 * 1812 * We only support PERF_PMU_TXN_ADD transactions. Save the 1813 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1814 * transactions. 1815 */ 1816 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1817 { 1818 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1819 1820 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1821 1822 cpuhw->txn_flags = txn_flags; 1823 if (txn_flags & ~PERF_PMU_TXN_ADD) 1824 return; 1825 1826 perf_pmu_disable(pmu); 1827 cpuhw->n_txn_start = cpuhw->n_events; 1828 } 1829 1830 /* 1831 * Stop group events scheduling transaction 1832 * Clear the flag and pmu::enable() will perform the 1833 * schedulability test. 1834 */ 1835 static void power_pmu_cancel_txn(struct pmu *pmu) 1836 { 1837 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1838 unsigned int txn_flags; 1839 1840 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1841 1842 txn_flags = cpuhw->txn_flags; 1843 cpuhw->txn_flags = 0; 1844 if (txn_flags & ~PERF_PMU_TXN_ADD) 1845 return; 1846 1847 perf_pmu_enable(pmu); 1848 } 1849 1850 /* 1851 * Commit group events scheduling transaction 1852 * Perform the group schedulability test as a whole 1853 * Return 0 if success 1854 */ 1855 static int power_pmu_commit_txn(struct pmu *pmu) 1856 { 1857 struct cpu_hw_events *cpuhw; 1858 long i, n; 1859 1860 if (!ppmu) 1861 return -EAGAIN; 1862 1863 cpuhw = this_cpu_ptr(&cpu_hw_events); 1864 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1865 1866 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1867 cpuhw->txn_flags = 0; 1868 return 0; 1869 } 1870 1871 n = cpuhw->n_events; 1872 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1873 return -EAGAIN; 1874 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n, cpuhw->event); 1875 if (i < 0) 1876 return -EAGAIN; 1877 1878 for (i = cpuhw->n_txn_start; i < n; ++i) 1879 cpuhw->event[i]->hw.config = cpuhw->events[i]; 1880 1881 cpuhw->txn_flags = 0; 1882 perf_pmu_enable(pmu); 1883 return 0; 1884 } 1885 1886 /* 1887 * Return 1 if we might be able to put event on a limited PMC, 1888 * or 0 if not. 1889 * An event can only go on a limited PMC if it counts something 1890 * that a limited PMC can count, doesn't require interrupts, and 1891 * doesn't exclude any processor mode. 1892 */ 1893 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1894 unsigned int flags) 1895 { 1896 int n; 1897 u64 alt[MAX_EVENT_ALTERNATIVES]; 1898 1899 if (event->attr.exclude_user 1900 || event->attr.exclude_kernel 1901 || event->attr.exclude_hv 1902 || event->attr.sample_period) 1903 return 0; 1904 1905 if (ppmu->limited_pmc_event(ev)) 1906 return 1; 1907 1908 /* 1909 * The requested event_id isn't on a limited PMC already; 1910 * see if any alternative code goes on a limited PMC. 1911 */ 1912 if (!ppmu->get_alternatives) 1913 return 0; 1914 1915 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1916 n = ppmu->get_alternatives(ev, flags, alt); 1917 1918 return n > 0; 1919 } 1920 1921 /* 1922 * Find an alternative event_id that goes on a normal PMC, if possible, 1923 * and return the event_id code, or 0 if there is no such alternative. 1924 * (Note: event_id code 0 is "don't count" on all machines.) 1925 */ 1926 static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1927 { 1928 u64 alt[MAX_EVENT_ALTERNATIVES]; 1929 int n; 1930 1931 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1932 n = ppmu->get_alternatives(ev, flags, alt); 1933 if (!n) 1934 return 0; 1935 return alt[0]; 1936 } 1937 1938 /* Number of perf_events counting hardware events */ 1939 static atomic_t num_events; 1940 /* Used to avoid races in calling reserve/release_pmc_hardware */ 1941 static DEFINE_MUTEX(pmc_reserve_mutex); 1942 1943 /* 1944 * Release the PMU if this is the last perf_event. 1945 */ 1946 static void hw_perf_event_destroy(struct perf_event *event) 1947 { 1948 if (!atomic_add_unless(&num_events, -1, 1)) { 1949 mutex_lock(&pmc_reserve_mutex); 1950 if (atomic_dec_return(&num_events) == 0) 1951 release_pmc_hardware(); 1952 mutex_unlock(&pmc_reserve_mutex); 1953 } 1954 } 1955 1956 /* 1957 * Translate a generic cache event_id config to a raw event_id code. 1958 */ 1959 static int hw_perf_cache_event(u64 config, u64 *eventp) 1960 { 1961 unsigned long type, op, result; 1962 u64 ev; 1963 1964 if (!ppmu->cache_events) 1965 return -EINVAL; 1966 1967 /* unpack config */ 1968 type = config & 0xff; 1969 op = (config >> 8) & 0xff; 1970 result = (config >> 16) & 0xff; 1971 1972 if (type >= PERF_COUNT_HW_CACHE_MAX || 1973 op >= PERF_COUNT_HW_CACHE_OP_MAX || 1974 result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1975 return -EINVAL; 1976 1977 ev = (*ppmu->cache_events)[type][op][result]; 1978 if (ev == 0) 1979 return -EOPNOTSUPP; 1980 if (ev == -1) 1981 return -EINVAL; 1982 *eventp = ev; 1983 return 0; 1984 } 1985 1986 static bool is_event_blacklisted(u64 ev) 1987 { 1988 int i; 1989 1990 for (i=0; i < ppmu->n_blacklist_ev; i++) { 1991 if (ppmu->blacklist_ev[i] == ev) 1992 return true; 1993 } 1994 1995 return false; 1996 } 1997 1998 static int power_pmu_event_init(struct perf_event *event) 1999 { 2000 u64 ev; 2001 unsigned long flags, irq_flags; 2002 struct perf_event *ctrs[MAX_HWEVENTS]; 2003 u64 events[MAX_HWEVENTS]; 2004 unsigned int cflags[MAX_HWEVENTS]; 2005 int n; 2006 int err; 2007 struct cpu_hw_events *cpuhw; 2008 2009 if (!ppmu) 2010 return -ENOENT; 2011 2012 if (has_branch_stack(event)) { 2013 /* PMU has BHRB enabled */ 2014 if (!(ppmu->flags & PPMU_ARCH_207S)) 2015 return -EOPNOTSUPP; 2016 } 2017 2018 switch (event->attr.type) { 2019 case PERF_TYPE_HARDWARE: 2020 ev = event->attr.config; 2021 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 2022 return -EOPNOTSUPP; 2023 2024 if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 2025 return -EINVAL; 2026 ev = ppmu->generic_events[ev]; 2027 break; 2028 case PERF_TYPE_HW_CACHE: 2029 err = hw_perf_cache_event(event->attr.config, &ev); 2030 if (err) 2031 return err; 2032 2033 if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 2034 return -EINVAL; 2035 break; 2036 case PERF_TYPE_RAW: 2037 ev = event->attr.config; 2038 2039 if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 2040 return -EINVAL; 2041 break; 2042 default: 2043 return -ENOENT; 2044 } 2045 2046 /* 2047 * PMU config registers have fields that are 2048 * reserved and some specific values for bit fields are reserved. 2049 * For ex., MMCRA[61:62] is Randome Sampling Mode (SM) 2050 * and value of 0b11 to this field is reserved. 2051 * Check for invalid values in attr.config. 2052 */ 2053 if (ppmu->check_attr_config && 2054 ppmu->check_attr_config(event)) 2055 return -EINVAL; 2056 2057 event->hw.config_base = ev; 2058 event->hw.idx = 0; 2059 2060 /* 2061 * If we are not running on a hypervisor, force the 2062 * exclude_hv bit to 0 so that we don't care what 2063 * the user set it to. 2064 */ 2065 if (!firmware_has_feature(FW_FEATURE_LPAR)) 2066 event->attr.exclude_hv = 0; 2067 2068 /* 2069 * If this is a per-task event, then we can use 2070 * PM_RUN_* events interchangeably with their non RUN_* 2071 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 2072 * XXX we should check if the task is an idle task. 2073 */ 2074 flags = 0; 2075 if (event->attach_state & PERF_ATTACH_TASK) 2076 flags |= PPMU_ONLY_COUNT_RUN; 2077 2078 /* 2079 * If this machine has limited events, check whether this 2080 * event_id could go on a limited event. 2081 */ 2082 if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 2083 if (can_go_on_limited_pmc(event, ev, flags)) { 2084 flags |= PPMU_LIMITED_PMC_OK; 2085 } else if (ppmu->limited_pmc_event(ev)) { 2086 /* 2087 * The requested event_id is on a limited PMC, 2088 * but we can't use a limited PMC; see if any 2089 * alternative goes on a normal PMC. 2090 */ 2091 ev = normal_pmc_alternative(ev, flags); 2092 if (!ev) 2093 return -EINVAL; 2094 } 2095 } 2096 2097 /* Extra checks for EBB */ 2098 err = ebb_event_check(event); 2099 if (err) 2100 return err; 2101 2102 /* 2103 * If this is in a group, check if it can go on with all the 2104 * other hardware events in the group. We assume the event 2105 * hasn't been linked into its leader's sibling list at this point. 2106 */ 2107 n = 0; 2108 if (event->group_leader != event) { 2109 n = collect_events(event->group_leader, ppmu->n_counter - 1, 2110 ctrs, events, cflags); 2111 if (n < 0) 2112 return -EINVAL; 2113 } 2114 events[n] = ev; 2115 ctrs[n] = event; 2116 cflags[n] = flags; 2117 if (check_excludes(ctrs, cflags, n, 1)) 2118 return -EINVAL; 2119 2120 local_irq_save(irq_flags); 2121 cpuhw = this_cpu_ptr(&cpu_hw_events); 2122 2123 err = power_check_constraints(cpuhw, events, cflags, n + 1, ctrs); 2124 2125 if (has_branch_stack(event)) { 2126 u64 bhrb_filter = -1; 2127 2128 if (ppmu->bhrb_filter_map) 2129 bhrb_filter = ppmu->bhrb_filter_map( 2130 event->attr.branch_sample_type); 2131 2132 if (bhrb_filter == -1) { 2133 local_irq_restore(irq_flags); 2134 return -EOPNOTSUPP; 2135 } 2136 cpuhw->bhrb_filter = bhrb_filter; 2137 } 2138 2139 local_irq_restore(irq_flags); 2140 if (err) 2141 return -EINVAL; 2142 2143 event->hw.config = events[n]; 2144 event->hw.event_base = cflags[n]; 2145 event->hw.last_period = event->hw.sample_period; 2146 local64_set(&event->hw.period_left, event->hw.last_period); 2147 2148 /* 2149 * For EBB events we just context switch the PMC value, we don't do any 2150 * of the sample_period logic. We use hw.prev_count for this. 2151 */ 2152 if (is_ebb_event(event)) 2153 local64_set(&event->hw.prev_count, 0); 2154 2155 /* 2156 * See if we need to reserve the PMU. 2157 * If no events are currently in use, then we have to take a 2158 * mutex to ensure that we don't race with another task doing 2159 * reserve_pmc_hardware or release_pmc_hardware. 2160 */ 2161 err = 0; 2162 if (!atomic_inc_not_zero(&num_events)) { 2163 mutex_lock(&pmc_reserve_mutex); 2164 if (atomic_read(&num_events) == 0 && 2165 reserve_pmc_hardware(perf_event_interrupt)) 2166 err = -EBUSY; 2167 else 2168 atomic_inc(&num_events); 2169 mutex_unlock(&pmc_reserve_mutex); 2170 } 2171 event->destroy = hw_perf_event_destroy; 2172 2173 return err; 2174 } 2175 2176 static int power_pmu_event_idx(struct perf_event *event) 2177 { 2178 return event->hw.idx; 2179 } 2180 2181 ssize_t power_events_sysfs_show(struct device *dev, 2182 struct device_attribute *attr, char *page) 2183 { 2184 struct perf_pmu_events_attr *pmu_attr; 2185 2186 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 2187 2188 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 2189 } 2190 2191 static struct pmu power_pmu = { 2192 .pmu_enable = power_pmu_enable, 2193 .pmu_disable = power_pmu_disable, 2194 .event_init = power_pmu_event_init, 2195 .add = power_pmu_add, 2196 .del = power_pmu_del, 2197 .start = power_pmu_start, 2198 .stop = power_pmu_stop, 2199 .read = power_pmu_read, 2200 .start_txn = power_pmu_start_txn, 2201 .cancel_txn = power_pmu_cancel_txn, 2202 .commit_txn = power_pmu_commit_txn, 2203 .event_idx = power_pmu_event_idx, 2204 .sched_task = power_pmu_sched_task, 2205 }; 2206 2207 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \ 2208 PERF_SAMPLE_PHYS_ADDR | \ 2209 PERF_SAMPLE_DATA_PAGE_SIZE) 2210 /* 2211 * A counter has overflowed; update its count and record 2212 * things if requested. Note that interrupts are hard-disabled 2213 * here so there is no possibility of being interrupted. 2214 */ 2215 static void record_and_restart(struct perf_event *event, unsigned long val, 2216 struct pt_regs *regs) 2217 { 2218 u64 period = event->hw.sample_period; 2219 s64 prev, delta, left; 2220 int record = 0; 2221 2222 if (event->hw.state & PERF_HES_STOPPED) { 2223 write_pmc(event->hw.idx, 0); 2224 return; 2225 } 2226 2227 /* we don't have to worry about interrupts here */ 2228 prev = local64_read(&event->hw.prev_count); 2229 delta = check_and_compute_delta(prev, val); 2230 local64_add(delta, &event->count); 2231 2232 /* 2233 * See if the total period for this event has expired, 2234 * and update for the next period. 2235 */ 2236 val = 0; 2237 left = local64_read(&event->hw.period_left) - delta; 2238 if (delta == 0) 2239 left++; 2240 if (period) { 2241 if (left <= 0) { 2242 left += period; 2243 if (left <= 0) 2244 left = period; 2245 2246 /* 2247 * If address is not requested in the sample via 2248 * PERF_SAMPLE_IP, just record that sample irrespective 2249 * of SIAR valid check. 2250 */ 2251 if (event->attr.sample_type & PERF_SAMPLE_IP) 2252 record = siar_valid(regs); 2253 else 2254 record = 1; 2255 2256 event->hw.last_period = event->hw.sample_period; 2257 } 2258 if (left < 0x80000000LL) 2259 val = 0x80000000LL - left; 2260 } 2261 2262 write_pmc(event->hw.idx, val); 2263 local64_set(&event->hw.prev_count, val); 2264 local64_set(&event->hw.period_left, left); 2265 perf_event_update_userpage(event); 2266 2267 /* 2268 * Due to hardware limitation, sometimes SIAR could sample a kernel 2269 * address even when freeze on supervisor state (kernel) is set in 2270 * MMCR2. Check attr.exclude_kernel and address to drop the sample in 2271 * these cases. 2272 */ 2273 if (event->attr.exclude_kernel && 2274 (event->attr.sample_type & PERF_SAMPLE_IP) && 2275 is_kernel_addr(mfspr(SPRN_SIAR))) 2276 record = 0; 2277 2278 /* 2279 * Finally record data if requested. 2280 */ 2281 if (record) { 2282 struct perf_sample_data data; 2283 2284 perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2285 2286 if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE) 2287 perf_get_data_addr(event, regs, &data.addr); 2288 2289 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 2290 struct cpu_hw_events *cpuhw; 2291 cpuhw = this_cpu_ptr(&cpu_hw_events); 2292 power_pmu_bhrb_read(event, cpuhw); 2293 data.br_stack = &cpuhw->bhrb_stack; 2294 } 2295 2296 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 2297 ppmu->get_mem_data_src) 2298 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 2299 2300 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE && 2301 ppmu->get_mem_weight) 2302 ppmu->get_mem_weight(&data.weight.full, event->attr.sample_type); 2303 2304 if (perf_event_overflow(event, &data, regs)) 2305 power_pmu_stop(event, 0); 2306 } else if (period) { 2307 /* Account for interrupt in case of invalid SIAR */ 2308 if (perf_event_account_interrupt(event)) 2309 power_pmu_stop(event, 0); 2310 } 2311 } 2312 2313 /* 2314 * Called from generic code to get the misc flags (i.e. processor mode) 2315 * for an event_id. 2316 */ 2317 unsigned long perf_misc_flags(struct pt_regs *regs) 2318 { 2319 u32 flags = perf_get_misc_flags(regs); 2320 2321 if (flags) 2322 return flags; 2323 return user_mode(regs) ? PERF_RECORD_MISC_USER : 2324 PERF_RECORD_MISC_KERNEL; 2325 } 2326 2327 /* 2328 * Called from generic code to get the instruction pointer 2329 * for an event_id. 2330 */ 2331 unsigned long perf_instruction_pointer(struct pt_regs *regs) 2332 { 2333 unsigned long siar = mfspr(SPRN_SIAR); 2334 2335 if (regs_use_siar(regs) && siar_valid(regs) && siar) 2336 return siar + perf_ip_adjust(regs); 2337 else 2338 return regs->nip; 2339 } 2340 2341 static bool pmc_overflow_power7(unsigned long val) 2342 { 2343 /* 2344 * Events on POWER7 can roll back if a speculative event doesn't 2345 * eventually complete. Unfortunately in some rare cases they will 2346 * raise a performance monitor exception. We need to catch this to 2347 * ensure we reset the PMC. In all cases the PMC will be 256 or less 2348 * cycles from overflow. 2349 * 2350 * We only do this if the first pass fails to find any overflowing 2351 * PMCs because a user might set a period of less than 256 and we 2352 * don't want to mistakenly reset them. 2353 */ 2354 if ((0x80000000 - val) <= 256) 2355 return true; 2356 2357 return false; 2358 } 2359 2360 static bool pmc_overflow(unsigned long val) 2361 { 2362 if ((int)val < 0) 2363 return true; 2364 2365 return false; 2366 } 2367 2368 /* 2369 * Performance monitor interrupt stuff 2370 */ 2371 static void __perf_event_interrupt(struct pt_regs *regs) 2372 { 2373 int i, j; 2374 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2375 struct perf_event *event; 2376 int found, active; 2377 2378 if (cpuhw->n_limited) 2379 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2380 mfspr(SPRN_PMC6)); 2381 2382 perf_read_regs(regs); 2383 2384 /* Read all the PMCs since we'll need them a bunch of times */ 2385 for (i = 0; i < ppmu->n_counter; ++i) 2386 cpuhw->pmcs[i] = read_pmc(i + 1); 2387 2388 /* Try to find what caused the IRQ */ 2389 found = 0; 2390 for (i = 0; i < ppmu->n_counter; ++i) { 2391 if (!pmc_overflow(cpuhw->pmcs[i])) 2392 continue; 2393 if (is_limited_pmc(i + 1)) 2394 continue; /* these won't generate IRQs */ 2395 /* 2396 * We've found one that's overflowed. For active 2397 * counters we need to log this. For inactive 2398 * counters, we need to reset it anyway 2399 */ 2400 found = 1; 2401 active = 0; 2402 for (j = 0; j < cpuhw->n_events; ++j) { 2403 event = cpuhw->event[j]; 2404 if (event->hw.idx == (i + 1)) { 2405 active = 1; 2406 record_and_restart(event, cpuhw->pmcs[i], regs); 2407 break; 2408 } 2409 } 2410 2411 /* 2412 * Clear PACA_IRQ_PMI in case it was set by 2413 * set_pmi_irq_pending() when PMU was enabled 2414 * after accounting for interrupts. 2415 */ 2416 clear_pmi_irq_pending(); 2417 2418 if (!active) 2419 /* reset non active counters that have overflowed */ 2420 write_pmc(i + 1, 0); 2421 } 2422 if (!found && pvr_version_is(PVR_POWER7)) { 2423 /* check active counters for special buggy p7 overflow */ 2424 for (i = 0; i < cpuhw->n_events; ++i) { 2425 event = cpuhw->event[i]; 2426 if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2427 continue; 2428 if (pmc_overflow_power7(cpuhw->pmcs[event->hw.idx - 1])) { 2429 /* event has overflowed in a buggy way*/ 2430 found = 1; 2431 record_and_restart(event, 2432 cpuhw->pmcs[event->hw.idx - 1], 2433 regs); 2434 } 2435 } 2436 } 2437 2438 /* 2439 * During system wide profling or while specific CPU is monitored for an 2440 * event, some corner cases could cause PMC to overflow in idle path. This 2441 * will trigger a PMI after waking up from idle. Since counter values are _not_ 2442 * saved/restored in idle path, can lead to below "Can't find PMC" message. 2443 */ 2444 if (unlikely(!found) && !arch_irq_disabled_regs(regs)) 2445 printk_ratelimited(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2446 2447 /* 2448 * Reset MMCR0 to its normal value. This will set PMXE and 2449 * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2450 * and thus allow interrupts to occur again. 2451 * XXX might want to use MSR.PM to keep the events frozen until 2452 * we get back out of this interrupt. 2453 */ 2454 write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0); 2455 2456 /* Clear the cpuhw->pmcs */ 2457 memset(&cpuhw->pmcs, 0, sizeof(cpuhw->pmcs)); 2458 2459 } 2460 2461 static void perf_event_interrupt(struct pt_regs *regs) 2462 { 2463 u64 start_clock = sched_clock(); 2464 2465 __perf_event_interrupt(regs); 2466 perf_sample_event_took(sched_clock() - start_clock); 2467 } 2468 2469 static int power_pmu_prepare_cpu(unsigned int cpu) 2470 { 2471 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2472 2473 if (ppmu) { 2474 memset(cpuhw, 0, sizeof(*cpuhw)); 2475 cpuhw->mmcr.mmcr0 = MMCR0_FC; 2476 } 2477 return 0; 2478 } 2479 2480 int __init register_power_pmu(struct power_pmu *pmu) 2481 { 2482 if (ppmu) 2483 return -EBUSY; /* something's already registered */ 2484 2485 ppmu = pmu; 2486 pr_info("%s performance monitor hardware support registered\n", 2487 pmu->name); 2488 2489 power_pmu.attr_groups = ppmu->attr_groups; 2490 power_pmu.capabilities |= (ppmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS); 2491 2492 #ifdef MSR_HV 2493 /* 2494 * Use FCHV to ignore kernel events if MSR.HV is set. 2495 */ 2496 if (mfmsr() & MSR_HV) 2497 freeze_events_kernel = MMCR0_FCHV; 2498 #endif /* CONFIG_PPC64 */ 2499 2500 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 2501 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 2502 power_pmu_prepare_cpu, NULL); 2503 return 0; 2504 } 2505 2506 #ifdef CONFIG_PPC64 2507 static bool pmu_override = false; 2508 static unsigned long pmu_override_val; 2509 static void do_pmu_override(void *data) 2510 { 2511 ppc_set_pmu_inuse(1); 2512 if (pmu_override_val) 2513 mtspr(SPRN_MMCR1, pmu_override_val); 2514 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC); 2515 } 2516 2517 static int __init init_ppc64_pmu(void) 2518 { 2519 if (cpu_has_feature(CPU_FTR_HVMODE) && pmu_override) { 2520 pr_warn("disabling perf due to pmu_override= command line option.\n"); 2521 on_each_cpu(do_pmu_override, NULL, 1); 2522 return 0; 2523 } 2524 2525 /* run through all the pmu drivers one at a time */ 2526 if (!init_power5_pmu()) 2527 return 0; 2528 else if (!init_power5p_pmu()) 2529 return 0; 2530 else if (!init_power6_pmu()) 2531 return 0; 2532 else if (!init_power7_pmu()) 2533 return 0; 2534 else if (!init_power8_pmu()) 2535 return 0; 2536 else if (!init_power9_pmu()) 2537 return 0; 2538 else if (!init_power10_pmu()) 2539 return 0; 2540 else if (!init_ppc970_pmu()) 2541 return 0; 2542 else 2543 return init_generic_compat_pmu(); 2544 } 2545 early_initcall(init_ppc64_pmu); 2546 2547 static int __init pmu_setup(char *str) 2548 { 2549 unsigned long val; 2550 2551 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) 2552 return 0; 2553 2554 pmu_override = true; 2555 2556 if (kstrtoul(str, 0, &val)) 2557 val = 0; 2558 2559 pmu_override_val = val; 2560 2561 return 1; 2562 } 2563 __setup("pmu_override=", pmu_setup); 2564 2565 #endif 2566