1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * bpf_jit_comp64.c: eBPF JIT compiler 4 * 5 * Copyright 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 6 * IBM Corporation 7 * 8 * Based on the powerpc classic BPF JIT compiler by Matt Evans 9 */ 10 #include <linux/moduleloader.h> 11 #include <asm/cacheflush.h> 12 #include <asm/asm-compat.h> 13 #include <linux/netdevice.h> 14 #include <linux/filter.h> 15 #include <linux/if_vlan.h> 16 #include <asm/kprobes.h> 17 #include <linux/bpf.h> 18 #include <asm/security_features.h> 19 20 #include "bpf_jit.h" 21 22 /* 23 * Stack layout: 24 * Ensure the top half (upto local_tmp_var) stays consistent 25 * with our redzone usage. 26 * 27 * [ prev sp ] <------------- 28 * [ nv gpr save area ] 5*8 | 29 * [ tail_call_cnt ] 8 | 30 * [ local_tmp_var ] 16 | 31 * fp (r31) --> [ ebpf stack space ] upto 512 | 32 * [ frame header ] 32/112 | 33 * sp (r1) ---> [ stack pointer ] -------------- 34 */ 35 36 /* for gpr non volatile registers BPG_REG_6 to 10 */ 37 #define BPF_PPC_STACK_SAVE (5*8) 38 /* for bpf JIT code internal usage */ 39 #define BPF_PPC_STACK_LOCALS 24 40 /* stack frame excluding BPF stack, ensure this is quadword aligned */ 41 #define BPF_PPC_STACKFRAME (STACK_FRAME_MIN_SIZE + \ 42 BPF_PPC_STACK_LOCALS + BPF_PPC_STACK_SAVE) 43 44 /* BPF register usage */ 45 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 46 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 47 48 /* BPF to ppc register mappings */ 49 void bpf_jit_init_reg_mapping(struct codegen_context *ctx) 50 { 51 /* function return value */ 52 ctx->b2p[BPF_REG_0] = _R8; 53 /* function arguments */ 54 ctx->b2p[BPF_REG_1] = _R3; 55 ctx->b2p[BPF_REG_2] = _R4; 56 ctx->b2p[BPF_REG_3] = _R5; 57 ctx->b2p[BPF_REG_4] = _R6; 58 ctx->b2p[BPF_REG_5] = _R7; 59 /* non volatile registers */ 60 ctx->b2p[BPF_REG_6] = _R27; 61 ctx->b2p[BPF_REG_7] = _R28; 62 ctx->b2p[BPF_REG_8] = _R29; 63 ctx->b2p[BPF_REG_9] = _R30; 64 /* frame pointer aka BPF_REG_10 */ 65 ctx->b2p[BPF_REG_FP] = _R31; 66 /* eBPF jit internal registers */ 67 ctx->b2p[BPF_REG_AX] = _R12; 68 ctx->b2p[TMP_REG_1] = _R9; 69 ctx->b2p[TMP_REG_2] = _R10; 70 } 71 72 /* PPC NVR range -- update this if we ever use NVRs below r27 */ 73 #define BPF_PPC_NVR_MIN _R27 74 75 static inline bool bpf_has_stack_frame(struct codegen_context *ctx) 76 { 77 /* 78 * We only need a stack frame if: 79 * - we call other functions (kernel helpers), or 80 * - the bpf program uses its stack area 81 * The latter condition is deduced from the usage of BPF_REG_FP 82 */ 83 return ctx->seen & SEEN_FUNC || bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP)); 84 } 85 86 /* 87 * When not setting up our own stackframe, the redzone (288 bytes) usage is: 88 * 89 * [ prev sp ] <------------- 90 * [ ... ] | 91 * sp (r1) ---> [ stack pointer ] -------------- 92 * [ nv gpr save area ] 5*8 93 * [ tail_call_cnt ] 8 94 * [ local_tmp_var ] 16 95 * [ unused red zone ] 224 96 */ 97 static int bpf_jit_stack_local(struct codegen_context *ctx) 98 { 99 if (bpf_has_stack_frame(ctx)) 100 return STACK_FRAME_MIN_SIZE + ctx->stack_size; 101 else 102 return -(BPF_PPC_STACK_SAVE + 24); 103 } 104 105 static int bpf_jit_stack_tailcallcnt(struct codegen_context *ctx) 106 { 107 return bpf_jit_stack_local(ctx) + 16; 108 } 109 110 static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg) 111 { 112 if (reg >= BPF_PPC_NVR_MIN && reg < 32) 113 return (bpf_has_stack_frame(ctx) ? 114 (BPF_PPC_STACKFRAME + ctx->stack_size) : 0) 115 - (8 * (32 - reg)); 116 117 pr_err("BPF JIT is asking about unknown registers"); 118 BUG(); 119 } 120 121 void bpf_jit_realloc_regs(struct codegen_context *ctx) 122 { 123 } 124 125 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) 126 { 127 int i; 128 129 /* Instruction for trampoline attach */ 130 EMIT(PPC_RAW_NOP()); 131 132 #ifndef CONFIG_PPC_KERNEL_PCREL 133 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2)) 134 EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc))); 135 #endif 136 137 /* 138 * Initialize tail_call_cnt if we do tail calls. 139 * Otherwise, put in NOPs so that it can be skipped when we are 140 * invoked through a tail call. 141 */ 142 if (ctx->seen & SEEN_TAILCALL) { 143 EMIT(PPC_RAW_LI(bpf_to_ppc(TMP_REG_1), 0)); 144 /* this goes in the redzone */ 145 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, -(BPF_PPC_STACK_SAVE + 8))); 146 } else { 147 EMIT(PPC_RAW_NOP()); 148 EMIT(PPC_RAW_NOP()); 149 } 150 151 if (bpf_has_stack_frame(ctx)) { 152 /* 153 * We need a stack frame, but we don't necessarily need to 154 * save/restore LR unless we call other functions 155 */ 156 if (ctx->seen & SEEN_FUNC) { 157 EMIT(PPC_RAW_MFLR(_R0)); 158 EMIT(PPC_RAW_STD(_R0, _R1, PPC_LR_STKOFF)); 159 } 160 161 EMIT(PPC_RAW_STDU(_R1, _R1, -(BPF_PPC_STACKFRAME + ctx->stack_size))); 162 } 163 164 /* 165 * Back up non-volatile regs -- BPF registers 6-10 166 * If we haven't created our own stack frame, we save these 167 * in the protected zone below the previous stack frame 168 */ 169 for (i = BPF_REG_6; i <= BPF_REG_10; i++) 170 if (bpf_is_seen_register(ctx, bpf_to_ppc(i))) 171 EMIT(PPC_RAW_STD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to_ppc(i)))); 172 173 /* Setup frame pointer to point to the bpf stack area */ 174 if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) 175 EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1, 176 STACK_FRAME_MIN_SIZE + ctx->stack_size)); 177 } 178 179 static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx) 180 { 181 int i; 182 183 /* Restore NVRs */ 184 for (i = BPF_REG_6; i <= BPF_REG_10; i++) 185 if (bpf_is_seen_register(ctx, bpf_to_ppc(i))) 186 EMIT(PPC_RAW_LD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to_ppc(i)))); 187 188 /* Tear down our stack frame */ 189 if (bpf_has_stack_frame(ctx)) { 190 EMIT(PPC_RAW_ADDI(_R1, _R1, BPF_PPC_STACKFRAME + ctx->stack_size)); 191 if (ctx->seen & SEEN_FUNC) { 192 EMIT(PPC_RAW_LD(_R0, _R1, PPC_LR_STKOFF)); 193 EMIT(PPC_RAW_MTLR(_R0)); 194 } 195 } 196 } 197 198 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) 199 { 200 bpf_jit_emit_common_epilogue(image, ctx); 201 202 /* Move result to r3 */ 203 EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(BPF_REG_0))); 204 205 EMIT(PPC_RAW_BLR()); 206 207 bpf_jit_build_fentry_stubs(image, ctx); 208 } 209 210 int bpf_jit_emit_func_call_rel(u32 *image, u32 *fimage, struct codegen_context *ctx, u64 func) 211 { 212 unsigned long func_addr = func ? ppc_function_entry((void *)func) : 0; 213 long reladdr; 214 215 /* bpf to bpf call, func is not known in the initial pass. Emit 5 nops as a placeholder */ 216 if (!func) { 217 for (int i = 0; i < 5; i++) 218 EMIT(PPC_RAW_NOP()); 219 /* elfv1 needs an additional instruction to load addr from descriptor */ 220 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) 221 EMIT(PPC_RAW_NOP()); 222 EMIT(PPC_RAW_MTCTR(_R12)); 223 EMIT(PPC_RAW_BCTRL()); 224 return 0; 225 } 226 227 #ifdef CONFIG_PPC_KERNEL_PCREL 228 reladdr = func_addr - local_paca->kernelbase; 229 230 /* 231 * If fimage is NULL (the initial pass to find image size), 232 * account for the maximum no. of instructions possible. 233 */ 234 if (!fimage) { 235 ctx->idx += 7; 236 return 0; 237 } else if (reladdr < (long)SZ_8G && reladdr >= -(long)SZ_8G) { 238 EMIT(PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernelbase))); 239 /* Align for subsequent prefix instruction */ 240 if (!IS_ALIGNED((unsigned long)fimage + CTX_NIA(ctx), 8)) 241 EMIT(PPC_RAW_NOP()); 242 /* paddi r12,r12,addr */ 243 EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(0) | IMM_H18(reladdr)); 244 EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | ___PPC_RA(_R12) | IMM_L(reladdr)); 245 } else { 246 unsigned long pc = (unsigned long)fimage + CTX_NIA(ctx); 247 bool alignment_needed = !IS_ALIGNED(pc, 8); 248 249 reladdr = func_addr - (alignment_needed ? pc + 4 : pc); 250 251 if (reladdr < (long)SZ_8G && reladdr >= -(long)SZ_8G) { 252 if (alignment_needed) 253 EMIT(PPC_RAW_NOP()); 254 /* pla r12,addr */ 255 EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(1) | IMM_H18(reladdr)); 256 EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | IMM_L(reladdr)); 257 } else { 258 /* We can clobber r12 */ 259 PPC_LI64(_R12, func); 260 } 261 } 262 EMIT(PPC_RAW_MTCTR(_R12)); 263 EMIT(PPC_RAW_BCTRL()); 264 #else 265 if (core_kernel_text(func_addr)) { 266 reladdr = func_addr - kernel_toc_addr(); 267 if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) { 268 pr_err("eBPF: address of %ps out of range of kernel_toc.\n", (void *)func); 269 return -ERANGE; 270 } 271 272 EMIT(PPC_RAW_ADDIS(_R12, _R2, PPC_HA(reladdr))); 273 EMIT(PPC_RAW_ADDI(_R12, _R12, PPC_LO(reladdr))); 274 EMIT(PPC_RAW_MTCTR(_R12)); 275 EMIT(PPC_RAW_BCTRL()); 276 } else { 277 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) { 278 /* func points to the function descriptor */ 279 PPC_LI64(bpf_to_ppc(TMP_REG_2), func); 280 /* Load actual entry point from function descriptor */ 281 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), 0)); 282 /* ... and move it to CTR */ 283 EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_1))); 284 /* 285 * Load TOC from function descriptor at offset 8. 286 * We can clobber r2 since we get called through a 287 * function pointer (so caller will save/restore r2). 288 */ 289 if (is_module_text_address(func_addr)) 290 EMIT(PPC_RAW_LD(_R2, bpf_to_ppc(TMP_REG_2), 8)); 291 } else { 292 PPC_LI64(_R12, func); 293 EMIT(PPC_RAW_MTCTR(_R12)); 294 } 295 EMIT(PPC_RAW_BCTRL()); 296 /* 297 * Load r2 with kernel TOC as kernel TOC is used if function address falls 298 * within core kernel text. 299 */ 300 if (is_module_text_address(func_addr)) 301 EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc))); 302 } 303 #endif 304 305 return 0; 306 } 307 308 static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out) 309 { 310 /* 311 * By now, the eBPF program has already setup parameters in r3, r4 and r5 312 * r3/BPF_REG_1 - pointer to ctx -- passed as is to the next bpf program 313 * r4/BPF_REG_2 - pointer to bpf_array 314 * r5/BPF_REG_3 - index in bpf_array 315 */ 316 int b2p_bpf_array = bpf_to_ppc(BPF_REG_2); 317 int b2p_index = bpf_to_ppc(BPF_REG_3); 318 int bpf_tailcall_prologue_size = 12; 319 320 if (!IS_ENABLED(CONFIG_PPC_KERNEL_PCREL) && IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2)) 321 bpf_tailcall_prologue_size += 4; /* skip past the toc load */ 322 323 /* 324 * if (index >= array->map.max_entries) 325 * goto out; 326 */ 327 EMIT(PPC_RAW_LWZ(bpf_to_ppc(TMP_REG_1), b2p_bpf_array, offsetof(struct bpf_array, map.max_entries))); 328 EMIT(PPC_RAW_RLWINM(b2p_index, b2p_index, 0, 0, 31)); 329 EMIT(PPC_RAW_CMPLW(b2p_index, bpf_to_ppc(TMP_REG_1))); 330 PPC_BCC_SHORT(COND_GE, out); 331 332 /* 333 * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) 334 * goto out; 335 */ 336 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), _R1, bpf_jit_stack_tailcallcnt(ctx))); 337 EMIT(PPC_RAW_CMPLWI(bpf_to_ppc(TMP_REG_1), MAX_TAIL_CALL_CNT)); 338 PPC_BCC_SHORT(COND_GE, out); 339 340 /* 341 * tail_call_cnt++; 342 */ 343 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 1)); 344 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, bpf_jit_stack_tailcallcnt(ctx))); 345 346 /* prog = array->ptrs[index]; */ 347 EMIT(PPC_RAW_MULI(bpf_to_ppc(TMP_REG_1), b2p_index, 8)); 348 EMIT(PPC_RAW_ADD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), b2p_bpf_array)); 349 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), offsetof(struct bpf_array, ptrs))); 350 351 /* 352 * if (prog == NULL) 353 * goto out; 354 */ 355 EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_1), 0)); 356 PPC_BCC_SHORT(COND_EQ, out); 357 358 /* goto *(prog->bpf_func + prologue_size); */ 359 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), offsetof(struct bpf_prog, bpf_func))); 360 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 361 FUNCTION_DESCR_SIZE + bpf_tailcall_prologue_size)); 362 EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_1))); 363 364 /* tear down stack, restore NVRs, ... */ 365 bpf_jit_emit_common_epilogue(image, ctx); 366 367 EMIT(PPC_RAW_BCTR()); 368 369 /* out: */ 370 return 0; 371 } 372 373 /* 374 * We spill into the redzone always, even if the bpf program has its own stackframe. 375 * Offsets hardcoded based on BPF_PPC_STACK_SAVE -- see bpf_jit_stack_local() 376 */ 377 void bpf_stf_barrier(void); 378 379 asm ( 380 " .global bpf_stf_barrier ;" 381 " bpf_stf_barrier: ;" 382 " std 21,-64(1) ;" 383 " std 22,-56(1) ;" 384 " sync ;" 385 " ld 21,-64(1) ;" 386 " ld 22,-56(1) ;" 387 " ori 31,31,0 ;" 388 " .rept 14 ;" 389 " b 1f ;" 390 " 1: ;" 391 " .endr ;" 392 " blr ;" 393 ); 394 395 /* Assemble the body code between the prologue & epilogue */ 396 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct codegen_context *ctx, 397 u32 *addrs, int pass, bool extra_pass) 398 { 399 enum stf_barrier_type stf_barrier = stf_barrier_type_get(); 400 const struct bpf_insn *insn = fp->insnsi; 401 int flen = fp->len; 402 int i, ret; 403 404 /* Start of epilogue code - will only be valid 2nd pass onwards */ 405 u32 exit_addr = addrs[flen]; 406 407 for (i = 0; i < flen; i++) { 408 u32 code = insn[i].code; 409 u32 dst_reg = bpf_to_ppc(insn[i].dst_reg); 410 u32 src_reg = bpf_to_ppc(insn[i].src_reg); 411 u32 size = BPF_SIZE(code); 412 u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); 413 u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); 414 u32 save_reg, ret_reg; 415 s16 off = insn[i].off; 416 s32 imm = insn[i].imm; 417 bool func_addr_fixed; 418 u64 func_addr; 419 u64 imm64; 420 u32 true_cond; 421 u32 tmp_idx; 422 423 /* 424 * addrs[] maps a BPF bytecode address into a real offset from 425 * the start of the body code. 426 */ 427 addrs[i] = ctx->idx * 4; 428 429 /* 430 * As an optimization, we note down which non-volatile registers 431 * are used so that we can only save/restore those in our 432 * prologue and epilogue. We do this here regardless of whether 433 * the actual BPF instruction uses src/dst registers or not 434 * (for instance, BPF_CALL does not use them). The expectation 435 * is that those instructions will have src_reg/dst_reg set to 436 * 0. Even otherwise, we just lose some prologue/epilogue 437 * optimization but everything else should work without 438 * any issues. 439 */ 440 if (dst_reg >= BPF_PPC_NVR_MIN && dst_reg < 32) 441 bpf_set_seen_register(ctx, dst_reg); 442 if (src_reg >= BPF_PPC_NVR_MIN && src_reg < 32) 443 bpf_set_seen_register(ctx, src_reg); 444 445 switch (code) { 446 /* 447 * Arithmetic operations: ADD/SUB/MUL/DIV/MOD/NEG 448 */ 449 case BPF_ALU | BPF_ADD | BPF_X: /* (u32) dst += (u32) src */ 450 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst += src */ 451 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, src_reg)); 452 goto bpf_alu32_trunc; 453 case BPF_ALU | BPF_SUB | BPF_X: /* (u32) dst -= (u32) src */ 454 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst -= src */ 455 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, src_reg)); 456 goto bpf_alu32_trunc; 457 case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */ 458 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */ 459 if (!imm) { 460 goto bpf_alu32_trunc; 461 } else if (imm >= -32768 && imm < 32768) { 462 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm))); 463 } else { 464 PPC_LI32(tmp1_reg, imm); 465 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, tmp1_reg)); 466 } 467 goto bpf_alu32_trunc; 468 case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */ 469 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */ 470 if (!imm) { 471 goto bpf_alu32_trunc; 472 } else if (imm > -32768 && imm <= 32768) { 473 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(-imm))); 474 } else { 475 PPC_LI32(tmp1_reg, imm); 476 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 477 } 478 goto bpf_alu32_trunc; 479 case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */ 480 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */ 481 if (BPF_CLASS(code) == BPF_ALU) 482 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg)); 483 else 484 EMIT(PPC_RAW_MULD(dst_reg, dst_reg, src_reg)); 485 goto bpf_alu32_trunc; 486 case BPF_ALU | BPF_MUL | BPF_K: /* (u32) dst *= (u32) imm */ 487 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */ 488 if (imm >= -32768 && imm < 32768) 489 EMIT(PPC_RAW_MULI(dst_reg, dst_reg, IMM_L(imm))); 490 else { 491 PPC_LI32(tmp1_reg, imm); 492 if (BPF_CLASS(code) == BPF_ALU) 493 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, tmp1_reg)); 494 else 495 EMIT(PPC_RAW_MULD(dst_reg, dst_reg, tmp1_reg)); 496 } 497 goto bpf_alu32_trunc; 498 case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */ 499 case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */ 500 if (BPF_OP(code) == BPF_MOD) { 501 if (off) 502 EMIT(PPC_RAW_DIVW(tmp1_reg, dst_reg, src_reg)); 503 else 504 EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg)); 505 506 EMIT(PPC_RAW_MULW(tmp1_reg, src_reg, tmp1_reg)); 507 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 508 } else 509 if (off) 510 EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, src_reg)); 511 else 512 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg)); 513 goto bpf_alu32_trunc; 514 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */ 515 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */ 516 if (BPF_OP(code) == BPF_MOD) { 517 if (off) 518 EMIT(PPC_RAW_DIVD(tmp1_reg, dst_reg, src_reg)); 519 else 520 EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg)); 521 EMIT(PPC_RAW_MULD(tmp1_reg, src_reg, tmp1_reg)); 522 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 523 } else 524 if (off) 525 EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, src_reg)); 526 else 527 EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg)); 528 break; 529 case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */ 530 case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */ 531 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst %= imm */ 532 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */ 533 if (imm == 0) 534 return -EINVAL; 535 if (imm == 1) { 536 if (BPF_OP(code) == BPF_DIV) { 537 goto bpf_alu32_trunc; 538 } else { 539 EMIT(PPC_RAW_LI(dst_reg, 0)); 540 break; 541 } 542 } 543 544 PPC_LI32(tmp1_reg, imm); 545 switch (BPF_CLASS(code)) { 546 case BPF_ALU: 547 if (BPF_OP(code) == BPF_MOD) { 548 if (off) 549 EMIT(PPC_RAW_DIVW(tmp2_reg, dst_reg, tmp1_reg)); 550 else 551 EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg)); 552 EMIT(PPC_RAW_MULW(tmp1_reg, tmp1_reg, tmp2_reg)); 553 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 554 } else 555 if (off) 556 EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, tmp1_reg)); 557 else 558 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg)); 559 break; 560 case BPF_ALU64: 561 if (BPF_OP(code) == BPF_MOD) { 562 if (off) 563 EMIT(PPC_RAW_DIVD(tmp2_reg, dst_reg, tmp1_reg)); 564 else 565 EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg)); 566 EMIT(PPC_RAW_MULD(tmp1_reg, tmp1_reg, tmp2_reg)); 567 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 568 } else 569 if (off) 570 EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, tmp1_reg)); 571 else 572 EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg)); 573 break; 574 } 575 goto bpf_alu32_trunc; 576 case BPF_ALU | BPF_NEG: /* (u32) dst = -dst */ 577 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 578 EMIT(PPC_RAW_NEG(dst_reg, dst_reg)); 579 goto bpf_alu32_trunc; 580 581 /* 582 * Logical operations: AND/OR/XOR/[A]LSH/[A]RSH 583 */ 584 case BPF_ALU | BPF_AND | BPF_X: /* (u32) dst = dst & src */ 585 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 586 EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg)); 587 goto bpf_alu32_trunc; 588 case BPF_ALU | BPF_AND | BPF_K: /* (u32) dst = dst & imm */ 589 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 590 if (!IMM_H(imm)) 591 EMIT(PPC_RAW_ANDI(dst_reg, dst_reg, IMM_L(imm))); 592 else { 593 /* Sign-extended */ 594 PPC_LI32(tmp1_reg, imm); 595 EMIT(PPC_RAW_AND(dst_reg, dst_reg, tmp1_reg)); 596 } 597 goto bpf_alu32_trunc; 598 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 599 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 600 EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg)); 601 goto bpf_alu32_trunc; 602 case BPF_ALU | BPF_OR | BPF_K:/* dst = (u32) dst | (u32) imm */ 603 case BPF_ALU64 | BPF_OR | BPF_K:/* dst = dst | imm */ 604 if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) { 605 /* Sign-extended */ 606 PPC_LI32(tmp1_reg, imm); 607 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp1_reg)); 608 } else { 609 if (IMM_L(imm)) 610 EMIT(PPC_RAW_ORI(dst_reg, dst_reg, IMM_L(imm))); 611 if (IMM_H(imm)) 612 EMIT(PPC_RAW_ORIS(dst_reg, dst_reg, IMM_H(imm))); 613 } 614 goto bpf_alu32_trunc; 615 case BPF_ALU | BPF_XOR | BPF_X: /* (u32) dst ^= src */ 616 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst ^= src */ 617 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg)); 618 goto bpf_alu32_trunc; 619 case BPF_ALU | BPF_XOR | BPF_K: /* (u32) dst ^= (u32) imm */ 620 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst ^= imm */ 621 if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) { 622 /* Sign-extended */ 623 PPC_LI32(tmp1_reg, imm); 624 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, tmp1_reg)); 625 } else { 626 if (IMM_L(imm)) 627 EMIT(PPC_RAW_XORI(dst_reg, dst_reg, IMM_L(imm))); 628 if (IMM_H(imm)) 629 EMIT(PPC_RAW_XORIS(dst_reg, dst_reg, IMM_H(imm))); 630 } 631 goto bpf_alu32_trunc; 632 case BPF_ALU | BPF_LSH | BPF_X: /* (u32) dst <<= (u32) src */ 633 /* slw clears top 32 bits */ 634 EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg)); 635 /* skip zero extension move, but set address map. */ 636 if (insn_is_zext(&insn[i + 1])) 637 addrs[++i] = ctx->idx * 4; 638 break; 639 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */ 640 EMIT(PPC_RAW_SLD(dst_reg, dst_reg, src_reg)); 641 break; 642 case BPF_ALU | BPF_LSH | BPF_K: /* (u32) dst <<== (u32) imm */ 643 /* with imm 0, we still need to clear top 32 bits */ 644 EMIT(PPC_RAW_SLWI(dst_reg, dst_reg, imm)); 645 if (insn_is_zext(&insn[i + 1])) 646 addrs[++i] = ctx->idx * 4; 647 break; 648 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst <<== imm */ 649 if (imm != 0) 650 EMIT(PPC_RAW_SLDI(dst_reg, dst_reg, imm)); 651 break; 652 case BPF_ALU | BPF_RSH | BPF_X: /* (u32) dst >>= (u32) src */ 653 EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); 654 if (insn_is_zext(&insn[i + 1])) 655 addrs[++i] = ctx->idx * 4; 656 break; 657 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */ 658 EMIT(PPC_RAW_SRD(dst_reg, dst_reg, src_reg)); 659 break; 660 case BPF_ALU | BPF_RSH | BPF_K: /* (u32) dst >>= (u32) imm */ 661 EMIT(PPC_RAW_SRWI(dst_reg, dst_reg, imm)); 662 if (insn_is_zext(&insn[i + 1])) 663 addrs[++i] = ctx->idx * 4; 664 break; 665 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst >>= imm */ 666 if (imm != 0) 667 EMIT(PPC_RAW_SRDI(dst_reg, dst_reg, imm)); 668 break; 669 case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */ 670 EMIT(PPC_RAW_SRAW(dst_reg, dst_reg, src_reg)); 671 goto bpf_alu32_trunc; 672 case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ 673 EMIT(PPC_RAW_SRAD(dst_reg, dst_reg, src_reg)); 674 break; 675 case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ 676 EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg, imm)); 677 goto bpf_alu32_trunc; 678 case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */ 679 if (imm != 0) 680 EMIT(PPC_RAW_SRADI(dst_reg, dst_reg, imm)); 681 break; 682 683 /* 684 * MOV 685 */ 686 case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */ 687 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 688 if (imm == 1) { 689 /* special mov32 for zext */ 690 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31)); 691 break; 692 } else if (off == 8) { 693 EMIT(PPC_RAW_EXTSB(dst_reg, src_reg)); 694 } else if (off == 16) { 695 EMIT(PPC_RAW_EXTSH(dst_reg, src_reg)); 696 } else if (off == 32) { 697 EMIT(PPC_RAW_EXTSW(dst_reg, src_reg)); 698 } else if (dst_reg != src_reg) 699 EMIT(PPC_RAW_MR(dst_reg, src_reg)); 700 goto bpf_alu32_trunc; 701 case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */ 702 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */ 703 PPC_LI32(dst_reg, imm); 704 if (imm < 0) 705 goto bpf_alu32_trunc; 706 else if (insn_is_zext(&insn[i + 1])) 707 addrs[++i] = ctx->idx * 4; 708 break; 709 710 bpf_alu32_trunc: 711 /* Truncate to 32-bits */ 712 if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext) 713 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31)); 714 break; 715 716 /* 717 * BPF_FROM_BE/LE 718 */ 719 case BPF_ALU | BPF_END | BPF_FROM_LE: 720 case BPF_ALU | BPF_END | BPF_FROM_BE: 721 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 722 #ifdef __BIG_ENDIAN__ 723 if (BPF_SRC(code) == BPF_FROM_BE) 724 goto emit_clear; 725 #else /* !__BIG_ENDIAN__ */ 726 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE) 727 goto emit_clear; 728 #endif 729 switch (imm) { 730 case 16: 731 /* Rotate 8 bits left & mask with 0x0000ff00 */ 732 EMIT(PPC_RAW_RLWINM(tmp1_reg, dst_reg, 8, 16, 23)); 733 /* Rotate 8 bits right & insert LSB to reg */ 734 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 24, 31)); 735 /* Move result back to dst_reg */ 736 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 737 break; 738 case 32: 739 /* 740 * Rotate word left by 8 bits: 741 * 2 bytes are already in their final position 742 * -- byte 2 and 4 (of bytes 1, 2, 3 and 4) 743 */ 744 EMIT(PPC_RAW_RLWINM(tmp1_reg, dst_reg, 8, 0, 31)); 745 /* Rotate 24 bits and insert byte 1 */ 746 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 0, 7)); 747 /* Rotate 24 bits and insert byte 3 */ 748 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 16, 23)); 749 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 750 break; 751 case 64: 752 /* Store the value to stack and then use byte-reverse loads */ 753 EMIT(PPC_RAW_STD(dst_reg, _R1, bpf_jit_stack_local(ctx))); 754 EMIT(PPC_RAW_ADDI(tmp1_reg, _R1, bpf_jit_stack_local(ctx))); 755 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 756 EMIT(PPC_RAW_LDBRX(dst_reg, 0, tmp1_reg)); 757 } else { 758 EMIT(PPC_RAW_LWBRX(dst_reg, 0, tmp1_reg)); 759 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 760 EMIT(PPC_RAW_SLDI(dst_reg, dst_reg, 32)); 761 EMIT(PPC_RAW_LI(tmp2_reg, 4)); 762 EMIT(PPC_RAW_LWBRX(tmp2_reg, tmp2_reg, tmp1_reg)); 763 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 764 EMIT(PPC_RAW_SLDI(tmp2_reg, tmp2_reg, 32)); 765 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp2_reg)); 766 } 767 break; 768 } 769 break; 770 771 emit_clear: 772 switch (imm) { 773 case 16: 774 /* zero-extend 16 bits into 64 bits */ 775 EMIT(PPC_RAW_RLDICL(dst_reg, dst_reg, 0, 48)); 776 if (insn_is_zext(&insn[i + 1])) 777 addrs[++i] = ctx->idx * 4; 778 break; 779 case 32: 780 if (!fp->aux->verifier_zext) 781 /* zero-extend 32 bits into 64 bits */ 782 EMIT(PPC_RAW_RLDICL(dst_reg, dst_reg, 0, 32)); 783 break; 784 case 64: 785 /* nop */ 786 break; 787 } 788 break; 789 790 /* 791 * BPF_ST NOSPEC (speculation barrier) 792 */ 793 case BPF_ST | BPF_NOSPEC: 794 if (!security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) || 795 !security_ftr_enabled(SEC_FTR_STF_BARRIER)) 796 break; 797 798 switch (stf_barrier) { 799 case STF_BARRIER_EIEIO: 800 EMIT(PPC_RAW_EIEIO() | 0x02000000); 801 break; 802 case STF_BARRIER_SYNC_ORI: 803 EMIT(PPC_RAW_SYNC()); 804 EMIT(PPC_RAW_LD(tmp1_reg, _R13, 0)); 805 EMIT(PPC_RAW_ORI(_R31, _R31, 0)); 806 break; 807 case STF_BARRIER_FALLBACK: 808 ctx->seen |= SEEN_FUNC; 809 PPC_LI64(_R12, dereference_kernel_function_descriptor(bpf_stf_barrier)); 810 EMIT(PPC_RAW_MTCTR(_R12)); 811 EMIT(PPC_RAW_BCTRL()); 812 break; 813 case STF_BARRIER_NONE: 814 break; 815 } 816 break; 817 818 /* 819 * BPF_ST(X) 820 */ 821 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src */ 822 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 823 if (BPF_CLASS(code) == BPF_ST) { 824 EMIT(PPC_RAW_LI(tmp1_reg, imm)); 825 src_reg = tmp1_reg; 826 } 827 EMIT(PPC_RAW_STB(src_reg, dst_reg, off)); 828 break; 829 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 830 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 831 if (BPF_CLASS(code) == BPF_ST) { 832 EMIT(PPC_RAW_LI(tmp1_reg, imm)); 833 src_reg = tmp1_reg; 834 } 835 EMIT(PPC_RAW_STH(src_reg, dst_reg, off)); 836 break; 837 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 838 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 839 if (BPF_CLASS(code) == BPF_ST) { 840 PPC_LI32(tmp1_reg, imm); 841 src_reg = tmp1_reg; 842 } 843 EMIT(PPC_RAW_STW(src_reg, dst_reg, off)); 844 break; 845 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 846 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 847 if (BPF_CLASS(code) == BPF_ST) { 848 PPC_LI32(tmp1_reg, imm); 849 src_reg = tmp1_reg; 850 } 851 if (off % 4) { 852 EMIT(PPC_RAW_LI(tmp2_reg, off)); 853 EMIT(PPC_RAW_STDX(src_reg, dst_reg, tmp2_reg)); 854 } else { 855 EMIT(PPC_RAW_STD(src_reg, dst_reg, off)); 856 } 857 break; 858 859 /* 860 * BPF_STX ATOMIC (atomic ops) 861 */ 862 case BPF_STX | BPF_ATOMIC | BPF_W: 863 case BPF_STX | BPF_ATOMIC | BPF_DW: 864 save_reg = tmp2_reg; 865 ret_reg = src_reg; 866 867 /* Get offset into TMP_REG_1 */ 868 EMIT(PPC_RAW_LI(tmp1_reg, off)); 869 /* 870 * Enforce full ordering for operations with BPF_FETCH by emitting a 'sync' 871 * before and after the operation. 872 * 873 * This is a requirement in the Linux Kernel Memory Model. 874 * See __cmpxchg_u64() in asm/cmpxchg.h as an example. 875 */ 876 if ((imm & BPF_FETCH) && IS_ENABLED(CONFIG_SMP)) 877 EMIT(PPC_RAW_SYNC()); 878 tmp_idx = ctx->idx * 4; 879 /* load value from memory into TMP_REG_2 */ 880 if (size == BPF_DW) 881 EMIT(PPC_RAW_LDARX(tmp2_reg, tmp1_reg, dst_reg, 0)); 882 else 883 EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg, 0)); 884 885 /* Save old value in _R0 */ 886 if (imm & BPF_FETCH) 887 EMIT(PPC_RAW_MR(_R0, tmp2_reg)); 888 889 switch (imm) { 890 case BPF_ADD: 891 case BPF_ADD | BPF_FETCH: 892 EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg)); 893 break; 894 case BPF_AND: 895 case BPF_AND | BPF_FETCH: 896 EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg)); 897 break; 898 case BPF_OR: 899 case BPF_OR | BPF_FETCH: 900 EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg)); 901 break; 902 case BPF_XOR: 903 case BPF_XOR | BPF_FETCH: 904 EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg)); 905 break; 906 case BPF_CMPXCHG: 907 /* 908 * Return old value in BPF_REG_0 for BPF_CMPXCHG & 909 * in src_reg for other cases. 910 */ 911 ret_reg = bpf_to_ppc(BPF_REG_0); 912 913 /* Compare with old value in BPF_R0 */ 914 if (size == BPF_DW) 915 EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg)); 916 else 917 EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg)); 918 /* Don't set if different from old value */ 919 PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); 920 fallthrough; 921 case BPF_XCHG: 922 save_reg = src_reg; 923 break; 924 default: 925 pr_err_ratelimited( 926 "eBPF filter atomic op code %02x (@%d) unsupported\n", 927 code, i); 928 return -EOPNOTSUPP; 929 } 930 931 /* store new value */ 932 if (size == BPF_DW) 933 EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg, dst_reg)); 934 else 935 EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg, dst_reg)); 936 /* we're done if this succeeded */ 937 PPC_BCC_SHORT(COND_NE, tmp_idx); 938 939 if (imm & BPF_FETCH) { 940 /* Emit 'sync' to enforce full ordering */ 941 if (IS_ENABLED(CONFIG_SMP)) 942 EMIT(PPC_RAW_SYNC()); 943 EMIT(PPC_RAW_MR(ret_reg, _R0)); 944 /* 945 * Skip unnecessary zero-extension for 32-bit cmpxchg. 946 * For context, see commit 39491867ace5. 947 */ 948 if (size != BPF_DW && imm == BPF_CMPXCHG && 949 insn_is_zext(&insn[i + 1])) 950 addrs[++i] = ctx->idx * 4; 951 } 952 break; 953 954 /* 955 * BPF_LDX 956 */ 957 /* dst = *(u8 *)(ul) (src + off) */ 958 case BPF_LDX | BPF_MEM | BPF_B: 959 case BPF_LDX | BPF_MEMSX | BPF_B: 960 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 961 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 962 /* dst = *(u16 *)(ul) (src + off) */ 963 case BPF_LDX | BPF_MEM | BPF_H: 964 case BPF_LDX | BPF_MEMSX | BPF_H: 965 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 966 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 967 /* dst = *(u32 *)(ul) (src + off) */ 968 case BPF_LDX | BPF_MEM | BPF_W: 969 case BPF_LDX | BPF_MEMSX | BPF_W: 970 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 971 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 972 /* dst = *(u64 *)(ul) (src + off) */ 973 case BPF_LDX | BPF_MEM | BPF_DW: 974 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 975 /* 976 * As PTR_TO_BTF_ID that uses BPF_PROBE_MEM mode could either be a valid 977 * kernel pointer or NULL but not a userspace address, execute BPF_PROBE_MEM 978 * load only if addr is kernel address (see is_kernel_addr()), otherwise 979 * set dst_reg=0 and move on. 980 */ 981 if (BPF_MODE(code) == BPF_PROBE_MEM || BPF_MODE(code) == BPF_PROBE_MEMSX) { 982 EMIT(PPC_RAW_ADDI(tmp1_reg, src_reg, off)); 983 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) 984 PPC_LI64(tmp2_reg, 0x8000000000000000ul); 985 else /* BOOK3S_64 */ 986 PPC_LI64(tmp2_reg, PAGE_OFFSET); 987 EMIT(PPC_RAW_CMPLD(tmp1_reg, tmp2_reg)); 988 PPC_BCC_SHORT(COND_GT, (ctx->idx + 3) * 4); 989 EMIT(PPC_RAW_LI(dst_reg, 0)); 990 /* 991 * Check if 'off' is word aligned for BPF_DW, because 992 * we might generate two instructions. 993 */ 994 if ((BPF_SIZE(code) == BPF_DW || 995 (BPF_SIZE(code) == BPF_B && BPF_MODE(code) == BPF_PROBE_MEMSX)) && 996 (off & 3)) 997 PPC_JMP((ctx->idx + 3) * 4); 998 else 999 PPC_JMP((ctx->idx + 2) * 4); 1000 } 1001 1002 if (BPF_MODE(code) == BPF_MEMSX || BPF_MODE(code) == BPF_PROBE_MEMSX) { 1003 switch (size) { 1004 case BPF_B: 1005 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 1006 EMIT(PPC_RAW_EXTSB(dst_reg, dst_reg)); 1007 break; 1008 case BPF_H: 1009 EMIT(PPC_RAW_LHA(dst_reg, src_reg, off)); 1010 break; 1011 case BPF_W: 1012 EMIT(PPC_RAW_LWA(dst_reg, src_reg, off)); 1013 break; 1014 } 1015 } else { 1016 switch (size) { 1017 case BPF_B: 1018 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 1019 break; 1020 case BPF_H: 1021 EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off)); 1022 break; 1023 case BPF_W: 1024 EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off)); 1025 break; 1026 case BPF_DW: 1027 if (off % 4) { 1028 EMIT(PPC_RAW_LI(tmp1_reg, off)); 1029 EMIT(PPC_RAW_LDX(dst_reg, src_reg, tmp1_reg)); 1030 } else { 1031 EMIT(PPC_RAW_LD(dst_reg, src_reg, off)); 1032 } 1033 break; 1034 } 1035 } 1036 1037 if (size != BPF_DW && insn_is_zext(&insn[i + 1])) 1038 addrs[++i] = ctx->idx * 4; 1039 1040 if (BPF_MODE(code) == BPF_PROBE_MEM) { 1041 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1042 ctx->idx - 1, 4, dst_reg); 1043 if (ret) 1044 return ret; 1045 } 1046 break; 1047 1048 /* 1049 * Doubleword load 1050 * 16 byte instruction that uses two 'struct bpf_insn' 1051 */ 1052 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 1053 imm64 = ((u64)(u32) insn[i].imm) | 1054 (((u64)(u32) insn[i+1].imm) << 32); 1055 PPC_LI64(dst_reg, imm64); 1056 /* Adjust for two bpf instructions */ 1057 addrs[++i] = ctx->idx * 4; 1058 break; 1059 1060 /* 1061 * Return/Exit 1062 */ 1063 case BPF_JMP | BPF_EXIT: 1064 /* 1065 * If this isn't the very last instruction, branch to 1066 * the epilogue. If we _are_ the last instruction, 1067 * we'll just fall through to the epilogue. 1068 */ 1069 if (i != flen - 1) { 1070 ret = bpf_jit_emit_exit_insn(image, ctx, tmp1_reg, exit_addr); 1071 if (ret) 1072 return ret; 1073 } 1074 /* else fall through to the epilogue */ 1075 break; 1076 1077 /* 1078 * Call kernel helper or bpf function 1079 */ 1080 case BPF_JMP | BPF_CALL: 1081 ctx->seen |= SEEN_FUNC; 1082 1083 ret = bpf_jit_get_func_addr(fp, &insn[i], extra_pass, 1084 &func_addr, &func_addr_fixed); 1085 if (ret < 0) 1086 return ret; 1087 1088 ret = bpf_jit_emit_func_call_rel(image, fimage, ctx, func_addr); 1089 if (ret) 1090 return ret; 1091 1092 /* move return value from r3 to BPF_REG_0 */ 1093 EMIT(PPC_RAW_MR(bpf_to_ppc(BPF_REG_0), _R3)); 1094 break; 1095 1096 /* 1097 * Jumps and branches 1098 */ 1099 case BPF_JMP | BPF_JA: 1100 PPC_JMP(addrs[i + 1 + off]); 1101 break; 1102 case BPF_JMP32 | BPF_JA: 1103 PPC_JMP(addrs[i + 1 + imm]); 1104 break; 1105 1106 case BPF_JMP | BPF_JGT | BPF_K: 1107 case BPF_JMP | BPF_JGT | BPF_X: 1108 case BPF_JMP | BPF_JSGT | BPF_K: 1109 case BPF_JMP | BPF_JSGT | BPF_X: 1110 case BPF_JMP32 | BPF_JGT | BPF_K: 1111 case BPF_JMP32 | BPF_JGT | BPF_X: 1112 case BPF_JMP32 | BPF_JSGT | BPF_K: 1113 case BPF_JMP32 | BPF_JSGT | BPF_X: 1114 true_cond = COND_GT; 1115 goto cond_branch; 1116 case BPF_JMP | BPF_JLT | BPF_K: 1117 case BPF_JMP | BPF_JLT | BPF_X: 1118 case BPF_JMP | BPF_JSLT | BPF_K: 1119 case BPF_JMP | BPF_JSLT | BPF_X: 1120 case BPF_JMP32 | BPF_JLT | BPF_K: 1121 case BPF_JMP32 | BPF_JLT | BPF_X: 1122 case BPF_JMP32 | BPF_JSLT | BPF_K: 1123 case BPF_JMP32 | BPF_JSLT | BPF_X: 1124 true_cond = COND_LT; 1125 goto cond_branch; 1126 case BPF_JMP | BPF_JGE | BPF_K: 1127 case BPF_JMP | BPF_JGE | BPF_X: 1128 case BPF_JMP | BPF_JSGE | BPF_K: 1129 case BPF_JMP | BPF_JSGE | BPF_X: 1130 case BPF_JMP32 | BPF_JGE | BPF_K: 1131 case BPF_JMP32 | BPF_JGE | BPF_X: 1132 case BPF_JMP32 | BPF_JSGE | BPF_K: 1133 case BPF_JMP32 | BPF_JSGE | BPF_X: 1134 true_cond = COND_GE; 1135 goto cond_branch; 1136 case BPF_JMP | BPF_JLE | BPF_K: 1137 case BPF_JMP | BPF_JLE | BPF_X: 1138 case BPF_JMP | BPF_JSLE | BPF_K: 1139 case BPF_JMP | BPF_JSLE | BPF_X: 1140 case BPF_JMP32 | BPF_JLE | BPF_K: 1141 case BPF_JMP32 | BPF_JLE | BPF_X: 1142 case BPF_JMP32 | BPF_JSLE | BPF_K: 1143 case BPF_JMP32 | BPF_JSLE | BPF_X: 1144 true_cond = COND_LE; 1145 goto cond_branch; 1146 case BPF_JMP | BPF_JEQ | BPF_K: 1147 case BPF_JMP | BPF_JEQ | BPF_X: 1148 case BPF_JMP32 | BPF_JEQ | BPF_K: 1149 case BPF_JMP32 | BPF_JEQ | BPF_X: 1150 true_cond = COND_EQ; 1151 goto cond_branch; 1152 case BPF_JMP | BPF_JNE | BPF_K: 1153 case BPF_JMP | BPF_JNE | BPF_X: 1154 case BPF_JMP32 | BPF_JNE | BPF_K: 1155 case BPF_JMP32 | BPF_JNE | BPF_X: 1156 true_cond = COND_NE; 1157 goto cond_branch; 1158 case BPF_JMP | BPF_JSET | BPF_K: 1159 case BPF_JMP | BPF_JSET | BPF_X: 1160 case BPF_JMP32 | BPF_JSET | BPF_K: 1161 case BPF_JMP32 | BPF_JSET | BPF_X: 1162 true_cond = COND_NE; 1163 /* Fall through */ 1164 1165 cond_branch: 1166 switch (code) { 1167 case BPF_JMP | BPF_JGT | BPF_X: 1168 case BPF_JMP | BPF_JLT | BPF_X: 1169 case BPF_JMP | BPF_JGE | BPF_X: 1170 case BPF_JMP | BPF_JLE | BPF_X: 1171 case BPF_JMP | BPF_JEQ | BPF_X: 1172 case BPF_JMP | BPF_JNE | BPF_X: 1173 case BPF_JMP32 | BPF_JGT | BPF_X: 1174 case BPF_JMP32 | BPF_JLT | BPF_X: 1175 case BPF_JMP32 | BPF_JGE | BPF_X: 1176 case BPF_JMP32 | BPF_JLE | BPF_X: 1177 case BPF_JMP32 | BPF_JEQ | BPF_X: 1178 case BPF_JMP32 | BPF_JNE | BPF_X: 1179 /* unsigned comparison */ 1180 if (BPF_CLASS(code) == BPF_JMP32) 1181 EMIT(PPC_RAW_CMPLW(dst_reg, src_reg)); 1182 else 1183 EMIT(PPC_RAW_CMPLD(dst_reg, src_reg)); 1184 break; 1185 case BPF_JMP | BPF_JSGT | BPF_X: 1186 case BPF_JMP | BPF_JSLT | BPF_X: 1187 case BPF_JMP | BPF_JSGE | BPF_X: 1188 case BPF_JMP | BPF_JSLE | BPF_X: 1189 case BPF_JMP32 | BPF_JSGT | BPF_X: 1190 case BPF_JMP32 | BPF_JSLT | BPF_X: 1191 case BPF_JMP32 | BPF_JSGE | BPF_X: 1192 case BPF_JMP32 | BPF_JSLE | BPF_X: 1193 /* signed comparison */ 1194 if (BPF_CLASS(code) == BPF_JMP32) 1195 EMIT(PPC_RAW_CMPW(dst_reg, src_reg)); 1196 else 1197 EMIT(PPC_RAW_CMPD(dst_reg, src_reg)); 1198 break; 1199 case BPF_JMP | BPF_JSET | BPF_X: 1200 case BPF_JMP32 | BPF_JSET | BPF_X: 1201 if (BPF_CLASS(code) == BPF_JMP) { 1202 EMIT(PPC_RAW_AND_DOT(tmp1_reg, dst_reg, src_reg)); 1203 } else { 1204 EMIT(PPC_RAW_AND(tmp1_reg, dst_reg, src_reg)); 1205 EMIT(PPC_RAW_RLWINM_DOT(tmp1_reg, tmp1_reg, 0, 0, 31)); 1206 } 1207 break; 1208 case BPF_JMP | BPF_JNE | BPF_K: 1209 case BPF_JMP | BPF_JEQ | BPF_K: 1210 case BPF_JMP | BPF_JGT | BPF_K: 1211 case BPF_JMP | BPF_JLT | BPF_K: 1212 case BPF_JMP | BPF_JGE | BPF_K: 1213 case BPF_JMP | BPF_JLE | BPF_K: 1214 case BPF_JMP32 | BPF_JNE | BPF_K: 1215 case BPF_JMP32 | BPF_JEQ | BPF_K: 1216 case BPF_JMP32 | BPF_JGT | BPF_K: 1217 case BPF_JMP32 | BPF_JLT | BPF_K: 1218 case BPF_JMP32 | BPF_JGE | BPF_K: 1219 case BPF_JMP32 | BPF_JLE | BPF_K: 1220 { 1221 bool is_jmp32 = BPF_CLASS(code) == BPF_JMP32; 1222 1223 /* 1224 * Need sign-extended load, so only positive 1225 * values can be used as imm in cmpldi 1226 */ 1227 if (imm >= 0 && imm < 32768) { 1228 if (is_jmp32) 1229 EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); 1230 else 1231 EMIT(PPC_RAW_CMPLDI(dst_reg, imm)); 1232 } else { 1233 /* sign-extending load */ 1234 PPC_LI32(tmp1_reg, imm); 1235 /* ... but unsigned comparison */ 1236 if (is_jmp32) 1237 EMIT(PPC_RAW_CMPLW(dst_reg, tmp1_reg)); 1238 else 1239 EMIT(PPC_RAW_CMPLD(dst_reg, tmp1_reg)); 1240 } 1241 break; 1242 } 1243 case BPF_JMP | BPF_JSGT | BPF_K: 1244 case BPF_JMP | BPF_JSLT | BPF_K: 1245 case BPF_JMP | BPF_JSGE | BPF_K: 1246 case BPF_JMP | BPF_JSLE | BPF_K: 1247 case BPF_JMP32 | BPF_JSGT | BPF_K: 1248 case BPF_JMP32 | BPF_JSLT | BPF_K: 1249 case BPF_JMP32 | BPF_JSGE | BPF_K: 1250 case BPF_JMP32 | BPF_JSLE | BPF_K: 1251 { 1252 bool is_jmp32 = BPF_CLASS(code) == BPF_JMP32; 1253 1254 /* 1255 * signed comparison, so any 16-bit value 1256 * can be used in cmpdi 1257 */ 1258 if (imm >= -32768 && imm < 32768) { 1259 if (is_jmp32) 1260 EMIT(PPC_RAW_CMPWI(dst_reg, imm)); 1261 else 1262 EMIT(PPC_RAW_CMPDI(dst_reg, imm)); 1263 } else { 1264 PPC_LI32(tmp1_reg, imm); 1265 if (is_jmp32) 1266 EMIT(PPC_RAW_CMPW(dst_reg, tmp1_reg)); 1267 else 1268 EMIT(PPC_RAW_CMPD(dst_reg, tmp1_reg)); 1269 } 1270 break; 1271 } 1272 case BPF_JMP | BPF_JSET | BPF_K: 1273 case BPF_JMP32 | BPF_JSET | BPF_K: 1274 /* andi does not sign-extend the immediate */ 1275 if (imm >= 0 && imm < 32768) 1276 /* PPC_ANDI is _only/always_ dot-form */ 1277 EMIT(PPC_RAW_ANDI(tmp1_reg, dst_reg, imm)); 1278 else { 1279 PPC_LI32(tmp1_reg, imm); 1280 if (BPF_CLASS(code) == BPF_JMP) { 1281 EMIT(PPC_RAW_AND_DOT(tmp1_reg, dst_reg, 1282 tmp1_reg)); 1283 } else { 1284 EMIT(PPC_RAW_AND(tmp1_reg, dst_reg, tmp1_reg)); 1285 EMIT(PPC_RAW_RLWINM_DOT(tmp1_reg, tmp1_reg, 1286 0, 0, 31)); 1287 } 1288 } 1289 break; 1290 } 1291 PPC_BCC(true_cond, addrs[i + 1 + off]); 1292 break; 1293 1294 /* 1295 * Tail call 1296 */ 1297 case BPF_JMP | BPF_TAIL_CALL: 1298 ctx->seen |= SEEN_TAILCALL; 1299 ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]); 1300 if (ret < 0) 1301 return ret; 1302 break; 1303 1304 default: 1305 /* 1306 * The filter contains something cruel & unusual. 1307 * We don't handle it, but also there shouldn't be 1308 * anything missing from our list. 1309 */ 1310 pr_err_ratelimited("eBPF filter opcode %04x (@%d) unsupported\n", 1311 code, i); 1312 return -ENOTSUPP; 1313 } 1314 } 1315 1316 /* Set end-of-body-code address for exit. */ 1317 addrs[i] = ctx->idx * 4; 1318 1319 return 0; 1320 } 1321