1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * bpf_jit_comp64.c: eBPF JIT compiler 4 * 5 * Copyright 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 6 * IBM Corporation 7 * 8 * Based on the powerpc classic BPF JIT compiler by Matt Evans 9 */ 10 #include <linux/moduleloader.h> 11 #include <asm/cacheflush.h> 12 #include <asm/asm-compat.h> 13 #include <linux/netdevice.h> 14 #include <linux/filter.h> 15 #include <linux/if_vlan.h> 16 #include <asm/kprobes.h> 17 #include <linux/bpf.h> 18 #include <asm/security_features.h> 19 20 #include "bpf_jit.h" 21 22 /* 23 * Stack layout: 24 * Ensure the top half (upto local_tmp_var) stays consistent 25 * with our redzone usage. 26 * 27 * [ prev sp ] <------------- 28 * [ nv gpr save area ] 5*8 | 29 * [ tail_call_cnt ] 8 | 30 * [ local_tmp_var ] 16 | 31 * fp (r31) --> [ ebpf stack space ] upto 512 | 32 * [ frame header ] 32/112 | 33 * sp (r1) ---> [ stack pointer ] -------------- 34 */ 35 36 /* for gpr non volatile registers BPG_REG_6 to 10 */ 37 #define BPF_PPC_STACK_SAVE (5*8) 38 /* for bpf JIT code internal usage */ 39 #define BPF_PPC_STACK_LOCALS 24 40 /* stack frame excluding BPF stack, ensure this is quadword aligned */ 41 #define BPF_PPC_STACKFRAME (STACK_FRAME_MIN_SIZE + \ 42 BPF_PPC_STACK_LOCALS + BPF_PPC_STACK_SAVE) 43 44 /* BPF register usage */ 45 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 46 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 47 48 /* BPF to ppc register mappings */ 49 void bpf_jit_init_reg_mapping(struct codegen_context *ctx) 50 { 51 /* function return value */ 52 ctx->b2p[BPF_REG_0] = _R8; 53 /* function arguments */ 54 ctx->b2p[BPF_REG_1] = _R3; 55 ctx->b2p[BPF_REG_2] = _R4; 56 ctx->b2p[BPF_REG_3] = _R5; 57 ctx->b2p[BPF_REG_4] = _R6; 58 ctx->b2p[BPF_REG_5] = _R7; 59 /* non volatile registers */ 60 ctx->b2p[BPF_REG_6] = _R27; 61 ctx->b2p[BPF_REG_7] = _R28; 62 ctx->b2p[BPF_REG_8] = _R29; 63 ctx->b2p[BPF_REG_9] = _R30; 64 /* frame pointer aka BPF_REG_10 */ 65 ctx->b2p[BPF_REG_FP] = _R31; 66 /* eBPF jit internal registers */ 67 ctx->b2p[BPF_REG_AX] = _R12; 68 ctx->b2p[TMP_REG_1] = _R9; 69 ctx->b2p[TMP_REG_2] = _R10; 70 } 71 72 /* PPC NVR range -- update this if we ever use NVRs below r27 */ 73 #define BPF_PPC_NVR_MIN _R27 74 75 static inline bool bpf_has_stack_frame(struct codegen_context *ctx) 76 { 77 /* 78 * We only need a stack frame if: 79 * - we call other functions (kernel helpers), or 80 * - the bpf program uses its stack area 81 * The latter condition is deduced from the usage of BPF_REG_FP 82 */ 83 return ctx->seen & SEEN_FUNC || bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP)); 84 } 85 86 /* 87 * When not setting up our own stackframe, the redzone (288 bytes) usage is: 88 * 89 * [ prev sp ] <------------- 90 * [ ... ] | 91 * sp (r1) ---> [ stack pointer ] -------------- 92 * [ nv gpr save area ] 5*8 93 * [ tail_call_cnt ] 8 94 * [ local_tmp_var ] 16 95 * [ unused red zone ] 224 96 */ 97 static int bpf_jit_stack_local(struct codegen_context *ctx) 98 { 99 if (bpf_has_stack_frame(ctx)) 100 return STACK_FRAME_MIN_SIZE + ctx->stack_size; 101 else 102 return -(BPF_PPC_STACK_SAVE + 24); 103 } 104 105 static int bpf_jit_stack_tailcallcnt(struct codegen_context *ctx) 106 { 107 return bpf_jit_stack_local(ctx) + 16; 108 } 109 110 static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg) 111 { 112 if (reg >= BPF_PPC_NVR_MIN && reg < 32) 113 return (bpf_has_stack_frame(ctx) ? 114 (BPF_PPC_STACKFRAME + ctx->stack_size) : 0) 115 - (8 * (32 - reg)); 116 117 pr_err("BPF JIT is asking about unknown registers"); 118 BUG(); 119 } 120 121 void bpf_jit_realloc_regs(struct codegen_context *ctx) 122 { 123 } 124 125 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) 126 { 127 int i; 128 129 /* Instruction for trampoline attach */ 130 EMIT(PPC_RAW_NOP()); 131 132 #ifndef CONFIG_PPC_KERNEL_PCREL 133 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2)) 134 EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc))); 135 #endif 136 137 /* 138 * Initialize tail_call_cnt if we do tail calls. 139 * Otherwise, put in NOPs so that it can be skipped when we are 140 * invoked through a tail call. 141 */ 142 if (ctx->seen & SEEN_TAILCALL) { 143 EMIT(PPC_RAW_LI(bpf_to_ppc(TMP_REG_1), 0)); 144 /* this goes in the redzone */ 145 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, -(BPF_PPC_STACK_SAVE + 8))); 146 } else { 147 EMIT(PPC_RAW_NOP()); 148 EMIT(PPC_RAW_NOP()); 149 } 150 151 if (bpf_has_stack_frame(ctx)) { 152 /* 153 * We need a stack frame, but we don't necessarily need to 154 * save/restore LR unless we call other functions 155 */ 156 if (ctx->seen & SEEN_FUNC) { 157 EMIT(PPC_RAW_MFLR(_R0)); 158 EMIT(PPC_RAW_STD(_R0, _R1, PPC_LR_STKOFF)); 159 } 160 161 EMIT(PPC_RAW_STDU(_R1, _R1, -(BPF_PPC_STACKFRAME + ctx->stack_size))); 162 } 163 164 /* 165 * Back up non-volatile regs -- BPF registers 6-10 166 * If we haven't created our own stack frame, we save these 167 * in the protected zone below the previous stack frame 168 */ 169 for (i = BPF_REG_6; i <= BPF_REG_10; i++) 170 if (bpf_is_seen_register(ctx, bpf_to_ppc(i))) 171 EMIT(PPC_RAW_STD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to_ppc(i)))); 172 173 /* Setup frame pointer to point to the bpf stack area */ 174 if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) 175 EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1, 176 STACK_FRAME_MIN_SIZE + ctx->stack_size)); 177 } 178 179 static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx) 180 { 181 int i; 182 183 /* Restore NVRs */ 184 for (i = BPF_REG_6; i <= BPF_REG_10; i++) 185 if (bpf_is_seen_register(ctx, bpf_to_ppc(i))) 186 EMIT(PPC_RAW_LD(bpf_to_ppc(i), _R1, bpf_jit_stack_offsetof(ctx, bpf_to_ppc(i)))); 187 188 /* Tear down our stack frame */ 189 if (bpf_has_stack_frame(ctx)) { 190 EMIT(PPC_RAW_ADDI(_R1, _R1, BPF_PPC_STACKFRAME + ctx->stack_size)); 191 if (ctx->seen & SEEN_FUNC) { 192 EMIT(PPC_RAW_LD(_R0, _R1, PPC_LR_STKOFF)); 193 EMIT(PPC_RAW_MTLR(_R0)); 194 } 195 } 196 } 197 198 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) 199 { 200 bpf_jit_emit_common_epilogue(image, ctx); 201 202 /* Move result to r3 */ 203 EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(BPF_REG_0))); 204 205 EMIT(PPC_RAW_BLR()); 206 207 bpf_jit_build_fentry_stubs(image, ctx); 208 } 209 210 int bpf_jit_emit_func_call_rel(u32 *image, u32 *fimage, struct codegen_context *ctx, u64 func) 211 { 212 unsigned long func_addr = func ? ppc_function_entry((void *)func) : 0; 213 long reladdr; 214 215 /* bpf to bpf call, func is not known in the initial pass. Emit 5 nops as a placeholder */ 216 if (!func) { 217 for (int i = 0; i < 5; i++) 218 EMIT(PPC_RAW_NOP()); 219 /* elfv1 needs an additional instruction to load addr from descriptor */ 220 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) 221 EMIT(PPC_RAW_NOP()); 222 EMIT(PPC_RAW_MTCTR(_R12)); 223 EMIT(PPC_RAW_BCTRL()); 224 return 0; 225 } 226 227 #ifdef CONFIG_PPC_KERNEL_PCREL 228 reladdr = func_addr - local_paca->kernelbase; 229 230 /* 231 * If fimage is NULL (the initial pass to find image size), 232 * account for the maximum no. of instructions possible. 233 */ 234 if (!fimage) { 235 ctx->idx += 7; 236 return 0; 237 } else if (reladdr < (long)SZ_8G && reladdr >= -(long)SZ_8G) { 238 EMIT(PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernelbase))); 239 /* Align for subsequent prefix instruction */ 240 if (!IS_ALIGNED((unsigned long)fimage + CTX_NIA(ctx), 8)) 241 EMIT(PPC_RAW_NOP()); 242 /* paddi r12,r12,addr */ 243 EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(0) | IMM_H18(reladdr)); 244 EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | ___PPC_RA(_R12) | IMM_L(reladdr)); 245 } else { 246 unsigned long pc = (unsigned long)fimage + CTX_NIA(ctx); 247 bool alignment_needed = !IS_ALIGNED(pc, 8); 248 249 reladdr = func_addr - (alignment_needed ? pc + 4 : pc); 250 251 if (reladdr < (long)SZ_8G && reladdr >= -(long)SZ_8G) { 252 if (alignment_needed) 253 EMIT(PPC_RAW_NOP()); 254 /* pla r12,addr */ 255 EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(1) | IMM_H18(reladdr)); 256 EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | IMM_L(reladdr)); 257 } else { 258 /* We can clobber r12 */ 259 PPC_LI64(_R12, func); 260 } 261 } 262 EMIT(PPC_RAW_MTCTR(_R12)); 263 EMIT(PPC_RAW_BCTRL()); 264 #else 265 if (core_kernel_text(func_addr)) { 266 reladdr = func_addr - kernel_toc_addr(); 267 if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) { 268 pr_err("eBPF: address of %ps out of range of kernel_toc.\n", (void *)func); 269 return -ERANGE; 270 } 271 272 EMIT(PPC_RAW_ADDIS(_R12, _R2, PPC_HA(reladdr))); 273 EMIT(PPC_RAW_ADDI(_R12, _R12, PPC_LO(reladdr))); 274 EMIT(PPC_RAW_MTCTR(_R12)); 275 EMIT(PPC_RAW_BCTRL()); 276 } else { 277 if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V1)) { 278 /* func points to the function descriptor */ 279 PPC_LI64(bpf_to_ppc(TMP_REG_2), func); 280 /* Load actual entry point from function descriptor */ 281 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), 0)); 282 /* ... and move it to CTR */ 283 EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_1))); 284 /* 285 * Load TOC from function descriptor at offset 8. 286 * We can clobber r2 since we get called through a 287 * function pointer (so caller will save/restore r2). 288 */ 289 if (is_module_text_address(func_addr)) 290 EMIT(PPC_RAW_LD(_R2, bpf_to_ppc(TMP_REG_2), 8)); 291 } else { 292 PPC_LI64(_R12, func); 293 EMIT(PPC_RAW_MTCTR(_R12)); 294 } 295 EMIT(PPC_RAW_BCTRL()); 296 /* 297 * Load r2 with kernel TOC as kernel TOC is used if function address falls 298 * within core kernel text. 299 */ 300 if (is_module_text_address(func_addr)) 301 EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc))); 302 } 303 #endif 304 305 return 0; 306 } 307 308 static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out) 309 { 310 /* 311 * By now, the eBPF program has already setup parameters in r3, r4 and r5 312 * r3/BPF_REG_1 - pointer to ctx -- passed as is to the next bpf program 313 * r4/BPF_REG_2 - pointer to bpf_array 314 * r5/BPF_REG_3 - index in bpf_array 315 */ 316 int b2p_bpf_array = bpf_to_ppc(BPF_REG_2); 317 int b2p_index = bpf_to_ppc(BPF_REG_3); 318 int bpf_tailcall_prologue_size = 12; 319 320 if (!IS_ENABLED(CONFIG_PPC_KERNEL_PCREL) && IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2)) 321 bpf_tailcall_prologue_size += 4; /* skip past the toc load */ 322 323 /* 324 * if (index >= array->map.max_entries) 325 * goto out; 326 */ 327 EMIT(PPC_RAW_LWZ(bpf_to_ppc(TMP_REG_1), b2p_bpf_array, offsetof(struct bpf_array, map.max_entries))); 328 EMIT(PPC_RAW_RLWINM(b2p_index, b2p_index, 0, 0, 31)); 329 EMIT(PPC_RAW_CMPLW(b2p_index, bpf_to_ppc(TMP_REG_1))); 330 PPC_BCC_SHORT(COND_GE, out); 331 332 /* 333 * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) 334 * goto out; 335 */ 336 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), _R1, bpf_jit_stack_tailcallcnt(ctx))); 337 EMIT(PPC_RAW_CMPLWI(bpf_to_ppc(TMP_REG_1), MAX_TAIL_CALL_CNT)); 338 PPC_BCC_SHORT(COND_GE, out); 339 340 /* 341 * tail_call_cnt++; 342 */ 343 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 1)); 344 EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), _R1, bpf_jit_stack_tailcallcnt(ctx))); 345 346 /* prog = array->ptrs[index]; */ 347 EMIT(PPC_RAW_MULI(bpf_to_ppc(TMP_REG_1), b2p_index, 8)); 348 EMIT(PPC_RAW_ADD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), b2p_bpf_array)); 349 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), offsetof(struct bpf_array, ptrs))); 350 351 /* 352 * if (prog == NULL) 353 * goto out; 354 */ 355 EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_1), 0)); 356 PPC_BCC_SHORT(COND_EQ, out); 357 358 /* goto *(prog->bpf_func + prologue_size); */ 359 EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), offsetof(struct bpf_prog, bpf_func))); 360 EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 361 FUNCTION_DESCR_SIZE + bpf_tailcall_prologue_size)); 362 EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_1))); 363 364 /* tear down stack, restore NVRs, ... */ 365 bpf_jit_emit_common_epilogue(image, ctx); 366 367 EMIT(PPC_RAW_BCTR()); 368 369 /* out: */ 370 return 0; 371 } 372 373 bool bpf_jit_bypass_spec_v1(void) 374 { 375 #if defined(CONFIG_PPC_E500) || defined(CONFIG_PPC_BOOK3S_64) 376 return !(security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 377 security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR)); 378 #else 379 return true; 380 #endif 381 } 382 383 bool bpf_jit_bypass_spec_v4(void) 384 { 385 return !(security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 386 security_ftr_enabled(SEC_FTR_STF_BARRIER) && 387 stf_barrier_type_get() != STF_BARRIER_NONE); 388 } 389 390 /* 391 * We spill into the redzone always, even if the bpf program has its own stackframe. 392 * Offsets hardcoded based on BPF_PPC_STACK_SAVE -- see bpf_jit_stack_local() 393 */ 394 void bpf_stf_barrier(void); 395 396 asm ( 397 " .global bpf_stf_barrier ;" 398 " bpf_stf_barrier: ;" 399 " std 21,-64(1) ;" 400 " std 22,-56(1) ;" 401 " sync ;" 402 " ld 21,-64(1) ;" 403 " ld 22,-56(1) ;" 404 " ori 31,31,0 ;" 405 " .rept 14 ;" 406 " b 1f ;" 407 " 1: ;" 408 " .endr ;" 409 " blr ;" 410 ); 411 412 /* Assemble the body code between the prologue & epilogue */ 413 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct codegen_context *ctx, 414 u32 *addrs, int pass, bool extra_pass) 415 { 416 enum stf_barrier_type stf_barrier = stf_barrier_type_get(); 417 bool sync_emitted, ori31_emitted; 418 const struct bpf_insn *insn = fp->insnsi; 419 int flen = fp->len; 420 int i, ret; 421 422 /* Start of epilogue code - will only be valid 2nd pass onwards */ 423 u32 exit_addr = addrs[flen]; 424 425 for (i = 0; i < flen; i++) { 426 u32 code = insn[i].code; 427 u32 dst_reg = bpf_to_ppc(insn[i].dst_reg); 428 u32 src_reg = bpf_to_ppc(insn[i].src_reg); 429 u32 size = BPF_SIZE(code); 430 u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); 431 u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); 432 u32 save_reg, ret_reg; 433 s16 off = insn[i].off; 434 s32 imm = insn[i].imm; 435 bool func_addr_fixed; 436 u64 func_addr; 437 u64 imm64; 438 u32 true_cond; 439 u32 tmp_idx; 440 441 /* 442 * addrs[] maps a BPF bytecode address into a real offset from 443 * the start of the body code. 444 */ 445 addrs[i] = ctx->idx * 4; 446 447 /* 448 * As an optimization, we note down which non-volatile registers 449 * are used so that we can only save/restore those in our 450 * prologue and epilogue. We do this here regardless of whether 451 * the actual BPF instruction uses src/dst registers or not 452 * (for instance, BPF_CALL does not use them). The expectation 453 * is that those instructions will have src_reg/dst_reg set to 454 * 0. Even otherwise, we just lose some prologue/epilogue 455 * optimization but everything else should work without 456 * any issues. 457 */ 458 if (dst_reg >= BPF_PPC_NVR_MIN && dst_reg < 32) 459 bpf_set_seen_register(ctx, dst_reg); 460 if (src_reg >= BPF_PPC_NVR_MIN && src_reg < 32) 461 bpf_set_seen_register(ctx, src_reg); 462 463 switch (code) { 464 /* 465 * Arithmetic operations: ADD/SUB/MUL/DIV/MOD/NEG 466 */ 467 case BPF_ALU | BPF_ADD | BPF_X: /* (u32) dst += (u32) src */ 468 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst += src */ 469 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, src_reg)); 470 goto bpf_alu32_trunc; 471 case BPF_ALU | BPF_SUB | BPF_X: /* (u32) dst -= (u32) src */ 472 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst -= src */ 473 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, src_reg)); 474 goto bpf_alu32_trunc; 475 case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */ 476 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */ 477 if (!imm) { 478 goto bpf_alu32_trunc; 479 } else if (imm >= -32768 && imm < 32768) { 480 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm))); 481 } else { 482 PPC_LI32(tmp1_reg, imm); 483 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, tmp1_reg)); 484 } 485 goto bpf_alu32_trunc; 486 case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */ 487 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */ 488 if (!imm) { 489 goto bpf_alu32_trunc; 490 } else if (imm > -32768 && imm <= 32768) { 491 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(-imm))); 492 } else { 493 PPC_LI32(tmp1_reg, imm); 494 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 495 } 496 goto bpf_alu32_trunc; 497 case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */ 498 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */ 499 if (BPF_CLASS(code) == BPF_ALU) 500 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg)); 501 else 502 EMIT(PPC_RAW_MULD(dst_reg, dst_reg, src_reg)); 503 goto bpf_alu32_trunc; 504 case BPF_ALU | BPF_MUL | BPF_K: /* (u32) dst *= (u32) imm */ 505 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */ 506 if (imm >= -32768 && imm < 32768) 507 EMIT(PPC_RAW_MULI(dst_reg, dst_reg, IMM_L(imm))); 508 else { 509 PPC_LI32(tmp1_reg, imm); 510 if (BPF_CLASS(code) == BPF_ALU) 511 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, tmp1_reg)); 512 else 513 EMIT(PPC_RAW_MULD(dst_reg, dst_reg, tmp1_reg)); 514 } 515 goto bpf_alu32_trunc; 516 case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */ 517 case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */ 518 if (BPF_OP(code) == BPF_MOD) { 519 if (off) 520 EMIT(PPC_RAW_DIVW(tmp1_reg, dst_reg, src_reg)); 521 else 522 EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg)); 523 524 EMIT(PPC_RAW_MULW(tmp1_reg, src_reg, tmp1_reg)); 525 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 526 } else 527 if (off) 528 EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, src_reg)); 529 else 530 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg)); 531 goto bpf_alu32_trunc; 532 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */ 533 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */ 534 if (BPF_OP(code) == BPF_MOD) { 535 if (off) 536 EMIT(PPC_RAW_DIVD(tmp1_reg, dst_reg, src_reg)); 537 else 538 EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg)); 539 EMIT(PPC_RAW_MULD(tmp1_reg, src_reg, tmp1_reg)); 540 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 541 } else 542 if (off) 543 EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, src_reg)); 544 else 545 EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg)); 546 break; 547 case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */ 548 case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */ 549 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst %= imm */ 550 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */ 551 if (imm == 0) 552 return -EINVAL; 553 if (imm == 1) { 554 if (BPF_OP(code) == BPF_DIV) { 555 goto bpf_alu32_trunc; 556 } else { 557 EMIT(PPC_RAW_LI(dst_reg, 0)); 558 break; 559 } 560 } 561 562 PPC_LI32(tmp1_reg, imm); 563 switch (BPF_CLASS(code)) { 564 case BPF_ALU: 565 if (BPF_OP(code) == BPF_MOD) { 566 if (off) 567 EMIT(PPC_RAW_DIVW(tmp2_reg, dst_reg, tmp1_reg)); 568 else 569 EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg)); 570 EMIT(PPC_RAW_MULW(tmp1_reg, tmp1_reg, tmp2_reg)); 571 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 572 } else 573 if (off) 574 EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, tmp1_reg)); 575 else 576 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg)); 577 break; 578 case BPF_ALU64: 579 if (BPF_OP(code) == BPF_MOD) { 580 if (off) 581 EMIT(PPC_RAW_DIVD(tmp2_reg, dst_reg, tmp1_reg)); 582 else 583 EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg)); 584 EMIT(PPC_RAW_MULD(tmp1_reg, tmp1_reg, tmp2_reg)); 585 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg)); 586 } else 587 if (off) 588 EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, tmp1_reg)); 589 else 590 EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg)); 591 break; 592 } 593 goto bpf_alu32_trunc; 594 case BPF_ALU | BPF_NEG: /* (u32) dst = -dst */ 595 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 596 EMIT(PPC_RAW_NEG(dst_reg, dst_reg)); 597 goto bpf_alu32_trunc; 598 599 /* 600 * Logical operations: AND/OR/XOR/[A]LSH/[A]RSH 601 */ 602 case BPF_ALU | BPF_AND | BPF_X: /* (u32) dst = dst & src */ 603 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 604 EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg)); 605 goto bpf_alu32_trunc; 606 case BPF_ALU | BPF_AND | BPF_K: /* (u32) dst = dst & imm */ 607 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 608 if (!IMM_H(imm)) 609 EMIT(PPC_RAW_ANDI(dst_reg, dst_reg, IMM_L(imm))); 610 else { 611 /* Sign-extended */ 612 PPC_LI32(tmp1_reg, imm); 613 EMIT(PPC_RAW_AND(dst_reg, dst_reg, tmp1_reg)); 614 } 615 goto bpf_alu32_trunc; 616 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 617 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 618 EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg)); 619 goto bpf_alu32_trunc; 620 case BPF_ALU | BPF_OR | BPF_K:/* dst = (u32) dst | (u32) imm */ 621 case BPF_ALU64 | BPF_OR | BPF_K:/* dst = dst | imm */ 622 if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) { 623 /* Sign-extended */ 624 PPC_LI32(tmp1_reg, imm); 625 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp1_reg)); 626 } else { 627 if (IMM_L(imm)) 628 EMIT(PPC_RAW_ORI(dst_reg, dst_reg, IMM_L(imm))); 629 if (IMM_H(imm)) 630 EMIT(PPC_RAW_ORIS(dst_reg, dst_reg, IMM_H(imm))); 631 } 632 goto bpf_alu32_trunc; 633 case BPF_ALU | BPF_XOR | BPF_X: /* (u32) dst ^= src */ 634 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst ^= src */ 635 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg)); 636 goto bpf_alu32_trunc; 637 case BPF_ALU | BPF_XOR | BPF_K: /* (u32) dst ^= (u32) imm */ 638 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst ^= imm */ 639 if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) { 640 /* Sign-extended */ 641 PPC_LI32(tmp1_reg, imm); 642 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, tmp1_reg)); 643 } else { 644 if (IMM_L(imm)) 645 EMIT(PPC_RAW_XORI(dst_reg, dst_reg, IMM_L(imm))); 646 if (IMM_H(imm)) 647 EMIT(PPC_RAW_XORIS(dst_reg, dst_reg, IMM_H(imm))); 648 } 649 goto bpf_alu32_trunc; 650 case BPF_ALU | BPF_LSH | BPF_X: /* (u32) dst <<= (u32) src */ 651 /* slw clears top 32 bits */ 652 EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg)); 653 /* skip zero extension move, but set address map. */ 654 if (insn_is_zext(&insn[i + 1])) 655 addrs[++i] = ctx->idx * 4; 656 break; 657 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */ 658 EMIT(PPC_RAW_SLD(dst_reg, dst_reg, src_reg)); 659 break; 660 case BPF_ALU | BPF_LSH | BPF_K: /* (u32) dst <<== (u32) imm */ 661 /* with imm 0, we still need to clear top 32 bits */ 662 EMIT(PPC_RAW_SLWI(dst_reg, dst_reg, imm)); 663 if (insn_is_zext(&insn[i + 1])) 664 addrs[++i] = ctx->idx * 4; 665 break; 666 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst <<== imm */ 667 if (imm != 0) 668 EMIT(PPC_RAW_SLDI(dst_reg, dst_reg, imm)); 669 break; 670 case BPF_ALU | BPF_RSH | BPF_X: /* (u32) dst >>= (u32) src */ 671 EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); 672 if (insn_is_zext(&insn[i + 1])) 673 addrs[++i] = ctx->idx * 4; 674 break; 675 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */ 676 EMIT(PPC_RAW_SRD(dst_reg, dst_reg, src_reg)); 677 break; 678 case BPF_ALU | BPF_RSH | BPF_K: /* (u32) dst >>= (u32) imm */ 679 EMIT(PPC_RAW_SRWI(dst_reg, dst_reg, imm)); 680 if (insn_is_zext(&insn[i + 1])) 681 addrs[++i] = ctx->idx * 4; 682 break; 683 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst >>= imm */ 684 if (imm != 0) 685 EMIT(PPC_RAW_SRDI(dst_reg, dst_reg, imm)); 686 break; 687 case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */ 688 EMIT(PPC_RAW_SRAW(dst_reg, dst_reg, src_reg)); 689 goto bpf_alu32_trunc; 690 case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ 691 EMIT(PPC_RAW_SRAD(dst_reg, dst_reg, src_reg)); 692 break; 693 case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ 694 EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg, imm)); 695 goto bpf_alu32_trunc; 696 case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */ 697 if (imm != 0) 698 EMIT(PPC_RAW_SRADI(dst_reg, dst_reg, imm)); 699 break; 700 701 /* 702 * MOV 703 */ 704 case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */ 705 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 706 if (imm == 1) { 707 /* special mov32 for zext */ 708 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31)); 709 break; 710 } else if (off == 8) { 711 EMIT(PPC_RAW_EXTSB(dst_reg, src_reg)); 712 } else if (off == 16) { 713 EMIT(PPC_RAW_EXTSH(dst_reg, src_reg)); 714 } else if (off == 32) { 715 EMIT(PPC_RAW_EXTSW(dst_reg, src_reg)); 716 } else if (dst_reg != src_reg) 717 EMIT(PPC_RAW_MR(dst_reg, src_reg)); 718 goto bpf_alu32_trunc; 719 case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */ 720 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */ 721 PPC_LI32(dst_reg, imm); 722 if (imm < 0) 723 goto bpf_alu32_trunc; 724 else if (insn_is_zext(&insn[i + 1])) 725 addrs[++i] = ctx->idx * 4; 726 break; 727 728 bpf_alu32_trunc: 729 /* Truncate to 32-bits */ 730 if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext) 731 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31)); 732 break; 733 734 /* 735 * BPF_FROM_BE/LE 736 */ 737 case BPF_ALU | BPF_END | BPF_FROM_LE: 738 case BPF_ALU | BPF_END | BPF_FROM_BE: 739 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 740 #ifdef __BIG_ENDIAN__ 741 if (BPF_SRC(code) == BPF_FROM_BE) 742 goto emit_clear; 743 #else /* !__BIG_ENDIAN__ */ 744 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE) 745 goto emit_clear; 746 #endif 747 switch (imm) { 748 case 16: 749 /* Rotate 8 bits left & mask with 0x0000ff00 */ 750 EMIT(PPC_RAW_RLWINM(tmp1_reg, dst_reg, 8, 16, 23)); 751 /* Rotate 8 bits right & insert LSB to reg */ 752 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 24, 31)); 753 /* Move result back to dst_reg */ 754 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 755 break; 756 case 32: 757 /* 758 * Rotate word left by 8 bits: 759 * 2 bytes are already in their final position 760 * -- byte 2 and 4 (of bytes 1, 2, 3 and 4) 761 */ 762 EMIT(PPC_RAW_RLWINM(tmp1_reg, dst_reg, 8, 0, 31)); 763 /* Rotate 24 bits and insert byte 1 */ 764 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 0, 7)); 765 /* Rotate 24 bits and insert byte 3 */ 766 EMIT(PPC_RAW_RLWIMI(tmp1_reg, dst_reg, 24, 16, 23)); 767 EMIT(PPC_RAW_MR(dst_reg, tmp1_reg)); 768 break; 769 case 64: 770 /* Store the value to stack and then use byte-reverse loads */ 771 EMIT(PPC_RAW_STD(dst_reg, _R1, bpf_jit_stack_local(ctx))); 772 EMIT(PPC_RAW_ADDI(tmp1_reg, _R1, bpf_jit_stack_local(ctx))); 773 if (cpu_has_feature(CPU_FTR_ARCH_206)) { 774 EMIT(PPC_RAW_LDBRX(dst_reg, 0, tmp1_reg)); 775 } else { 776 EMIT(PPC_RAW_LWBRX(dst_reg, 0, tmp1_reg)); 777 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 778 EMIT(PPC_RAW_SLDI(dst_reg, dst_reg, 32)); 779 EMIT(PPC_RAW_LI(tmp2_reg, 4)); 780 EMIT(PPC_RAW_LWBRX(tmp2_reg, tmp2_reg, tmp1_reg)); 781 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 782 EMIT(PPC_RAW_SLDI(tmp2_reg, tmp2_reg, 32)); 783 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp2_reg)); 784 } 785 break; 786 } 787 break; 788 789 emit_clear: 790 switch (imm) { 791 case 16: 792 /* zero-extend 16 bits into 64 bits */ 793 EMIT(PPC_RAW_RLDICL(dst_reg, dst_reg, 0, 48)); 794 if (insn_is_zext(&insn[i + 1])) 795 addrs[++i] = ctx->idx * 4; 796 break; 797 case 32: 798 if (!fp->aux->verifier_zext) 799 /* zero-extend 32 bits into 64 bits */ 800 EMIT(PPC_RAW_RLDICL(dst_reg, dst_reg, 0, 32)); 801 break; 802 case 64: 803 /* nop */ 804 break; 805 } 806 break; 807 808 /* 809 * BPF_ST NOSPEC (speculation barrier) 810 * 811 * The following must act as a barrier against both Spectre v1 812 * and v4 if we requested both mitigations. Therefore, also emit 813 * 'isync; sync' on E500 or 'ori31' on BOOK3S_64 in addition to 814 * the insns needed for a Spectre v4 barrier. 815 * 816 * If we requested only !bypass_spec_v1 OR only !bypass_spec_v4, 817 * we can skip the respective other barrier type as an 818 * optimization. 819 */ 820 case BPF_ST | BPF_NOSPEC: 821 sync_emitted = false; 822 ori31_emitted = false; 823 #ifdef CONFIG_PPC_E500 824 if (!bpf_jit_bypass_spec_v1()) { 825 EMIT(PPC_RAW_ISYNC()); 826 EMIT(PPC_RAW_SYNC()); 827 sync_emitted = true; 828 } 829 #endif 830 if (!bpf_jit_bypass_spec_v4()) { 831 switch (stf_barrier) { 832 case STF_BARRIER_EIEIO: 833 EMIT(PPC_RAW_EIEIO() | 0x02000000); 834 break; 835 case STF_BARRIER_SYNC_ORI: 836 if (!sync_emitted) 837 EMIT(PPC_RAW_SYNC()); 838 EMIT(PPC_RAW_LD(tmp1_reg, _R13, 0)); 839 EMIT(PPC_RAW_ORI(_R31, _R31, 0)); 840 ori31_emitted = true; 841 break; 842 case STF_BARRIER_FALLBACK: 843 ctx->seen |= SEEN_FUNC; 844 PPC_LI64(_R12, dereference_kernel_function_descriptor(bpf_stf_barrier)); 845 EMIT(PPC_RAW_MTCTR(_R12)); 846 EMIT(PPC_RAW_BCTRL()); 847 break; 848 case STF_BARRIER_NONE: 849 break; 850 } 851 } 852 #ifdef CONFIG_PPC_BOOK3S_64 853 if (!bpf_jit_bypass_spec_v1() && !ori31_emitted) 854 EMIT(PPC_RAW_ORI(_R31, _R31, 0)); 855 #endif 856 break; 857 858 /* 859 * BPF_ST(X) 860 */ 861 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src */ 862 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 863 if (BPF_CLASS(code) == BPF_ST) { 864 EMIT(PPC_RAW_LI(tmp1_reg, imm)); 865 src_reg = tmp1_reg; 866 } 867 EMIT(PPC_RAW_STB(src_reg, dst_reg, off)); 868 break; 869 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 870 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 871 if (BPF_CLASS(code) == BPF_ST) { 872 EMIT(PPC_RAW_LI(tmp1_reg, imm)); 873 src_reg = tmp1_reg; 874 } 875 EMIT(PPC_RAW_STH(src_reg, dst_reg, off)); 876 break; 877 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 878 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 879 if (BPF_CLASS(code) == BPF_ST) { 880 PPC_LI32(tmp1_reg, imm); 881 src_reg = tmp1_reg; 882 } 883 EMIT(PPC_RAW_STW(src_reg, dst_reg, off)); 884 break; 885 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 886 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 887 if (BPF_CLASS(code) == BPF_ST) { 888 PPC_LI32(tmp1_reg, imm); 889 src_reg = tmp1_reg; 890 } 891 if (off % 4) { 892 EMIT(PPC_RAW_LI(tmp2_reg, off)); 893 EMIT(PPC_RAW_STDX(src_reg, dst_reg, tmp2_reg)); 894 } else { 895 EMIT(PPC_RAW_STD(src_reg, dst_reg, off)); 896 } 897 break; 898 899 /* 900 * BPF_STX ATOMIC (atomic ops) 901 */ 902 case BPF_STX | BPF_ATOMIC | BPF_W: 903 case BPF_STX | BPF_ATOMIC | BPF_DW: 904 save_reg = tmp2_reg; 905 ret_reg = src_reg; 906 907 /* Get offset into TMP_REG_1 */ 908 EMIT(PPC_RAW_LI(tmp1_reg, off)); 909 /* 910 * Enforce full ordering for operations with BPF_FETCH by emitting a 'sync' 911 * before and after the operation. 912 * 913 * This is a requirement in the Linux Kernel Memory Model. 914 * See __cmpxchg_u64() in asm/cmpxchg.h as an example. 915 */ 916 if ((imm & BPF_FETCH) && IS_ENABLED(CONFIG_SMP)) 917 EMIT(PPC_RAW_SYNC()); 918 tmp_idx = ctx->idx * 4; 919 /* load value from memory into TMP_REG_2 */ 920 if (size == BPF_DW) 921 EMIT(PPC_RAW_LDARX(tmp2_reg, tmp1_reg, dst_reg, 0)); 922 else 923 EMIT(PPC_RAW_LWARX(tmp2_reg, tmp1_reg, dst_reg, 0)); 924 925 /* Save old value in _R0 */ 926 if (imm & BPF_FETCH) 927 EMIT(PPC_RAW_MR(_R0, tmp2_reg)); 928 929 switch (imm) { 930 case BPF_ADD: 931 case BPF_ADD | BPF_FETCH: 932 EMIT(PPC_RAW_ADD(tmp2_reg, tmp2_reg, src_reg)); 933 break; 934 case BPF_AND: 935 case BPF_AND | BPF_FETCH: 936 EMIT(PPC_RAW_AND(tmp2_reg, tmp2_reg, src_reg)); 937 break; 938 case BPF_OR: 939 case BPF_OR | BPF_FETCH: 940 EMIT(PPC_RAW_OR(tmp2_reg, tmp2_reg, src_reg)); 941 break; 942 case BPF_XOR: 943 case BPF_XOR | BPF_FETCH: 944 EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg)); 945 break; 946 case BPF_CMPXCHG: 947 /* 948 * Return old value in BPF_REG_0 for BPF_CMPXCHG & 949 * in src_reg for other cases. 950 */ 951 ret_reg = bpf_to_ppc(BPF_REG_0); 952 953 /* Compare with old value in BPF_R0 */ 954 if (size == BPF_DW) 955 EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg)); 956 else 957 EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg)); 958 /* Don't set if different from old value */ 959 PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); 960 fallthrough; 961 case BPF_XCHG: 962 save_reg = src_reg; 963 break; 964 default: 965 pr_err_ratelimited( 966 "eBPF filter atomic op code %02x (@%d) unsupported\n", 967 code, i); 968 return -EOPNOTSUPP; 969 } 970 971 /* store new value */ 972 if (size == BPF_DW) 973 EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg, dst_reg)); 974 else 975 EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg, dst_reg)); 976 /* we're done if this succeeded */ 977 PPC_BCC_SHORT(COND_NE, tmp_idx); 978 979 if (imm & BPF_FETCH) { 980 /* Emit 'sync' to enforce full ordering */ 981 if (IS_ENABLED(CONFIG_SMP)) 982 EMIT(PPC_RAW_SYNC()); 983 EMIT(PPC_RAW_MR(ret_reg, _R0)); 984 /* 985 * Skip unnecessary zero-extension for 32-bit cmpxchg. 986 * For context, see commit 39491867ace5. 987 */ 988 if (size != BPF_DW && imm == BPF_CMPXCHG && 989 insn_is_zext(&insn[i + 1])) 990 addrs[++i] = ctx->idx * 4; 991 } 992 break; 993 994 /* 995 * BPF_LDX 996 */ 997 /* dst = *(u8 *)(ul) (src + off) */ 998 case BPF_LDX | BPF_MEM | BPF_B: 999 case BPF_LDX | BPF_MEMSX | BPF_B: 1000 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1001 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1002 /* dst = *(u16 *)(ul) (src + off) */ 1003 case BPF_LDX | BPF_MEM | BPF_H: 1004 case BPF_LDX | BPF_MEMSX | BPF_H: 1005 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1006 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1007 /* dst = *(u32 *)(ul) (src + off) */ 1008 case BPF_LDX | BPF_MEM | BPF_W: 1009 case BPF_LDX | BPF_MEMSX | BPF_W: 1010 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1011 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1012 /* dst = *(u64 *)(ul) (src + off) */ 1013 case BPF_LDX | BPF_MEM | BPF_DW: 1014 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1015 /* 1016 * As PTR_TO_BTF_ID that uses BPF_PROBE_MEM mode could either be a valid 1017 * kernel pointer or NULL but not a userspace address, execute BPF_PROBE_MEM 1018 * load only if addr is kernel address (see is_kernel_addr()), otherwise 1019 * set dst_reg=0 and move on. 1020 */ 1021 if (BPF_MODE(code) == BPF_PROBE_MEM || BPF_MODE(code) == BPF_PROBE_MEMSX) { 1022 EMIT(PPC_RAW_ADDI(tmp1_reg, src_reg, off)); 1023 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) 1024 PPC_LI64(tmp2_reg, 0x8000000000000000ul); 1025 else /* BOOK3S_64 */ 1026 PPC_LI64(tmp2_reg, PAGE_OFFSET); 1027 EMIT(PPC_RAW_CMPLD(tmp1_reg, tmp2_reg)); 1028 PPC_BCC_SHORT(COND_GT, (ctx->idx + 3) * 4); 1029 EMIT(PPC_RAW_LI(dst_reg, 0)); 1030 /* 1031 * Check if 'off' is word aligned for BPF_DW, because 1032 * we might generate two instructions. 1033 */ 1034 if ((BPF_SIZE(code) == BPF_DW || 1035 (BPF_SIZE(code) == BPF_B && BPF_MODE(code) == BPF_PROBE_MEMSX)) && 1036 (off & 3)) 1037 PPC_JMP((ctx->idx + 3) * 4); 1038 else 1039 PPC_JMP((ctx->idx + 2) * 4); 1040 } 1041 1042 if (BPF_MODE(code) == BPF_MEMSX || BPF_MODE(code) == BPF_PROBE_MEMSX) { 1043 switch (size) { 1044 case BPF_B: 1045 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 1046 EMIT(PPC_RAW_EXTSB(dst_reg, dst_reg)); 1047 break; 1048 case BPF_H: 1049 EMIT(PPC_RAW_LHA(dst_reg, src_reg, off)); 1050 break; 1051 case BPF_W: 1052 EMIT(PPC_RAW_LWA(dst_reg, src_reg, off)); 1053 break; 1054 } 1055 } else { 1056 switch (size) { 1057 case BPF_B: 1058 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); 1059 break; 1060 case BPF_H: 1061 EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off)); 1062 break; 1063 case BPF_W: 1064 EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off)); 1065 break; 1066 case BPF_DW: 1067 if (off % 4) { 1068 EMIT(PPC_RAW_LI(tmp1_reg, off)); 1069 EMIT(PPC_RAW_LDX(dst_reg, src_reg, tmp1_reg)); 1070 } else { 1071 EMIT(PPC_RAW_LD(dst_reg, src_reg, off)); 1072 } 1073 break; 1074 } 1075 } 1076 1077 if (size != BPF_DW && insn_is_zext(&insn[i + 1])) 1078 addrs[++i] = ctx->idx * 4; 1079 1080 if (BPF_MODE(code) == BPF_PROBE_MEM) { 1081 ret = bpf_add_extable_entry(fp, image, fimage, pass, ctx, 1082 ctx->idx - 1, 4, dst_reg); 1083 if (ret) 1084 return ret; 1085 } 1086 break; 1087 1088 /* 1089 * Doubleword load 1090 * 16 byte instruction that uses two 'struct bpf_insn' 1091 */ 1092 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 1093 imm64 = ((u64)(u32) insn[i].imm) | 1094 (((u64)(u32) insn[i+1].imm) << 32); 1095 PPC_LI64(dst_reg, imm64); 1096 /* Adjust for two bpf instructions */ 1097 addrs[++i] = ctx->idx * 4; 1098 break; 1099 1100 /* 1101 * Return/Exit 1102 */ 1103 case BPF_JMP | BPF_EXIT: 1104 /* 1105 * If this isn't the very last instruction, branch to 1106 * the epilogue. If we _are_ the last instruction, 1107 * we'll just fall through to the epilogue. 1108 */ 1109 if (i != flen - 1) { 1110 ret = bpf_jit_emit_exit_insn(image, ctx, tmp1_reg, exit_addr); 1111 if (ret) 1112 return ret; 1113 } 1114 /* else fall through to the epilogue */ 1115 break; 1116 1117 /* 1118 * Call kernel helper or bpf function 1119 */ 1120 case BPF_JMP | BPF_CALL: 1121 ctx->seen |= SEEN_FUNC; 1122 1123 ret = bpf_jit_get_func_addr(fp, &insn[i], extra_pass, 1124 &func_addr, &func_addr_fixed); 1125 if (ret < 0) 1126 return ret; 1127 1128 ret = bpf_jit_emit_func_call_rel(image, fimage, ctx, func_addr); 1129 if (ret) 1130 return ret; 1131 1132 /* move return value from r3 to BPF_REG_0 */ 1133 EMIT(PPC_RAW_MR(bpf_to_ppc(BPF_REG_0), _R3)); 1134 break; 1135 1136 /* 1137 * Jumps and branches 1138 */ 1139 case BPF_JMP | BPF_JA: 1140 PPC_JMP(addrs[i + 1 + off]); 1141 break; 1142 case BPF_JMP32 | BPF_JA: 1143 PPC_JMP(addrs[i + 1 + imm]); 1144 break; 1145 1146 case BPF_JMP | BPF_JGT | BPF_K: 1147 case BPF_JMP | BPF_JGT | BPF_X: 1148 case BPF_JMP | BPF_JSGT | BPF_K: 1149 case BPF_JMP | BPF_JSGT | BPF_X: 1150 case BPF_JMP32 | BPF_JGT | BPF_K: 1151 case BPF_JMP32 | BPF_JGT | BPF_X: 1152 case BPF_JMP32 | BPF_JSGT | BPF_K: 1153 case BPF_JMP32 | BPF_JSGT | BPF_X: 1154 true_cond = COND_GT; 1155 goto cond_branch; 1156 case BPF_JMP | BPF_JLT | BPF_K: 1157 case BPF_JMP | BPF_JLT | BPF_X: 1158 case BPF_JMP | BPF_JSLT | BPF_K: 1159 case BPF_JMP | BPF_JSLT | BPF_X: 1160 case BPF_JMP32 | BPF_JLT | BPF_K: 1161 case BPF_JMP32 | BPF_JLT | BPF_X: 1162 case BPF_JMP32 | BPF_JSLT | BPF_K: 1163 case BPF_JMP32 | BPF_JSLT | BPF_X: 1164 true_cond = COND_LT; 1165 goto cond_branch; 1166 case BPF_JMP | BPF_JGE | BPF_K: 1167 case BPF_JMP | BPF_JGE | BPF_X: 1168 case BPF_JMP | BPF_JSGE | BPF_K: 1169 case BPF_JMP | BPF_JSGE | BPF_X: 1170 case BPF_JMP32 | BPF_JGE | BPF_K: 1171 case BPF_JMP32 | BPF_JGE | BPF_X: 1172 case BPF_JMP32 | BPF_JSGE | BPF_K: 1173 case BPF_JMP32 | BPF_JSGE | BPF_X: 1174 true_cond = COND_GE; 1175 goto cond_branch; 1176 case BPF_JMP | BPF_JLE | BPF_K: 1177 case BPF_JMP | BPF_JLE | BPF_X: 1178 case BPF_JMP | BPF_JSLE | BPF_K: 1179 case BPF_JMP | BPF_JSLE | BPF_X: 1180 case BPF_JMP32 | BPF_JLE | BPF_K: 1181 case BPF_JMP32 | BPF_JLE | BPF_X: 1182 case BPF_JMP32 | BPF_JSLE | BPF_K: 1183 case BPF_JMP32 | BPF_JSLE | BPF_X: 1184 true_cond = COND_LE; 1185 goto cond_branch; 1186 case BPF_JMP | BPF_JEQ | BPF_K: 1187 case BPF_JMP | BPF_JEQ | BPF_X: 1188 case BPF_JMP32 | BPF_JEQ | BPF_K: 1189 case BPF_JMP32 | BPF_JEQ | BPF_X: 1190 true_cond = COND_EQ; 1191 goto cond_branch; 1192 case BPF_JMP | BPF_JNE | BPF_K: 1193 case BPF_JMP | BPF_JNE | BPF_X: 1194 case BPF_JMP32 | BPF_JNE | BPF_K: 1195 case BPF_JMP32 | BPF_JNE | BPF_X: 1196 true_cond = COND_NE; 1197 goto cond_branch; 1198 case BPF_JMP | BPF_JSET | BPF_K: 1199 case BPF_JMP | BPF_JSET | BPF_X: 1200 case BPF_JMP32 | BPF_JSET | BPF_K: 1201 case BPF_JMP32 | BPF_JSET | BPF_X: 1202 true_cond = COND_NE; 1203 /* Fall through */ 1204 1205 cond_branch: 1206 switch (code) { 1207 case BPF_JMP | BPF_JGT | BPF_X: 1208 case BPF_JMP | BPF_JLT | BPF_X: 1209 case BPF_JMP | BPF_JGE | BPF_X: 1210 case BPF_JMP | BPF_JLE | BPF_X: 1211 case BPF_JMP | BPF_JEQ | BPF_X: 1212 case BPF_JMP | BPF_JNE | BPF_X: 1213 case BPF_JMP32 | BPF_JGT | BPF_X: 1214 case BPF_JMP32 | BPF_JLT | BPF_X: 1215 case BPF_JMP32 | BPF_JGE | BPF_X: 1216 case BPF_JMP32 | BPF_JLE | BPF_X: 1217 case BPF_JMP32 | BPF_JEQ | BPF_X: 1218 case BPF_JMP32 | BPF_JNE | BPF_X: 1219 /* unsigned comparison */ 1220 if (BPF_CLASS(code) == BPF_JMP32) 1221 EMIT(PPC_RAW_CMPLW(dst_reg, src_reg)); 1222 else 1223 EMIT(PPC_RAW_CMPLD(dst_reg, src_reg)); 1224 break; 1225 case BPF_JMP | BPF_JSGT | BPF_X: 1226 case BPF_JMP | BPF_JSLT | BPF_X: 1227 case BPF_JMP | BPF_JSGE | BPF_X: 1228 case BPF_JMP | BPF_JSLE | BPF_X: 1229 case BPF_JMP32 | BPF_JSGT | BPF_X: 1230 case BPF_JMP32 | BPF_JSLT | BPF_X: 1231 case BPF_JMP32 | BPF_JSGE | BPF_X: 1232 case BPF_JMP32 | BPF_JSLE | BPF_X: 1233 /* signed comparison */ 1234 if (BPF_CLASS(code) == BPF_JMP32) 1235 EMIT(PPC_RAW_CMPW(dst_reg, src_reg)); 1236 else 1237 EMIT(PPC_RAW_CMPD(dst_reg, src_reg)); 1238 break; 1239 case BPF_JMP | BPF_JSET | BPF_X: 1240 case BPF_JMP32 | BPF_JSET | BPF_X: 1241 if (BPF_CLASS(code) == BPF_JMP) { 1242 EMIT(PPC_RAW_AND_DOT(tmp1_reg, dst_reg, src_reg)); 1243 } else { 1244 EMIT(PPC_RAW_AND(tmp1_reg, dst_reg, src_reg)); 1245 EMIT(PPC_RAW_RLWINM_DOT(tmp1_reg, tmp1_reg, 0, 0, 31)); 1246 } 1247 break; 1248 case BPF_JMP | BPF_JNE | BPF_K: 1249 case BPF_JMP | BPF_JEQ | BPF_K: 1250 case BPF_JMP | BPF_JGT | BPF_K: 1251 case BPF_JMP | BPF_JLT | BPF_K: 1252 case BPF_JMP | BPF_JGE | BPF_K: 1253 case BPF_JMP | BPF_JLE | BPF_K: 1254 case BPF_JMP32 | BPF_JNE | BPF_K: 1255 case BPF_JMP32 | BPF_JEQ | BPF_K: 1256 case BPF_JMP32 | BPF_JGT | BPF_K: 1257 case BPF_JMP32 | BPF_JLT | BPF_K: 1258 case BPF_JMP32 | BPF_JGE | BPF_K: 1259 case BPF_JMP32 | BPF_JLE | BPF_K: 1260 { 1261 bool is_jmp32 = BPF_CLASS(code) == BPF_JMP32; 1262 1263 /* 1264 * Need sign-extended load, so only positive 1265 * values can be used as imm in cmpldi 1266 */ 1267 if (imm >= 0 && imm < 32768) { 1268 if (is_jmp32) 1269 EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); 1270 else 1271 EMIT(PPC_RAW_CMPLDI(dst_reg, imm)); 1272 } else { 1273 /* sign-extending load */ 1274 PPC_LI32(tmp1_reg, imm); 1275 /* ... but unsigned comparison */ 1276 if (is_jmp32) 1277 EMIT(PPC_RAW_CMPLW(dst_reg, tmp1_reg)); 1278 else 1279 EMIT(PPC_RAW_CMPLD(dst_reg, tmp1_reg)); 1280 } 1281 break; 1282 } 1283 case BPF_JMP | BPF_JSGT | BPF_K: 1284 case BPF_JMP | BPF_JSLT | BPF_K: 1285 case BPF_JMP | BPF_JSGE | BPF_K: 1286 case BPF_JMP | BPF_JSLE | BPF_K: 1287 case BPF_JMP32 | BPF_JSGT | BPF_K: 1288 case BPF_JMP32 | BPF_JSLT | BPF_K: 1289 case BPF_JMP32 | BPF_JSGE | BPF_K: 1290 case BPF_JMP32 | BPF_JSLE | BPF_K: 1291 { 1292 bool is_jmp32 = BPF_CLASS(code) == BPF_JMP32; 1293 1294 /* 1295 * signed comparison, so any 16-bit value 1296 * can be used in cmpdi 1297 */ 1298 if (imm >= -32768 && imm < 32768) { 1299 if (is_jmp32) 1300 EMIT(PPC_RAW_CMPWI(dst_reg, imm)); 1301 else 1302 EMIT(PPC_RAW_CMPDI(dst_reg, imm)); 1303 } else { 1304 PPC_LI32(tmp1_reg, imm); 1305 if (is_jmp32) 1306 EMIT(PPC_RAW_CMPW(dst_reg, tmp1_reg)); 1307 else 1308 EMIT(PPC_RAW_CMPD(dst_reg, tmp1_reg)); 1309 } 1310 break; 1311 } 1312 case BPF_JMP | BPF_JSET | BPF_K: 1313 case BPF_JMP32 | BPF_JSET | BPF_K: 1314 /* andi does not sign-extend the immediate */ 1315 if (imm >= 0 && imm < 32768) 1316 /* PPC_ANDI is _only/always_ dot-form */ 1317 EMIT(PPC_RAW_ANDI(tmp1_reg, dst_reg, imm)); 1318 else { 1319 PPC_LI32(tmp1_reg, imm); 1320 if (BPF_CLASS(code) == BPF_JMP) { 1321 EMIT(PPC_RAW_AND_DOT(tmp1_reg, dst_reg, 1322 tmp1_reg)); 1323 } else { 1324 EMIT(PPC_RAW_AND(tmp1_reg, dst_reg, tmp1_reg)); 1325 EMIT(PPC_RAW_RLWINM_DOT(tmp1_reg, tmp1_reg, 1326 0, 0, 31)); 1327 } 1328 } 1329 break; 1330 } 1331 PPC_BCC(true_cond, addrs[i + 1 + off]); 1332 break; 1333 1334 /* 1335 * Tail call 1336 */ 1337 case BPF_JMP | BPF_TAIL_CALL: 1338 ctx->seen |= SEEN_TAILCALL; 1339 ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]); 1340 if (ret < 0) 1341 return ret; 1342 break; 1343 1344 default: 1345 /* 1346 * The filter contains something cruel & unusual. 1347 * We don't handle it, but also there shouldn't be 1348 * anything missing from our list. 1349 */ 1350 pr_err_ratelimited("eBPF filter opcode %04x (@%d) unsupported\n", 1351 code, i); 1352 return -ENOTSUPP; 1353 } 1354 } 1355 1356 /* Set end-of-body-code address for exit. */ 1357 addrs[i] = ctx->idx * 4; 1358 1359 return 0; 1360 } 1361