1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This file contains the routines for initializing the MMU 4 * on the 8xx series of chips. 5 * -- christophe 6 * 7 * Derived from arch/powerpc/mm/40x_mmu.c: 8 */ 9 10 #include <linux/memblock.h> 11 #include <linux/hugetlb.h> 12 13 #include <asm/fixmap.h> 14 #include <asm/pgalloc.h> 15 16 #include <mm/mmu_decl.h> 17 18 #define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT) 19 20 static unsigned long block_mapped_ram; 21 22 /* 23 * Return PA for this VA if it is in an area mapped with LTLBs or fixmap. 24 * Otherwise, returns 0 25 */ 26 phys_addr_t v_block_mapped(unsigned long va) 27 { 28 unsigned long p = PHYS_IMMR_BASE; 29 30 if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE) 31 return p + va - VIRT_IMMR_BASE; 32 if (va >= PAGE_OFFSET && va < PAGE_OFFSET + block_mapped_ram) 33 return __pa(va); 34 return 0; 35 } 36 37 /* 38 * Return VA for a given PA mapped with LTLBs or fixmap 39 * Return 0 if not mapped 40 */ 41 unsigned long p_block_mapped(phys_addr_t pa) 42 { 43 unsigned long p = PHYS_IMMR_BASE; 44 45 if (pa >= p && pa < p + IMMR_SIZE) 46 return VIRT_IMMR_BASE + pa - p; 47 if (pa < block_mapped_ram) 48 return (unsigned long)__va(pa); 49 return 0; 50 } 51 52 static int __ref __early_map_kernel_hugepage(unsigned long va, phys_addr_t pa, 53 pgprot_t prot, int psize, bool new) 54 { 55 pmd_t *pmdp = pmd_off_k(va); 56 pte_t *ptep; 57 58 if (WARN_ON(psize != MMU_PAGE_512K && psize != MMU_PAGE_8M)) 59 return -EINVAL; 60 61 if (new) { 62 if (WARN_ON(slab_is_available())) 63 return -EINVAL; 64 65 if (psize == MMU_PAGE_512K) { 66 ptep = early_pte_alloc_kernel(pmdp, va); 67 /* The PTE should never be already present */ 68 if (WARN_ON(pte_present(*ptep) && pgprot_val(prot))) 69 return -EINVAL; 70 } else { 71 if (WARN_ON(!pmd_none(*pmdp) || !pmd_none(*(pmdp + 1)))) 72 return -EINVAL; 73 74 ptep = early_alloc_pgtable(PTE_FRAG_SIZE); 75 pmd_populate_kernel(&init_mm, pmdp, ptep); 76 77 ptep = early_alloc_pgtable(PTE_FRAG_SIZE); 78 pmd_populate_kernel(&init_mm, pmdp + 1, ptep); 79 80 ptep = (pte_t *)pmdp; 81 } 82 } else { 83 if (psize == MMU_PAGE_512K) 84 ptep = pte_offset_kernel(pmdp, va); 85 else 86 ptep = (pte_t *)pmdp; 87 } 88 89 if (WARN_ON(!ptep)) 90 return -ENOMEM; 91 92 set_huge_pte_at(&init_mm, va, ptep, 93 pte_mkhuge(pfn_pte(pa >> PAGE_SHIFT, prot)), 94 1UL << mmu_psize_to_shift(psize)); 95 96 return 0; 97 } 98 99 /* 100 * MMU_init_hw does the chip-specific initialization of the MMU hardware. 101 */ 102 void __init MMU_init_hw(void) 103 { 104 } 105 106 static bool immr_is_mapped __initdata; 107 108 void __init mmu_mapin_immr(void) 109 { 110 if (immr_is_mapped) 111 return; 112 113 immr_is_mapped = true; 114 115 __early_map_kernel_hugepage(VIRT_IMMR_BASE, PHYS_IMMR_BASE, 116 PAGE_KERNEL_NCG, MMU_PAGE_512K, true); 117 } 118 119 static int mmu_mapin_ram_chunk(unsigned long offset, unsigned long top, 120 pgprot_t prot, bool new) 121 { 122 unsigned long v = PAGE_OFFSET + offset; 123 unsigned long p = offset; 124 int err = 0; 125 126 WARN_ON(!IS_ALIGNED(offset, SZ_512K) || !IS_ALIGNED(top, SZ_512K)); 127 128 for (; p < ALIGN(p, SZ_8M) && p < top && !err; p += SZ_512K, v += SZ_512K) 129 err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new); 130 for (; p < ALIGN_DOWN(top, SZ_8M) && p < top && !err; p += SZ_8M, v += SZ_8M) 131 err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_8M, new); 132 for (; p < ALIGN_DOWN(top, SZ_512K) && p < top && !err; p += SZ_512K, v += SZ_512K) 133 err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new); 134 135 if (!new) 136 flush_tlb_kernel_range(PAGE_OFFSET + v, PAGE_OFFSET + top); 137 138 return err; 139 } 140 141 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) 142 { 143 unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M); 144 unsigned long sinittext = __pa(_sinittext); 145 bool strict_boundary = strict_kernel_rwx_enabled() || debug_pagealloc_enabled_or_kfence(); 146 unsigned long boundary = strict_boundary ? sinittext : etext8; 147 unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M); 148 149 WARN_ON(top < einittext8); 150 151 mmu_mapin_immr(); 152 153 mmu_mapin_ram_chunk(0, boundary, PAGE_KERNEL_TEXT, true); 154 if (debug_pagealloc_enabled_or_kfence()) { 155 top = boundary; 156 } else { 157 mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL_TEXT, true); 158 mmu_mapin_ram_chunk(einittext8, top, PAGE_KERNEL, true); 159 } 160 161 if (top > SZ_32M) 162 memblock_set_current_limit(top); 163 164 block_mapped_ram = top; 165 166 return top; 167 } 168 169 int mmu_mark_initmem_nx(void) 170 { 171 unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M); 172 unsigned long sinittext = __pa(_sinittext); 173 unsigned long boundary = strict_kernel_rwx_enabled() ? sinittext : etext8; 174 unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M); 175 int err = 0; 176 177 if (!debug_pagealloc_enabled_or_kfence()) 178 err = mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL, false); 179 180 mmu_pin_tlb(block_mapped_ram, false); 181 182 return err; 183 } 184 185 #ifdef CONFIG_STRICT_KERNEL_RWX 186 int mmu_mark_rodata_ro(void) 187 { 188 unsigned long sinittext = __pa(_sinittext); 189 int err; 190 191 err = mmu_mapin_ram_chunk(0, sinittext, PAGE_KERNEL_ROX, false); 192 if (IS_ENABLED(CONFIG_PIN_TLB_DATA)) 193 mmu_pin_tlb(block_mapped_ram, true); 194 195 return err; 196 } 197 #endif 198 199 void __init setup_initial_memory_limit(phys_addr_t first_memblock_base, 200 phys_addr_t first_memblock_size) 201 { 202 /* We don't currently support the first MEMBLOCK not mapping 0 203 * physical on those processors 204 */ 205 BUG_ON(first_memblock_base != 0); 206 207 /* 8xx can only access 32MB at the moment */ 208 memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M)); 209 } 210 211 int pud_clear_huge(pud_t *pud) 212 { 213 return 0; 214 } 215 216 int pmd_clear_huge(pmd_t *pmd) 217 { 218 return 0; 219 } 220