1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Common implementation of switch_mm_irqs_off 4 * 5 * Copyright IBM Corp. 2017 6 */ 7 8 #include <linux/mm.h> 9 #include <linux/cpu.h> 10 #include <linux/sched/mm.h> 11 12 #include <asm/mmu_context.h> 13 #include <asm/pgalloc.h> 14 15 #if defined(CONFIG_PPC32) 16 static inline void switch_mm_pgdir(struct task_struct *tsk, 17 struct mm_struct *mm) 18 { 19 /* 32-bit keeps track of the current PGDIR in the thread struct */ 20 tsk->thread.pgdir = mm->pgd; 21 } 22 #elif defined(CONFIG_PPC_BOOK3E_64) 23 static inline void switch_mm_pgdir(struct task_struct *tsk, 24 struct mm_struct *mm) 25 { 26 /* 64-bit Book3E keeps track of current PGD in the PACA */ 27 get_paca()->pgd = mm->pgd; 28 } 29 #else 30 static inline void switch_mm_pgdir(struct task_struct *tsk, 31 struct mm_struct *mm) { } 32 #endif 33 34 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 35 struct task_struct *tsk) 36 { 37 bool new_on_cpu = false; 38 39 /* Mark this context has been used on the new CPU */ 40 if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) { 41 cpumask_set_cpu(smp_processor_id(), mm_cpumask(next)); 42 inc_mm_active_cpus(next); 43 44 /* 45 * This full barrier orders the store to the cpumask above vs 46 * a subsequent load which allows this CPU/MMU to begin loading 47 * translations for 'next' from page table PTEs into the TLB. 48 * 49 * When using the radix MMU, that operation is the load of the 50 * MMU context id, which is then moved to SPRN_PID. 51 * 52 * For the hash MMU it is either the first load from slb_cache 53 * in switch_slb() to preload the SLBs, or the load of 54 * get_user_context which loads the context for the VSID hash 55 * to insert a new SLB, in the SLB fault handler. 56 * 57 * On the other side, the barrier is in mm/tlb-radix.c for 58 * radix which orders earlier stores to clear the PTEs before 59 * the load of mm_cpumask to check which CPU TLBs should be 60 * flushed. For hash, pte_xchg to clear the PTE includes the 61 * barrier. 62 * 63 * This full barrier is also needed by membarrier when 64 * switching between processes after store to rq->curr, before 65 * user-space memory accesses. 66 */ 67 smp_mb(); 68 69 new_on_cpu = true; 70 } 71 72 /* Some subarchs need to track the PGD elsewhere */ 73 switch_mm_pgdir(tsk, next); 74 75 /* Nothing else to do if we aren't actually switching */ 76 if (prev == next) 77 return; 78 79 /* 80 * We must stop all altivec streams before changing the HW 81 * context 82 */ 83 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 84 asm volatile ("dssall"); 85 86 if (!new_on_cpu) 87 membarrier_arch_switch_mm(prev, next, tsk); 88 89 /* 90 * The actual HW switching method differs between the various 91 * sub architectures. Out of line for now 92 */ 93 switch_mmu_context(prev, next, tsk); 94 } 95 96 #ifndef CONFIG_PPC_BOOK3S_64 97 void arch_exit_mmap(struct mm_struct *mm) 98 { 99 void *frag = pte_frag_get(&mm->context); 100 101 if (frag) 102 pte_frag_destroy(frag); 103 } 104 #endif 105