1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later) 4 * 5 * Copyright (C) 2003 David Gibson, IBM Corporation. 6 * 7 * Based on the IA-32 version: 8 * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com> 9 */ 10 11 #include <linux/mm.h> 12 #include <linux/hugetlb.h> 13 #include <asm/cacheflush.h> 14 #include <asm/machdep.h> 15 16 unsigned int hpage_shift; 17 EXPORT_SYMBOL(hpage_shift); 18 19 #ifdef CONFIG_PPC_64S_HASH_MMU 20 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, 21 pte_t *ptep, unsigned long trap, unsigned long flags, 22 int ssize, unsigned int shift, unsigned int mmu_psize) 23 { 24 real_pte_t rpte; 25 unsigned long vpn; 26 unsigned long old_pte, new_pte; 27 unsigned long rflags, pa; 28 long slot, offset; 29 30 BUG_ON(shift != mmu_psize_defs[mmu_psize].shift); 31 32 /* Search the Linux page table for a match with va */ 33 vpn = hpt_vpn(ea, vsid, ssize); 34 35 /* 36 * At this point, we have a pte (old_pte) which can be used to build 37 * or update an HPTE. There are 2 cases: 38 * 39 * 1. There is a valid (present) pte with no associated HPTE (this is 40 * the most common case) 41 * 2. There is a valid (present) pte with an associated HPTE. The 42 * current values of the pp bits in the HPTE prevent access 43 * because we are doing software DIRTY bit management and the 44 * page is currently not DIRTY. 45 */ 46 47 48 do { 49 old_pte = pte_val(*ptep); 50 /* If PTE busy, retry the access */ 51 if (unlikely(old_pte & H_PAGE_BUSY)) 52 return 0; 53 /* If PTE permissions don't match, take page fault */ 54 if (unlikely(!check_pte_access(access, old_pte))) 55 return 1; 56 /* 57 * If hash-4k, hugepages use seeral contiguous PxD entries 58 * so bail out and let mm make the page young or dirty 59 */ 60 if (IS_ENABLED(CONFIG_PPC_4K_PAGES)) { 61 if (!(old_pte & _PAGE_ACCESSED)) 62 return 1; 63 if ((access & _PAGE_WRITE) && !(old_pte & _PAGE_DIRTY)) 64 return 1; 65 } 66 67 /* 68 * Try to lock the PTE, add ACCESSED and DIRTY if it was 69 * a write access 70 */ 71 new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED; 72 if (access & _PAGE_WRITE) 73 new_pte |= _PAGE_DIRTY; 74 } while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte))); 75 76 /* Make sure this is a hugetlb entry */ 77 if (old_pte & (H_PAGE_THP_HUGE | _PAGE_DEVMAP)) 78 return 0; 79 80 rflags = htab_convert_pte_flags(new_pte, flags); 81 if (unlikely(mmu_psize == MMU_PAGE_16G)) 82 offset = PTRS_PER_PUD; 83 else 84 offset = PTRS_PER_PMD; 85 rpte = __real_pte(__pte(old_pte), ptep, offset); 86 87 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) 88 /* 89 * No CPU has hugepages but lacks no execute, so we 90 * don't need to worry about that case 91 */ 92 rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap); 93 94 /* Check if pte already has an hpte (case 2) */ 95 if (unlikely(old_pte & H_PAGE_HASHPTE)) { 96 /* There MIGHT be an HPTE for this pte */ 97 unsigned long gslot; 98 99 gslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, 0); 100 if (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, mmu_psize, 101 mmu_psize, ssize, flags) == -1) 102 old_pte &= ~_PAGE_HPTEFLAGS; 103 } 104 105 if (likely(!(old_pte & H_PAGE_HASHPTE))) { 106 unsigned long hash = hpt_hash(vpn, shift, ssize); 107 108 pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT; 109 110 /* clear HPTE slot informations in new PTE */ 111 new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE; 112 113 slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0, 114 mmu_psize, ssize); 115 116 /* 117 * Hypervisor failure. Restore old pte and return -1 118 * similar to __hash_page_* 119 */ 120 if (unlikely(slot == -2)) { 121 *ptep = __pte(old_pte); 122 hash_failure_debug(ea, access, vsid, trap, ssize, 123 mmu_psize, mmu_psize, old_pte); 124 return -1; 125 } 126 127 new_pte |= pte_set_hidx(ptep, rpte, 0, slot, offset); 128 } 129 130 /* 131 * No need to use ldarx/stdcx here 132 */ 133 *ptep = __pte(new_pte & ~H_PAGE_BUSY); 134 return 0; 135 } 136 #endif 137 138 pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, 139 unsigned long addr, pte_t *ptep) 140 { 141 unsigned long pte_val; 142 /* 143 * Clear the _PAGE_PRESENT so that no hardware parallel update is 144 * possible. Also keep the pte_present true so that we don't take 145 * wrong fault. 146 */ 147 pte_val = pte_update(vma->vm_mm, addr, ptep, 148 _PAGE_PRESENT, _PAGE_INVALID, 1); 149 150 return __pte(pte_val); 151 } 152 153 void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, 154 pte_t *ptep, pte_t old_pte, pte_t pte) 155 { 156 unsigned long psize; 157 158 if (radix_enabled()) 159 return radix__huge_ptep_modify_prot_commit(vma, addr, ptep, 160 old_pte, pte); 161 162 psize = huge_page_size(hstate_vma(vma)); 163 set_huge_pte_at(vma->vm_mm, addr, ptep, pte, psize); 164 } 165 166 void __init hugetlbpage_init_defaultsize(void) 167 { 168 /* Set default large page size. Currently, we pick 16M or 1M 169 * depending on what is available 170 */ 171 if (mmu_psize_defs[MMU_PAGE_16M].shift) 172 hpage_shift = mmu_psize_defs[MMU_PAGE_16M].shift; 173 else if (mmu_psize_defs[MMU_PAGE_1M].shift) 174 hpage_shift = mmu_psize_defs[MMU_PAGE_1M].shift; 175 else if (mmu_psize_defs[MMU_PAGE_2M].shift) 176 hpage_shift = mmu_psize_defs[MMU_PAGE_2M].shift; 177 } 178