1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen 4 * {mikejc|engebret}@us.ibm.com 5 * 6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> 7 * 8 * SMP scalability work: 9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM 10 * 11 * Module name: htab.c 12 * 13 * Description: 14 * PowerPC Hashed Page Table functions 15 */ 16 17 #undef DEBUG 18 #undef DEBUG_LOW 19 20 #define pr_fmt(fmt) "hash-mmu: " fmt 21 #include <linux/spinlock.h> 22 #include <linux/errno.h> 23 #include <linux/sched/mm.h> 24 #include <linux/proc_fs.h> 25 #include <linux/stat.h> 26 #include <linux/sysctl.h> 27 #include <linux/export.h> 28 #include <linux/ctype.h> 29 #include <linux/cache.h> 30 #include <linux/init.h> 31 #include <linux/signal.h> 32 #include <linux/memblock.h> 33 #include <linux/context_tracking.h> 34 #include <linux/libfdt.h> 35 #include <linux/pkeys.h> 36 #include <linux/hugetlb.h> 37 #include <linux/cpu.h> 38 #include <linux/pgtable.h> 39 40 #include <asm/debugfs.h> 41 #include <asm/processor.h> 42 #include <asm/mmu.h> 43 #include <asm/mmu_context.h> 44 #include <asm/page.h> 45 #include <asm/types.h> 46 #include <linux/uaccess.h> 47 #include <asm/machdep.h> 48 #include <asm/prom.h> 49 #include <asm/io.h> 50 #include <asm/eeh.h> 51 #include <asm/tlb.h> 52 #include <asm/cacheflush.h> 53 #include <asm/cputable.h> 54 #include <asm/sections.h> 55 #include <asm/copro.h> 56 #include <asm/udbg.h> 57 #include <asm/code-patching.h> 58 #include <asm/fadump.h> 59 #include <asm/firmware.h> 60 #include <asm/tm.h> 61 #include <asm/trace.h> 62 #include <asm/ps3.h> 63 #include <asm/pte-walk.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/ultravisor.h> 66 67 #include <mm/mmu_decl.h> 68 69 #include "internal.h" 70 71 72 #ifdef DEBUG 73 #define DBG(fmt...) udbg_printf(fmt) 74 #else 75 #define DBG(fmt...) 76 #endif 77 78 #ifdef DEBUG_LOW 79 #define DBG_LOW(fmt...) udbg_printf(fmt) 80 #else 81 #define DBG_LOW(fmt...) 82 #endif 83 84 #define KB (1024) 85 #define MB (1024*KB) 86 #define GB (1024L*MB) 87 88 /* 89 * Note: pte --> Linux PTE 90 * HPTE --> PowerPC Hashed Page Table Entry 91 * 92 * Execution context: 93 * htab_initialize is called with the MMU off (of course), but 94 * the kernel has been copied down to zero so it can directly 95 * reference global data. At this point it is very difficult 96 * to print debug info. 97 * 98 */ 99 100 static unsigned long _SDR1; 101 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 102 EXPORT_SYMBOL_GPL(mmu_psize_defs); 103 104 u8 hpte_page_sizes[1 << LP_BITS]; 105 EXPORT_SYMBOL_GPL(hpte_page_sizes); 106 107 struct hash_pte *htab_address; 108 unsigned long htab_size_bytes; 109 unsigned long htab_hash_mask; 110 EXPORT_SYMBOL_GPL(htab_hash_mask); 111 int mmu_linear_psize = MMU_PAGE_4K; 112 EXPORT_SYMBOL_GPL(mmu_linear_psize); 113 int mmu_virtual_psize = MMU_PAGE_4K; 114 int mmu_vmalloc_psize = MMU_PAGE_4K; 115 #ifdef CONFIG_SPARSEMEM_VMEMMAP 116 int mmu_vmemmap_psize = MMU_PAGE_4K; 117 #endif 118 int mmu_io_psize = MMU_PAGE_4K; 119 int mmu_kernel_ssize = MMU_SEGSIZE_256M; 120 EXPORT_SYMBOL_GPL(mmu_kernel_ssize); 121 int mmu_highuser_ssize = MMU_SEGSIZE_256M; 122 u16 mmu_slb_size = 64; 123 EXPORT_SYMBOL_GPL(mmu_slb_size); 124 #ifdef CONFIG_PPC_64K_PAGES 125 int mmu_ci_restrictions; 126 #endif 127 #ifdef CONFIG_DEBUG_PAGEALLOC 128 static u8 *linear_map_hash_slots; 129 static unsigned long linear_map_hash_count; 130 static DEFINE_SPINLOCK(linear_map_hash_lock); 131 #endif /* CONFIG_DEBUG_PAGEALLOC */ 132 struct mmu_hash_ops mmu_hash_ops; 133 EXPORT_SYMBOL(mmu_hash_ops); 134 135 /* 136 * These are definitions of page sizes arrays to be used when none 137 * is provided by the firmware. 138 */ 139 140 /* 141 * Fallback (4k pages only) 142 */ 143 static struct mmu_psize_def mmu_psize_defaults[] = { 144 [MMU_PAGE_4K] = { 145 .shift = 12, 146 .sllp = 0, 147 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 148 .avpnm = 0, 149 .tlbiel = 0, 150 }, 151 }; 152 153 /* 154 * POWER4, GPUL, POWER5 155 * 156 * Support for 16Mb large pages 157 */ 158 static struct mmu_psize_def mmu_psize_defaults_gp[] = { 159 [MMU_PAGE_4K] = { 160 .shift = 12, 161 .sllp = 0, 162 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 163 .avpnm = 0, 164 .tlbiel = 1, 165 }, 166 [MMU_PAGE_16M] = { 167 .shift = 24, 168 .sllp = SLB_VSID_L, 169 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, 170 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, 171 .avpnm = 0x1UL, 172 .tlbiel = 0, 173 }, 174 }; 175 176 /* 177 * 'R' and 'C' update notes: 178 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* 179 * create writeable HPTEs without C set, because the hcall H_PROTECT 180 * that we use in that case will not update C 181 * - The above is however not a problem, because we also don't do that 182 * fancy "no flush" variant of eviction and we use H_REMOVE which will 183 * do the right thing and thus we don't have the race I described earlier 184 * 185 * - Under bare metal, we do have the race, so we need R and C set 186 * - We make sure R is always set and never lost 187 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping 188 */ 189 unsigned long htab_convert_pte_flags(unsigned long pteflags) 190 { 191 unsigned long rflags = 0; 192 193 /* _PAGE_EXEC -> NOEXEC */ 194 if ((pteflags & _PAGE_EXEC) == 0) 195 rflags |= HPTE_R_N; 196 /* 197 * PPP bits: 198 * Linux uses slb key 0 for kernel and 1 for user. 199 * kernel RW areas are mapped with PPP=0b000 200 * User area is mapped with PPP=0b010 for read/write 201 * or PPP=0b011 for read-only (including writeable but clean pages). 202 */ 203 if (pteflags & _PAGE_PRIVILEGED) { 204 /* 205 * Kernel read only mapped with ppp bits 0b110 206 */ 207 if (!(pteflags & _PAGE_WRITE)) { 208 if (mmu_has_feature(MMU_FTR_KERNEL_RO)) 209 rflags |= (HPTE_R_PP0 | 0x2); 210 else 211 rflags |= 0x3; 212 } 213 } else { 214 if (pteflags & _PAGE_RWX) 215 rflags |= 0x2; 216 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) 217 rflags |= 0x1; 218 } 219 /* 220 * We can't allow hardware to update hpte bits. Hence always 221 * set 'R' bit and set 'C' if it is a write fault 222 */ 223 rflags |= HPTE_R_R; 224 225 if (pteflags & _PAGE_DIRTY) 226 rflags |= HPTE_R_C; 227 /* 228 * Add in WIG bits 229 */ 230 231 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) 232 rflags |= HPTE_R_I; 233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) 234 rflags |= (HPTE_R_I | HPTE_R_G); 235 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) 236 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); 237 else 238 /* 239 * Add memory coherence if cache inhibited is not set 240 */ 241 rflags |= HPTE_R_M; 242 243 rflags |= pte_to_hpte_pkey_bits(pteflags); 244 return rflags; 245 } 246 247 int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 248 unsigned long pstart, unsigned long prot, 249 int psize, int ssize) 250 { 251 unsigned long vaddr, paddr; 252 unsigned int step, shift; 253 int ret = 0; 254 255 shift = mmu_psize_defs[psize].shift; 256 step = 1 << shift; 257 258 prot = htab_convert_pte_flags(prot); 259 260 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", 261 vstart, vend, pstart, prot, psize, ssize); 262 263 for (vaddr = vstart, paddr = pstart; vaddr < vend; 264 vaddr += step, paddr += step) { 265 unsigned long hash, hpteg; 266 unsigned long vsid = get_kernel_vsid(vaddr, ssize); 267 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); 268 unsigned long tprot = prot; 269 bool secondary_hash = false; 270 271 /* 272 * If we hit a bad address return error. 273 */ 274 if (!vsid) 275 return -1; 276 /* Make kernel text executable */ 277 if (overlaps_kernel_text(vaddr, vaddr + step)) 278 tprot &= ~HPTE_R_N; 279 280 /* 281 * If relocatable, check if it overlaps interrupt vectors that 282 * are copied down to real 0. For relocatable kernel 283 * (e.g. kdump case) we copy interrupt vectors down to real 284 * address 0. Mark that region as executable. This is 285 * because on p8 system with relocation on exception feature 286 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence 287 * in order to execute the interrupt handlers in virtual 288 * mode the vector region need to be marked as executable. 289 */ 290 if ((PHYSICAL_START > MEMORY_START) && 291 overlaps_interrupt_vector_text(vaddr, vaddr + step)) 292 tprot &= ~HPTE_R_N; 293 294 hash = hpt_hash(vpn, shift, ssize); 295 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); 296 297 BUG_ON(!mmu_hash_ops.hpte_insert); 298 repeat: 299 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 300 HPTE_V_BOLTED, psize, psize, 301 ssize); 302 if (ret == -1) { 303 /* 304 * Try to to keep bolted entries in primary. 305 * Remove non bolted entries and try insert again 306 */ 307 ret = mmu_hash_ops.hpte_remove(hpteg); 308 if (ret != -1) 309 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 310 HPTE_V_BOLTED, psize, psize, 311 ssize); 312 if (ret == -1 && !secondary_hash) { 313 secondary_hash = true; 314 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP); 315 goto repeat; 316 } 317 } 318 319 if (ret < 0) 320 break; 321 322 cond_resched(); 323 #ifdef CONFIG_DEBUG_PAGEALLOC 324 if (debug_pagealloc_enabled() && 325 (paddr >> PAGE_SHIFT) < linear_map_hash_count) 326 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; 327 #endif /* CONFIG_DEBUG_PAGEALLOC */ 328 } 329 return ret < 0 ? ret : 0; 330 } 331 332 int htab_remove_mapping(unsigned long vstart, unsigned long vend, 333 int psize, int ssize) 334 { 335 unsigned long vaddr; 336 unsigned int step, shift; 337 int rc; 338 int ret = 0; 339 340 shift = mmu_psize_defs[psize].shift; 341 step = 1 << shift; 342 343 if (!mmu_hash_ops.hpte_removebolted) 344 return -ENODEV; 345 346 for (vaddr = vstart; vaddr < vend; vaddr += step) { 347 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); 348 if (rc == -ENOENT) { 349 ret = -ENOENT; 350 continue; 351 } 352 if (rc < 0) 353 return rc; 354 } 355 356 return ret; 357 } 358 359 static bool disable_1tb_segments = false; 360 361 static int __init parse_disable_1tb_segments(char *p) 362 { 363 disable_1tb_segments = true; 364 return 0; 365 } 366 early_param("disable_1tb_segments", parse_disable_1tb_segments); 367 368 static int __init htab_dt_scan_seg_sizes(unsigned long node, 369 const char *uname, int depth, 370 void *data) 371 { 372 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 373 const __be32 *prop; 374 int size = 0; 375 376 /* We are scanning "cpu" nodes only */ 377 if (type == NULL || strcmp(type, "cpu") != 0) 378 return 0; 379 380 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); 381 if (prop == NULL) 382 return 0; 383 for (; size >= 4; size -= 4, ++prop) { 384 if (be32_to_cpu(prop[0]) == 40) { 385 DBG("1T segment support detected\n"); 386 387 if (disable_1tb_segments) { 388 DBG("1T segments disabled by command line\n"); 389 break; 390 } 391 392 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; 393 return 1; 394 } 395 } 396 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; 397 return 0; 398 } 399 400 static int __init get_idx_from_shift(unsigned int shift) 401 { 402 int idx = -1; 403 404 switch (shift) { 405 case 0xc: 406 idx = MMU_PAGE_4K; 407 break; 408 case 0x10: 409 idx = MMU_PAGE_64K; 410 break; 411 case 0x14: 412 idx = MMU_PAGE_1M; 413 break; 414 case 0x18: 415 idx = MMU_PAGE_16M; 416 break; 417 case 0x22: 418 idx = MMU_PAGE_16G; 419 break; 420 } 421 return idx; 422 } 423 424 static int __init htab_dt_scan_page_sizes(unsigned long node, 425 const char *uname, int depth, 426 void *data) 427 { 428 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 429 const __be32 *prop; 430 int size = 0; 431 432 /* We are scanning "cpu" nodes only */ 433 if (type == NULL || strcmp(type, "cpu") != 0) 434 return 0; 435 436 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); 437 if (!prop) 438 return 0; 439 440 pr_info("Page sizes from device-tree:\n"); 441 size /= 4; 442 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); 443 while(size > 0) { 444 unsigned int base_shift = be32_to_cpu(prop[0]); 445 unsigned int slbenc = be32_to_cpu(prop[1]); 446 unsigned int lpnum = be32_to_cpu(prop[2]); 447 struct mmu_psize_def *def; 448 int idx, base_idx; 449 450 size -= 3; prop += 3; 451 base_idx = get_idx_from_shift(base_shift); 452 if (base_idx < 0) { 453 /* skip the pte encoding also */ 454 prop += lpnum * 2; size -= lpnum * 2; 455 continue; 456 } 457 def = &mmu_psize_defs[base_idx]; 458 if (base_idx == MMU_PAGE_16M) 459 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; 460 461 def->shift = base_shift; 462 if (base_shift <= 23) 463 def->avpnm = 0; 464 else 465 def->avpnm = (1 << (base_shift - 23)) - 1; 466 def->sllp = slbenc; 467 /* 468 * We don't know for sure what's up with tlbiel, so 469 * for now we only set it for 4K and 64K pages 470 */ 471 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) 472 def->tlbiel = 1; 473 else 474 def->tlbiel = 0; 475 476 while (size > 0 && lpnum) { 477 unsigned int shift = be32_to_cpu(prop[0]); 478 int penc = be32_to_cpu(prop[1]); 479 480 prop += 2; size -= 2; 481 lpnum--; 482 483 idx = get_idx_from_shift(shift); 484 if (idx < 0) 485 continue; 486 487 if (penc == -1) 488 pr_err("Invalid penc for base_shift=%d " 489 "shift=%d\n", base_shift, shift); 490 491 def->penc[idx] = penc; 492 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," 493 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", 494 base_shift, shift, def->sllp, 495 def->avpnm, def->tlbiel, def->penc[idx]); 496 } 497 } 498 499 return 1; 500 } 501 502 #ifdef CONFIG_HUGETLB_PAGE 503 /* 504 * Scan for 16G memory blocks that have been set aside for huge pages 505 * and reserve those blocks for 16G huge pages. 506 */ 507 static int __init htab_dt_scan_hugepage_blocks(unsigned long node, 508 const char *uname, int depth, 509 void *data) { 510 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 511 const __be64 *addr_prop; 512 const __be32 *page_count_prop; 513 unsigned int expected_pages; 514 long unsigned int phys_addr; 515 long unsigned int block_size; 516 517 /* We are scanning "memory" nodes only */ 518 if (type == NULL || strcmp(type, "memory") != 0) 519 return 0; 520 521 /* 522 * This property is the log base 2 of the number of virtual pages that 523 * will represent this memory block. 524 */ 525 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); 526 if (page_count_prop == NULL) 527 return 0; 528 expected_pages = (1 << be32_to_cpu(page_count_prop[0])); 529 addr_prop = of_get_flat_dt_prop(node, "reg", NULL); 530 if (addr_prop == NULL) 531 return 0; 532 phys_addr = be64_to_cpu(addr_prop[0]); 533 block_size = be64_to_cpu(addr_prop[1]); 534 if (block_size != (16 * GB)) 535 return 0; 536 printk(KERN_INFO "Huge page(16GB) memory: " 537 "addr = 0x%lX size = 0x%lX pages = %d\n", 538 phys_addr, block_size, expected_pages); 539 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { 540 memblock_reserve(phys_addr, block_size * expected_pages); 541 pseries_add_gpage(phys_addr, block_size, expected_pages); 542 } 543 return 0; 544 } 545 #endif /* CONFIG_HUGETLB_PAGE */ 546 547 static void mmu_psize_set_default_penc(void) 548 { 549 int bpsize, apsize; 550 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) 551 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) 552 mmu_psize_defs[bpsize].penc[apsize] = -1; 553 } 554 555 #ifdef CONFIG_PPC_64K_PAGES 556 557 static bool might_have_hea(void) 558 { 559 /* 560 * The HEA ethernet adapter requires awareness of the 561 * GX bus. Without that awareness we can easily assume 562 * we will never see an HEA ethernet device. 563 */ 564 #ifdef CONFIG_IBMEBUS 565 return !cpu_has_feature(CPU_FTR_ARCH_207S) && 566 firmware_has_feature(FW_FEATURE_SPLPAR); 567 #else 568 return false; 569 #endif 570 } 571 572 #endif /* #ifdef CONFIG_PPC_64K_PAGES */ 573 574 static void __init htab_scan_page_sizes(void) 575 { 576 int rc; 577 578 /* se the invalid penc to -1 */ 579 mmu_psize_set_default_penc(); 580 581 /* Default to 4K pages only */ 582 memcpy(mmu_psize_defs, mmu_psize_defaults, 583 sizeof(mmu_psize_defaults)); 584 585 /* 586 * Try to find the available page sizes in the device-tree 587 */ 588 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); 589 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { 590 /* 591 * Nothing in the device-tree, but the CPU supports 16M pages, 592 * so let's fallback on a known size list for 16M capable CPUs. 593 */ 594 memcpy(mmu_psize_defs, mmu_psize_defaults_gp, 595 sizeof(mmu_psize_defaults_gp)); 596 } 597 598 #ifdef CONFIG_HUGETLB_PAGE 599 if (!hugetlb_disabled) { 600 /* Reserve 16G huge page memory sections for huge pages */ 601 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); 602 } 603 #endif /* CONFIG_HUGETLB_PAGE */ 604 } 605 606 /* 607 * Fill in the hpte_page_sizes[] array. 608 * We go through the mmu_psize_defs[] array looking for all the 609 * supported base/actual page size combinations. Each combination 610 * has a unique pagesize encoding (penc) value in the low bits of 611 * the LP field of the HPTE. For actual page sizes less than 1MB, 612 * some of the upper LP bits are used for RPN bits, meaning that 613 * we need to fill in several entries in hpte_page_sizes[]. 614 * 615 * In diagrammatic form, with r = RPN bits and z = page size bits: 616 * PTE LP actual page size 617 * rrrr rrrz >=8KB 618 * rrrr rrzz >=16KB 619 * rrrr rzzz >=32KB 620 * rrrr zzzz >=64KB 621 * ... 622 * 623 * The zzzz bits are implementation-specific but are chosen so that 624 * no encoding for a larger page size uses the same value in its 625 * low-order N bits as the encoding for the 2^(12+N) byte page size 626 * (if it exists). 627 */ 628 static void init_hpte_page_sizes(void) 629 { 630 long int ap, bp; 631 long int shift, penc; 632 633 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { 634 if (!mmu_psize_defs[bp].shift) 635 continue; /* not a supported page size */ 636 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { 637 penc = mmu_psize_defs[bp].penc[ap]; 638 if (penc == -1 || !mmu_psize_defs[ap].shift) 639 continue; 640 shift = mmu_psize_defs[ap].shift - LP_SHIFT; 641 if (shift <= 0) 642 continue; /* should never happen */ 643 /* 644 * For page sizes less than 1MB, this loop 645 * replicates the entry for all possible values 646 * of the rrrr bits. 647 */ 648 while (penc < (1 << LP_BITS)) { 649 hpte_page_sizes[penc] = (ap << 4) | bp; 650 penc += 1 << shift; 651 } 652 } 653 } 654 } 655 656 static void __init htab_init_page_sizes(void) 657 { 658 bool aligned = true; 659 init_hpte_page_sizes(); 660 661 if (!debug_pagealloc_enabled()) { 662 /* 663 * Pick a size for the linear mapping. Currently, we only 664 * support 16M, 1M and 4K which is the default 665 */ 666 if (IS_ENABLED(STRICT_KERNEL_RWX) && 667 (unsigned long)_stext % 0x1000000) { 668 if (mmu_psize_defs[MMU_PAGE_16M].shift) 669 pr_warn("Kernel not 16M aligned, " 670 "disabling 16M linear map alignment"); 671 aligned = false; 672 } 673 674 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned) 675 mmu_linear_psize = MMU_PAGE_16M; 676 else if (mmu_psize_defs[MMU_PAGE_1M].shift) 677 mmu_linear_psize = MMU_PAGE_1M; 678 } 679 680 #ifdef CONFIG_PPC_64K_PAGES 681 /* 682 * Pick a size for the ordinary pages. Default is 4K, we support 683 * 64K for user mappings and vmalloc if supported by the processor. 684 * We only use 64k for ioremap if the processor 685 * (and firmware) support cache-inhibited large pages. 686 * If not, we use 4k and set mmu_ci_restrictions so that 687 * hash_page knows to switch processes that use cache-inhibited 688 * mappings to 4k pages. 689 */ 690 if (mmu_psize_defs[MMU_PAGE_64K].shift) { 691 mmu_virtual_psize = MMU_PAGE_64K; 692 mmu_vmalloc_psize = MMU_PAGE_64K; 693 if (mmu_linear_psize == MMU_PAGE_4K) 694 mmu_linear_psize = MMU_PAGE_64K; 695 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { 696 /* 697 * When running on pSeries using 64k pages for ioremap 698 * would stop us accessing the HEA ethernet. So if we 699 * have the chance of ever seeing one, stay at 4k. 700 */ 701 if (!might_have_hea()) 702 mmu_io_psize = MMU_PAGE_64K; 703 } else 704 mmu_ci_restrictions = 1; 705 } 706 #endif /* CONFIG_PPC_64K_PAGES */ 707 708 #ifdef CONFIG_SPARSEMEM_VMEMMAP 709 /* 710 * We try to use 16M pages for vmemmap if that is supported 711 * and we have at least 1G of RAM at boot 712 */ 713 if (mmu_psize_defs[MMU_PAGE_16M].shift && 714 memblock_phys_mem_size() >= 0x40000000) 715 mmu_vmemmap_psize = MMU_PAGE_16M; 716 else 717 mmu_vmemmap_psize = mmu_virtual_psize; 718 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 719 720 printk(KERN_DEBUG "Page orders: linear mapping = %d, " 721 "virtual = %d, io = %d" 722 #ifdef CONFIG_SPARSEMEM_VMEMMAP 723 ", vmemmap = %d" 724 #endif 725 "\n", 726 mmu_psize_defs[mmu_linear_psize].shift, 727 mmu_psize_defs[mmu_virtual_psize].shift, 728 mmu_psize_defs[mmu_io_psize].shift 729 #ifdef CONFIG_SPARSEMEM_VMEMMAP 730 ,mmu_psize_defs[mmu_vmemmap_psize].shift 731 #endif 732 ); 733 } 734 735 static int __init htab_dt_scan_pftsize(unsigned long node, 736 const char *uname, int depth, 737 void *data) 738 { 739 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 740 const __be32 *prop; 741 742 /* We are scanning "cpu" nodes only */ 743 if (type == NULL || strcmp(type, "cpu") != 0) 744 return 0; 745 746 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); 747 if (prop != NULL) { 748 /* pft_size[0] is the NUMA CEC cookie */ 749 ppc64_pft_size = be32_to_cpu(prop[1]); 750 return 1; 751 } 752 return 0; 753 } 754 755 unsigned htab_shift_for_mem_size(unsigned long mem_size) 756 { 757 unsigned memshift = __ilog2(mem_size); 758 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; 759 unsigned pteg_shift; 760 761 /* round mem_size up to next power of 2 */ 762 if ((1UL << memshift) < mem_size) 763 memshift += 1; 764 765 /* aim for 2 pages / pteg */ 766 pteg_shift = memshift - (pshift + 1); 767 768 /* 769 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab 770 * size permitted by the architecture. 771 */ 772 return max(pteg_shift + 7, 18U); 773 } 774 775 static unsigned long __init htab_get_table_size(void) 776 { 777 /* 778 * If hash size isn't already provided by the platform, we try to 779 * retrieve it from the device-tree. If it's not there neither, we 780 * calculate it now based on the total RAM size 781 */ 782 if (ppc64_pft_size == 0) 783 of_scan_flat_dt(htab_dt_scan_pftsize, NULL); 784 if (ppc64_pft_size) 785 return 1UL << ppc64_pft_size; 786 787 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); 788 } 789 790 #ifdef CONFIG_MEMORY_HOTPLUG 791 int resize_hpt_for_hotplug(unsigned long new_mem_size) 792 { 793 unsigned target_hpt_shift; 794 795 if (!mmu_hash_ops.resize_hpt) 796 return 0; 797 798 target_hpt_shift = htab_shift_for_mem_size(new_mem_size); 799 800 /* 801 * To avoid lots of HPT resizes if memory size is fluctuating 802 * across a boundary, we deliberately have some hysterisis 803 * here: we immediately increase the HPT size if the target 804 * shift exceeds the current shift, but we won't attempt to 805 * reduce unless the target shift is at least 2 below the 806 * current shift 807 */ 808 if (target_hpt_shift > ppc64_pft_size || 809 target_hpt_shift < ppc64_pft_size - 1) 810 return mmu_hash_ops.resize_hpt(target_hpt_shift); 811 812 return 0; 813 } 814 815 int hash__create_section_mapping(unsigned long start, unsigned long end, 816 int nid, pgprot_t prot) 817 { 818 int rc; 819 820 if (end >= H_VMALLOC_START) { 821 pr_warn("Outside the supported range\n"); 822 return -1; 823 } 824 825 rc = htab_bolt_mapping(start, end, __pa(start), 826 pgprot_val(prot), mmu_linear_psize, 827 mmu_kernel_ssize); 828 829 if (rc < 0) { 830 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, 831 mmu_kernel_ssize); 832 BUG_ON(rc2 && (rc2 != -ENOENT)); 833 } 834 return rc; 835 } 836 837 int hash__remove_section_mapping(unsigned long start, unsigned long end) 838 { 839 int rc = htab_remove_mapping(start, end, mmu_linear_psize, 840 mmu_kernel_ssize); 841 WARN_ON(rc < 0); 842 return rc; 843 } 844 #endif /* CONFIG_MEMORY_HOTPLUG */ 845 846 static void __init hash_init_partition_table(phys_addr_t hash_table, 847 unsigned long htab_size) 848 { 849 mmu_partition_table_init(); 850 851 /* 852 * PS field (VRMA page size) is not used for LPID 0, hence set to 0. 853 * For now, UPRT is 0 and we have no segment table. 854 */ 855 htab_size = __ilog2(htab_size) - 18; 856 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false); 857 pr_info("Partition table %p\n", partition_tb); 858 } 859 860 static void __init htab_initialize(void) 861 { 862 unsigned long table; 863 unsigned long pteg_count; 864 unsigned long prot; 865 unsigned long base = 0, size = 0; 866 struct memblock_region *reg; 867 868 DBG(" -> htab_initialize()\n"); 869 870 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { 871 mmu_kernel_ssize = MMU_SEGSIZE_1T; 872 mmu_highuser_ssize = MMU_SEGSIZE_1T; 873 printk(KERN_INFO "Using 1TB segments\n"); 874 } 875 876 if (stress_slb_enabled) 877 static_branch_enable(&stress_slb_key); 878 879 /* 880 * Calculate the required size of the htab. We want the number of 881 * PTEGs to equal one half the number of real pages. 882 */ 883 htab_size_bytes = htab_get_table_size(); 884 pteg_count = htab_size_bytes >> 7; 885 886 htab_hash_mask = pteg_count - 1; 887 888 if (firmware_has_feature(FW_FEATURE_LPAR) || 889 firmware_has_feature(FW_FEATURE_PS3_LV1)) { 890 /* Using a hypervisor which owns the htab */ 891 htab_address = NULL; 892 _SDR1 = 0; 893 #ifdef CONFIG_FA_DUMP 894 /* 895 * If firmware assisted dump is active firmware preserves 896 * the contents of htab along with entire partition memory. 897 * Clear the htab if firmware assisted dump is active so 898 * that we dont end up using old mappings. 899 */ 900 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) 901 mmu_hash_ops.hpte_clear_all(); 902 #endif 903 } else { 904 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; 905 906 #ifdef CONFIG_PPC_CELL 907 /* 908 * Cell may require the hash table down low when using the 909 * Axon IOMMU in order to fit the dynamic region over it, see 910 * comments in cell/iommu.c 911 */ 912 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { 913 limit = 0x80000000; 914 pr_info("Hash table forced below 2G for Axon IOMMU\n"); 915 } 916 #endif /* CONFIG_PPC_CELL */ 917 918 table = memblock_phys_alloc_range(htab_size_bytes, 919 htab_size_bytes, 920 0, limit); 921 if (!table) 922 panic("ERROR: Failed to allocate %pa bytes below %pa\n", 923 &htab_size_bytes, &limit); 924 925 DBG("Hash table allocated at %lx, size: %lx\n", table, 926 htab_size_bytes); 927 928 htab_address = __va(table); 929 930 /* htab absolute addr + encoded htabsize */ 931 _SDR1 = table + __ilog2(htab_size_bytes) - 18; 932 933 /* Initialize the HPT with no entries */ 934 memset((void *)table, 0, htab_size_bytes); 935 936 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 937 /* Set SDR1 */ 938 mtspr(SPRN_SDR1, _SDR1); 939 else 940 hash_init_partition_table(table, htab_size_bytes); 941 } 942 943 prot = pgprot_val(PAGE_KERNEL); 944 945 #ifdef CONFIG_DEBUG_PAGEALLOC 946 if (debug_pagealloc_enabled()) { 947 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; 948 linear_map_hash_slots = memblock_alloc_try_nid( 949 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, 950 ppc64_rma_size, NUMA_NO_NODE); 951 if (!linear_map_hash_slots) 952 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", 953 __func__, linear_map_hash_count, &ppc64_rma_size); 954 } 955 #endif /* CONFIG_DEBUG_PAGEALLOC */ 956 957 /* create bolted the linear mapping in the hash table */ 958 for_each_memblock(memory, reg) { 959 base = (unsigned long)__va(reg->base); 960 size = reg->size; 961 962 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", 963 base, size, prot); 964 965 if ((base + size) >= H_VMALLOC_START) { 966 pr_warn("Outside the supported range\n"); 967 continue; 968 } 969 970 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), 971 prot, mmu_linear_psize, mmu_kernel_ssize)); 972 } 973 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); 974 975 /* 976 * If we have a memory_limit and we've allocated TCEs then we need to 977 * explicitly map the TCE area at the top of RAM. We also cope with the 978 * case that the TCEs start below memory_limit. 979 * tce_alloc_start/end are 16MB aligned so the mapping should work 980 * for either 4K or 16MB pages. 981 */ 982 if (tce_alloc_start) { 983 tce_alloc_start = (unsigned long)__va(tce_alloc_start); 984 tce_alloc_end = (unsigned long)__va(tce_alloc_end); 985 986 if (base + size >= tce_alloc_start) 987 tce_alloc_start = base + size + 1; 988 989 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, 990 __pa(tce_alloc_start), prot, 991 mmu_linear_psize, mmu_kernel_ssize)); 992 } 993 994 995 DBG(" <- htab_initialize()\n"); 996 } 997 #undef KB 998 #undef MB 999 1000 void __init hash__early_init_devtree(void) 1001 { 1002 /* Initialize segment sizes */ 1003 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); 1004 1005 /* Initialize page sizes */ 1006 htab_scan_page_sizes(); 1007 } 1008 1009 static struct hash_mm_context init_hash_mm_context; 1010 void __init hash__early_init_mmu(void) 1011 { 1012 #ifndef CONFIG_PPC_64K_PAGES 1013 /* 1014 * We have code in __hash_page_4K() and elsewhere, which assumes it can 1015 * do the following: 1016 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); 1017 * 1018 * Where the slot number is between 0-15, and values of 8-15 indicate 1019 * the secondary bucket. For that code to work H_PAGE_F_SECOND and 1020 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and 1021 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here 1022 * with a BUILD_BUG_ON(). 1023 */ 1024 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); 1025 #endif /* CONFIG_PPC_64K_PAGES */ 1026 1027 htab_init_page_sizes(); 1028 1029 /* 1030 * initialize page table size 1031 */ 1032 __pte_frag_nr = H_PTE_FRAG_NR; 1033 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; 1034 __pmd_frag_nr = H_PMD_FRAG_NR; 1035 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; 1036 1037 __pte_index_size = H_PTE_INDEX_SIZE; 1038 __pmd_index_size = H_PMD_INDEX_SIZE; 1039 __pud_index_size = H_PUD_INDEX_SIZE; 1040 __pgd_index_size = H_PGD_INDEX_SIZE; 1041 __pud_cache_index = H_PUD_CACHE_INDEX; 1042 __pte_table_size = H_PTE_TABLE_SIZE; 1043 __pmd_table_size = H_PMD_TABLE_SIZE; 1044 __pud_table_size = H_PUD_TABLE_SIZE; 1045 __pgd_table_size = H_PGD_TABLE_SIZE; 1046 /* 1047 * 4k use hugepd format, so for hash set then to 1048 * zero 1049 */ 1050 __pmd_val_bits = HASH_PMD_VAL_BITS; 1051 __pud_val_bits = HASH_PUD_VAL_BITS; 1052 __pgd_val_bits = HASH_PGD_VAL_BITS; 1053 1054 __kernel_virt_start = H_KERN_VIRT_START; 1055 __vmalloc_start = H_VMALLOC_START; 1056 __vmalloc_end = H_VMALLOC_END; 1057 __kernel_io_start = H_KERN_IO_START; 1058 __kernel_io_end = H_KERN_IO_END; 1059 vmemmap = (struct page *)H_VMEMMAP_START; 1060 ioremap_bot = IOREMAP_BASE; 1061 1062 #ifdef CONFIG_PCI 1063 pci_io_base = ISA_IO_BASE; 1064 #endif 1065 1066 /* Select appropriate backend */ 1067 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) 1068 ps3_early_mm_init(); 1069 else if (firmware_has_feature(FW_FEATURE_LPAR)) 1070 hpte_init_pseries(); 1071 else if (IS_ENABLED(CONFIG_PPC_NATIVE)) 1072 hpte_init_native(); 1073 1074 if (!mmu_hash_ops.hpte_insert) 1075 panic("hash__early_init_mmu: No MMU hash ops defined!\n"); 1076 1077 /* 1078 * Initialize the MMU Hash table and create the linear mapping 1079 * of memory. Has to be done before SLB initialization as this is 1080 * currently where the page size encoding is obtained. 1081 */ 1082 htab_initialize(); 1083 1084 init_mm.context.hash_context = &init_hash_mm_context; 1085 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT); 1086 1087 pr_info("Initializing hash mmu with SLB\n"); 1088 /* Initialize SLB management */ 1089 slb_initialize(); 1090 1091 if (cpu_has_feature(CPU_FTR_ARCH_206) 1092 && cpu_has_feature(CPU_FTR_HVMODE)) 1093 tlbiel_all(); 1094 } 1095 1096 #ifdef CONFIG_SMP 1097 void hash__early_init_mmu_secondary(void) 1098 { 1099 /* Initialize hash table for that CPU */ 1100 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 1101 1102 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1103 mtspr(SPRN_SDR1, _SDR1); 1104 else 1105 set_ptcr_when_no_uv(__pa(partition_tb) | 1106 (PATB_SIZE_SHIFT - 12)); 1107 } 1108 /* Initialize SLB */ 1109 slb_initialize(); 1110 1111 if (cpu_has_feature(CPU_FTR_ARCH_206) 1112 && cpu_has_feature(CPU_FTR_HVMODE)) 1113 tlbiel_all(); 1114 } 1115 #endif /* CONFIG_SMP */ 1116 1117 /* 1118 * Called by asm hashtable.S for doing lazy icache flush 1119 */ 1120 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) 1121 { 1122 struct page *page; 1123 1124 if (!pfn_valid(pte_pfn(pte))) 1125 return pp; 1126 1127 page = pte_page(pte); 1128 1129 /* page is dirty */ 1130 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { 1131 if (trap == 0x400) { 1132 flush_dcache_icache_page(page); 1133 set_bit(PG_arch_1, &page->flags); 1134 } else 1135 pp |= HPTE_R_N; 1136 } 1137 return pp; 1138 } 1139 1140 #ifdef CONFIG_PPC_MM_SLICES 1141 static unsigned int get_paca_psize(unsigned long addr) 1142 { 1143 unsigned char *psizes; 1144 unsigned long index, mask_index; 1145 1146 if (addr < SLICE_LOW_TOP) { 1147 psizes = get_paca()->mm_ctx_low_slices_psize; 1148 index = GET_LOW_SLICE_INDEX(addr); 1149 } else { 1150 psizes = get_paca()->mm_ctx_high_slices_psize; 1151 index = GET_HIGH_SLICE_INDEX(addr); 1152 } 1153 mask_index = index & 0x1; 1154 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; 1155 } 1156 1157 #else 1158 unsigned int get_paca_psize(unsigned long addr) 1159 { 1160 return get_paca()->mm_ctx_user_psize; 1161 } 1162 #endif 1163 1164 /* 1165 * Demote a segment to using 4k pages. 1166 * For now this makes the whole process use 4k pages. 1167 */ 1168 #ifdef CONFIG_PPC_64K_PAGES 1169 void demote_segment_4k(struct mm_struct *mm, unsigned long addr) 1170 { 1171 if (get_slice_psize(mm, addr) == MMU_PAGE_4K) 1172 return; 1173 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); 1174 copro_flush_all_slbs(mm); 1175 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { 1176 1177 copy_mm_to_paca(mm); 1178 slb_flush_and_restore_bolted(); 1179 } 1180 } 1181 #endif /* CONFIG_PPC_64K_PAGES */ 1182 1183 #ifdef CONFIG_PPC_SUBPAGE_PROT 1184 /* 1185 * This looks up a 2-bit protection code for a 4k subpage of a 64k page. 1186 * Userspace sets the subpage permissions using the subpage_prot system call. 1187 * 1188 * Result is 0: full permissions, _PAGE_RW: read-only, 1189 * _PAGE_RWX: no access. 1190 */ 1191 static int subpage_protection(struct mm_struct *mm, unsigned long ea) 1192 { 1193 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context); 1194 u32 spp = 0; 1195 u32 **sbpm, *sbpp; 1196 1197 if (!spt) 1198 return 0; 1199 1200 if (ea >= spt->maxaddr) 1201 return 0; 1202 if (ea < 0x100000000UL) { 1203 /* addresses below 4GB use spt->low_prot */ 1204 sbpm = spt->low_prot; 1205 } else { 1206 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; 1207 if (!sbpm) 1208 return 0; 1209 } 1210 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; 1211 if (!sbpp) 1212 return 0; 1213 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; 1214 1215 /* extract 2-bit bitfield for this 4k subpage */ 1216 spp >>= 30 - 2 * ((ea >> 12) & 0xf); 1217 1218 /* 1219 * 0 -> full premission 1220 * 1 -> Read only 1221 * 2 -> no access. 1222 * We return the flag that need to be cleared. 1223 */ 1224 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); 1225 return spp; 1226 } 1227 1228 #else /* CONFIG_PPC_SUBPAGE_PROT */ 1229 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) 1230 { 1231 return 0; 1232 } 1233 #endif 1234 1235 void hash_failure_debug(unsigned long ea, unsigned long access, 1236 unsigned long vsid, unsigned long trap, 1237 int ssize, int psize, int lpsize, unsigned long pte) 1238 { 1239 if (!printk_ratelimit()) 1240 return; 1241 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", 1242 ea, access, current->comm); 1243 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", 1244 trap, vsid, ssize, psize, lpsize, pte); 1245 } 1246 1247 static void check_paca_psize(unsigned long ea, struct mm_struct *mm, 1248 int psize, bool user_region) 1249 { 1250 if (user_region) { 1251 if (psize != get_paca_psize(ea)) { 1252 copy_mm_to_paca(mm); 1253 slb_flush_and_restore_bolted(); 1254 } 1255 } else if (get_paca()->vmalloc_sllp != 1256 mmu_psize_defs[mmu_vmalloc_psize].sllp) { 1257 get_paca()->vmalloc_sllp = 1258 mmu_psize_defs[mmu_vmalloc_psize].sllp; 1259 slb_vmalloc_update(); 1260 } 1261 } 1262 1263 /* 1264 * Result code is: 1265 * 0 - handled 1266 * 1 - normal page fault 1267 * -1 - critical hash insertion error 1268 * -2 - access not permitted by subpage protection mechanism 1269 */ 1270 int hash_page_mm(struct mm_struct *mm, unsigned long ea, 1271 unsigned long access, unsigned long trap, 1272 unsigned long flags) 1273 { 1274 bool is_thp; 1275 enum ctx_state prev_state = exception_enter(); 1276 pgd_t *pgdir; 1277 unsigned long vsid; 1278 pte_t *ptep; 1279 unsigned hugeshift; 1280 int rc, user_region = 0; 1281 int psize, ssize; 1282 1283 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", 1284 ea, access, trap); 1285 trace_hash_fault(ea, access, trap); 1286 1287 /* Get region & vsid */ 1288 switch (get_region_id(ea)) { 1289 case USER_REGION_ID: 1290 user_region = 1; 1291 if (! mm) { 1292 DBG_LOW(" user region with no mm !\n"); 1293 rc = 1; 1294 goto bail; 1295 } 1296 psize = get_slice_psize(mm, ea); 1297 ssize = user_segment_size(ea); 1298 vsid = get_user_vsid(&mm->context, ea, ssize); 1299 break; 1300 case VMALLOC_REGION_ID: 1301 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1302 psize = mmu_vmalloc_psize; 1303 ssize = mmu_kernel_ssize; 1304 break; 1305 1306 case IO_REGION_ID: 1307 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1308 psize = mmu_io_psize; 1309 ssize = mmu_kernel_ssize; 1310 break; 1311 default: 1312 /* 1313 * Not a valid range 1314 * Send the problem up to do_page_fault() 1315 */ 1316 rc = 1; 1317 goto bail; 1318 } 1319 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); 1320 1321 /* Bad address. */ 1322 if (!vsid) { 1323 DBG_LOW("Bad address!\n"); 1324 rc = 1; 1325 goto bail; 1326 } 1327 /* Get pgdir */ 1328 pgdir = mm->pgd; 1329 if (pgdir == NULL) { 1330 rc = 1; 1331 goto bail; 1332 } 1333 1334 /* Check CPU locality */ 1335 if (user_region && mm_is_thread_local(mm)) 1336 flags |= HPTE_LOCAL_UPDATE; 1337 1338 #ifndef CONFIG_PPC_64K_PAGES 1339 /* 1340 * If we use 4K pages and our psize is not 4K, then we might 1341 * be hitting a special driver mapping, and need to align the 1342 * address before we fetch the PTE. 1343 * 1344 * It could also be a hugepage mapping, in which case this is 1345 * not necessary, but it's not harmful, either. 1346 */ 1347 if (psize != MMU_PAGE_4K) 1348 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); 1349 #endif /* CONFIG_PPC_64K_PAGES */ 1350 1351 /* Get PTE and page size from page tables */ 1352 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); 1353 if (ptep == NULL || !pte_present(*ptep)) { 1354 DBG_LOW(" no PTE !\n"); 1355 rc = 1; 1356 goto bail; 1357 } 1358 1359 /* 1360 * Add _PAGE_PRESENT to the required access perm. If there are parallel 1361 * updates to the pte that can possibly clear _PAGE_PTE, catch that too. 1362 * 1363 * We can safely use the return pte address in rest of the function 1364 * because we do set H_PAGE_BUSY which prevents further updates to pte 1365 * from generic code. 1366 */ 1367 access |= _PAGE_PRESENT | _PAGE_PTE; 1368 1369 /* 1370 * Pre-check access permissions (will be re-checked atomically 1371 * in __hash_page_XX but this pre-check is a fast path 1372 */ 1373 if (!check_pte_access(access, pte_val(*ptep))) { 1374 DBG_LOW(" no access !\n"); 1375 rc = 1; 1376 goto bail; 1377 } 1378 1379 if (hugeshift) { 1380 if (is_thp) 1381 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, 1382 trap, flags, ssize, psize); 1383 #ifdef CONFIG_HUGETLB_PAGE 1384 else 1385 rc = __hash_page_huge(ea, access, vsid, ptep, trap, 1386 flags, ssize, hugeshift, psize); 1387 #else 1388 else { 1389 /* 1390 * if we have hugeshift, and is not transhuge with 1391 * hugetlb disabled, something is really wrong. 1392 */ 1393 rc = 1; 1394 WARN_ON(1); 1395 } 1396 #endif 1397 if (current->mm == mm) 1398 check_paca_psize(ea, mm, psize, user_region); 1399 1400 goto bail; 1401 } 1402 1403 #ifndef CONFIG_PPC_64K_PAGES 1404 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); 1405 #else 1406 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), 1407 pte_val(*(ptep + PTRS_PER_PTE))); 1408 #endif 1409 /* Do actual hashing */ 1410 #ifdef CONFIG_PPC_64K_PAGES 1411 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ 1412 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { 1413 demote_segment_4k(mm, ea); 1414 psize = MMU_PAGE_4K; 1415 } 1416 1417 /* 1418 * If this PTE is non-cacheable and we have restrictions on 1419 * using non cacheable large pages, then we switch to 4k 1420 */ 1421 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { 1422 if (user_region) { 1423 demote_segment_4k(mm, ea); 1424 psize = MMU_PAGE_4K; 1425 } else if (ea < VMALLOC_END) { 1426 /* 1427 * some driver did a non-cacheable mapping 1428 * in vmalloc space, so switch vmalloc 1429 * to 4k pages 1430 */ 1431 printk(KERN_ALERT "Reducing vmalloc segment " 1432 "to 4kB pages because of " 1433 "non-cacheable mapping\n"); 1434 psize = mmu_vmalloc_psize = MMU_PAGE_4K; 1435 copro_flush_all_slbs(mm); 1436 } 1437 } 1438 1439 #endif /* CONFIG_PPC_64K_PAGES */ 1440 1441 if (current->mm == mm) 1442 check_paca_psize(ea, mm, psize, user_region); 1443 1444 #ifdef CONFIG_PPC_64K_PAGES 1445 if (psize == MMU_PAGE_64K) 1446 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1447 flags, ssize); 1448 else 1449 #endif /* CONFIG_PPC_64K_PAGES */ 1450 { 1451 int spp = subpage_protection(mm, ea); 1452 if (access & spp) 1453 rc = -2; 1454 else 1455 rc = __hash_page_4K(ea, access, vsid, ptep, trap, 1456 flags, ssize, spp); 1457 } 1458 1459 /* 1460 * Dump some info in case of hash insertion failure, they should 1461 * never happen so it is really useful to know if/when they do 1462 */ 1463 if (rc == -1) 1464 hash_failure_debug(ea, access, vsid, trap, ssize, psize, 1465 psize, pte_val(*ptep)); 1466 #ifndef CONFIG_PPC_64K_PAGES 1467 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); 1468 #else 1469 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), 1470 pte_val(*(ptep + PTRS_PER_PTE))); 1471 #endif 1472 DBG_LOW(" -> rc=%d\n", rc); 1473 1474 bail: 1475 exception_exit(prev_state); 1476 return rc; 1477 } 1478 EXPORT_SYMBOL_GPL(hash_page_mm); 1479 1480 int hash_page(unsigned long ea, unsigned long access, unsigned long trap, 1481 unsigned long dsisr) 1482 { 1483 unsigned long flags = 0; 1484 struct mm_struct *mm = current->mm; 1485 1486 if ((get_region_id(ea) == VMALLOC_REGION_ID) || 1487 (get_region_id(ea) == IO_REGION_ID)) 1488 mm = &init_mm; 1489 1490 if (dsisr & DSISR_NOHPTE) 1491 flags |= HPTE_NOHPTE_UPDATE; 1492 1493 return hash_page_mm(mm, ea, access, trap, flags); 1494 } 1495 EXPORT_SYMBOL_GPL(hash_page); 1496 1497 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr, 1498 unsigned long msr) 1499 { 1500 unsigned long access = _PAGE_PRESENT | _PAGE_READ; 1501 unsigned long flags = 0; 1502 struct mm_struct *mm = current->mm; 1503 unsigned int region_id = get_region_id(ea); 1504 1505 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) 1506 mm = &init_mm; 1507 1508 if (dsisr & DSISR_NOHPTE) 1509 flags |= HPTE_NOHPTE_UPDATE; 1510 1511 if (dsisr & DSISR_ISSTORE) 1512 access |= _PAGE_WRITE; 1513 /* 1514 * We set _PAGE_PRIVILEGED only when 1515 * kernel mode access kernel space. 1516 * 1517 * _PAGE_PRIVILEGED is NOT set 1518 * 1) when kernel mode access user space 1519 * 2) user space access kernel space. 1520 */ 1521 access |= _PAGE_PRIVILEGED; 1522 if ((msr & MSR_PR) || (region_id == USER_REGION_ID)) 1523 access &= ~_PAGE_PRIVILEGED; 1524 1525 if (trap == 0x400) 1526 access |= _PAGE_EXEC; 1527 1528 return hash_page_mm(mm, ea, access, trap, flags); 1529 } 1530 1531 #ifdef CONFIG_PPC_MM_SLICES 1532 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1533 { 1534 int psize = get_slice_psize(mm, ea); 1535 1536 /* We only prefault standard pages for now */ 1537 if (unlikely(psize != mm_ctx_user_psize(&mm->context))) 1538 return false; 1539 1540 /* 1541 * Don't prefault if subpage protection is enabled for the EA. 1542 */ 1543 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) 1544 return false; 1545 1546 return true; 1547 } 1548 #else 1549 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1550 { 1551 return true; 1552 } 1553 #endif 1554 1555 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea, 1556 bool is_exec, unsigned long trap) 1557 { 1558 unsigned long vsid; 1559 pgd_t *pgdir; 1560 int rc, ssize, update_flags = 0; 1561 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0); 1562 1563 BUG_ON(get_region_id(ea) != USER_REGION_ID); 1564 1565 if (!should_hash_preload(mm, ea)) 1566 return; 1567 1568 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," 1569 " trap=%lx\n", mm, mm->pgd, ea, access, trap); 1570 1571 /* Get Linux PTE if available */ 1572 pgdir = mm->pgd; 1573 if (pgdir == NULL) 1574 return; 1575 1576 /* Get VSID */ 1577 ssize = user_segment_size(ea); 1578 vsid = get_user_vsid(&mm->context, ea, ssize); 1579 if (!vsid) 1580 return; 1581 1582 #ifdef CONFIG_PPC_64K_PAGES 1583 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on 1584 * a 64K kernel), then we don't preload, hash_page() will take 1585 * care of it once we actually try to access the page. 1586 * That way we don't have to duplicate all of the logic for segment 1587 * page size demotion here 1588 * Called with PTL held, hence can be sure the value won't change in 1589 * between. 1590 */ 1591 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) 1592 return; 1593 #endif /* CONFIG_PPC_64K_PAGES */ 1594 1595 /* Is that local to this CPU ? */ 1596 if (mm_is_thread_local(mm)) 1597 update_flags |= HPTE_LOCAL_UPDATE; 1598 1599 /* Hash it in */ 1600 #ifdef CONFIG_PPC_64K_PAGES 1601 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K) 1602 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1603 update_flags, ssize); 1604 else 1605 #endif /* CONFIG_PPC_64K_PAGES */ 1606 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, 1607 ssize, subpage_protection(mm, ea)); 1608 1609 /* Dump some info in case of hash insertion failure, they should 1610 * never happen so it is really useful to know if/when they do 1611 */ 1612 if (rc == -1) 1613 hash_failure_debug(ea, access, vsid, trap, ssize, 1614 mm_ctx_user_psize(&mm->context), 1615 mm_ctx_user_psize(&mm->context), 1616 pte_val(*ptep)); 1617 } 1618 1619 /* 1620 * This is called at the end of handling a user page fault, when the 1621 * fault has been handled by updating a PTE in the linux page tables. 1622 * We use it to preload an HPTE into the hash table corresponding to 1623 * the updated linux PTE. 1624 * 1625 * This must always be called with the pte lock held. 1626 */ 1627 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1628 pte_t *ptep) 1629 { 1630 /* 1631 * We don't need to worry about _PAGE_PRESENT here because we are 1632 * called with either mm->page_table_lock held or ptl lock held 1633 */ 1634 unsigned long trap; 1635 bool is_exec; 1636 1637 if (radix_enabled()) 1638 return; 1639 1640 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 1641 if (!pte_young(*ptep) || address >= TASK_SIZE) 1642 return; 1643 1644 /* 1645 * We try to figure out if we are coming from an instruction 1646 * access fault and pass that down to __hash_page so we avoid 1647 * double-faulting on execution of fresh text. We have to test 1648 * for regs NULL since init will get here first thing at boot. 1649 * 1650 * We also avoid filling the hash if not coming from a fault. 1651 */ 1652 1653 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL; 1654 switch (trap) { 1655 case 0x300: 1656 is_exec = false; 1657 break; 1658 case 0x400: 1659 is_exec = true; 1660 break; 1661 default: 1662 return; 1663 } 1664 1665 hash_preload(vma->vm_mm, ptep, address, is_exec, trap); 1666 } 1667 1668 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1669 static inline void tm_flush_hash_page(int local) 1670 { 1671 /* 1672 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a 1673 * page back to a block device w/PIO could pick up transactional data 1674 * (bad!) so we force an abort here. Before the sync the page will be 1675 * made read-only, which will flush_hash_page. BIG ISSUE here: if the 1676 * kernel uses a page from userspace without unmapping it first, it may 1677 * see the speculated version. 1678 */ 1679 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && 1680 MSR_TM_ACTIVE(current->thread.regs->msr)) { 1681 tm_enable(); 1682 tm_abort(TM_CAUSE_TLBI); 1683 } 1684 } 1685 #else 1686 static inline void tm_flush_hash_page(int local) 1687 { 1688 } 1689 #endif 1690 1691 /* 1692 * Return the global hash slot, corresponding to the given PTE, which contains 1693 * the HPTE. 1694 */ 1695 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, 1696 int ssize, real_pte_t rpte, unsigned int subpg_index) 1697 { 1698 unsigned long hash, gslot, hidx; 1699 1700 hash = hpt_hash(vpn, shift, ssize); 1701 hidx = __rpte_to_hidx(rpte, subpg_index); 1702 if (hidx & _PTEIDX_SECONDARY) 1703 hash = ~hash; 1704 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1705 gslot += hidx & _PTEIDX_GROUP_IX; 1706 return gslot; 1707 } 1708 1709 /* 1710 * WARNING: This is called from hash_low_64.S, if you change this prototype, 1711 * do not forget to update the assembly call site ! 1712 */ 1713 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, 1714 unsigned long flags) 1715 { 1716 unsigned long index, shift, gslot; 1717 int local = flags & HPTE_LOCAL_UPDATE; 1718 1719 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); 1720 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { 1721 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); 1722 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); 1723 /* 1724 * We use same base page size and actual psize, because we don't 1725 * use these functions for hugepage 1726 */ 1727 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, 1728 ssize, local); 1729 } pte_iterate_hashed_end(); 1730 1731 tm_flush_hash_page(local); 1732 } 1733 1734 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1735 void flush_hash_hugepage(unsigned long vsid, unsigned long addr, 1736 pmd_t *pmdp, unsigned int psize, int ssize, 1737 unsigned long flags) 1738 { 1739 int i, max_hpte_count, valid; 1740 unsigned long s_addr; 1741 unsigned char *hpte_slot_array; 1742 unsigned long hidx, shift, vpn, hash, slot; 1743 int local = flags & HPTE_LOCAL_UPDATE; 1744 1745 s_addr = addr & HPAGE_PMD_MASK; 1746 hpte_slot_array = get_hpte_slot_array(pmdp); 1747 /* 1748 * IF we try to do a HUGE PTE update after a withdraw is done. 1749 * we will find the below NULL. This happens when we do 1750 * split_huge_pmd 1751 */ 1752 if (!hpte_slot_array) 1753 return; 1754 1755 if (mmu_hash_ops.hugepage_invalidate) { 1756 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, 1757 psize, ssize, local); 1758 goto tm_abort; 1759 } 1760 /* 1761 * No bluk hpte removal support, invalidate each entry 1762 */ 1763 shift = mmu_psize_defs[psize].shift; 1764 max_hpte_count = HPAGE_PMD_SIZE >> shift; 1765 for (i = 0; i < max_hpte_count; i++) { 1766 /* 1767 * 8 bits per each hpte entries 1768 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] 1769 */ 1770 valid = hpte_valid(hpte_slot_array, i); 1771 if (!valid) 1772 continue; 1773 hidx = hpte_hash_index(hpte_slot_array, i); 1774 1775 /* get the vpn */ 1776 addr = s_addr + (i * (1ul << shift)); 1777 vpn = hpt_vpn(addr, vsid, ssize); 1778 hash = hpt_hash(vpn, shift, ssize); 1779 if (hidx & _PTEIDX_SECONDARY) 1780 hash = ~hash; 1781 1782 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1783 slot += hidx & _PTEIDX_GROUP_IX; 1784 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, 1785 MMU_PAGE_16M, ssize, local); 1786 } 1787 tm_abort: 1788 tm_flush_hash_page(local); 1789 } 1790 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1791 1792 void flush_hash_range(unsigned long number, int local) 1793 { 1794 if (mmu_hash_ops.flush_hash_range) 1795 mmu_hash_ops.flush_hash_range(number, local); 1796 else { 1797 int i; 1798 struct ppc64_tlb_batch *batch = 1799 this_cpu_ptr(&ppc64_tlb_batch); 1800 1801 for (i = 0; i < number; i++) 1802 flush_hash_page(batch->vpn[i], batch->pte[i], 1803 batch->psize, batch->ssize, local); 1804 } 1805 } 1806 1807 /* 1808 * low_hash_fault is called when we the low level hash code failed 1809 * to instert a PTE due to an hypervisor error 1810 */ 1811 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) 1812 { 1813 enum ctx_state prev_state = exception_enter(); 1814 1815 if (user_mode(regs)) { 1816 #ifdef CONFIG_PPC_SUBPAGE_PROT 1817 if (rc == -2) 1818 _exception(SIGSEGV, regs, SEGV_ACCERR, address); 1819 else 1820 #endif 1821 _exception(SIGBUS, regs, BUS_ADRERR, address); 1822 } else 1823 bad_page_fault(regs, address, SIGBUS); 1824 1825 exception_exit(prev_state); 1826 } 1827 1828 long hpte_insert_repeating(unsigned long hash, unsigned long vpn, 1829 unsigned long pa, unsigned long rflags, 1830 unsigned long vflags, int psize, int ssize) 1831 { 1832 unsigned long hpte_group; 1833 long slot; 1834 1835 repeat: 1836 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1837 1838 /* Insert into the hash table, primary slot */ 1839 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, 1840 psize, psize, ssize); 1841 1842 /* Primary is full, try the secondary */ 1843 if (unlikely(slot == -1)) { 1844 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; 1845 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, 1846 vflags | HPTE_V_SECONDARY, 1847 psize, psize, ssize); 1848 if (slot == -1) { 1849 if (mftb() & 0x1) 1850 hpte_group = (hash & htab_hash_mask) * 1851 HPTES_PER_GROUP; 1852 1853 mmu_hash_ops.hpte_remove(hpte_group); 1854 goto repeat; 1855 } 1856 } 1857 1858 return slot; 1859 } 1860 1861 #ifdef CONFIG_DEBUG_PAGEALLOC 1862 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) 1863 { 1864 unsigned long hash; 1865 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1866 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1867 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); 1868 long ret; 1869 1870 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1871 1872 /* Don't create HPTE entries for bad address */ 1873 if (!vsid) 1874 return; 1875 1876 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, 1877 HPTE_V_BOLTED, 1878 mmu_linear_psize, mmu_kernel_ssize); 1879 1880 BUG_ON (ret < 0); 1881 spin_lock(&linear_map_hash_lock); 1882 BUG_ON(linear_map_hash_slots[lmi] & 0x80); 1883 linear_map_hash_slots[lmi] = ret | 0x80; 1884 spin_unlock(&linear_map_hash_lock); 1885 } 1886 1887 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) 1888 { 1889 unsigned long hash, hidx, slot; 1890 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1891 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1892 1893 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1894 spin_lock(&linear_map_hash_lock); 1895 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); 1896 hidx = linear_map_hash_slots[lmi] & 0x7f; 1897 linear_map_hash_slots[lmi] = 0; 1898 spin_unlock(&linear_map_hash_lock); 1899 if (hidx & _PTEIDX_SECONDARY) 1900 hash = ~hash; 1901 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1902 slot += hidx & _PTEIDX_GROUP_IX; 1903 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, 1904 mmu_linear_psize, 1905 mmu_kernel_ssize, 0); 1906 } 1907 1908 void __kernel_map_pages(struct page *page, int numpages, int enable) 1909 { 1910 unsigned long flags, vaddr, lmi; 1911 int i; 1912 1913 local_irq_save(flags); 1914 for (i = 0; i < numpages; i++, page++) { 1915 vaddr = (unsigned long)page_address(page); 1916 lmi = __pa(vaddr) >> PAGE_SHIFT; 1917 if (lmi >= linear_map_hash_count) 1918 continue; 1919 if (enable) 1920 kernel_map_linear_page(vaddr, lmi); 1921 else 1922 kernel_unmap_linear_page(vaddr, lmi); 1923 } 1924 local_irq_restore(flags); 1925 } 1926 #endif /* CONFIG_DEBUG_PAGEALLOC */ 1927 1928 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 1929 phys_addr_t first_memblock_size) 1930 { 1931 /* 1932 * We don't currently support the first MEMBLOCK not mapping 0 1933 * physical on those processors 1934 */ 1935 BUG_ON(first_memblock_base != 0); 1936 1937 /* 1938 * On virtualized systems the first entry is our RMA region aka VRMA, 1939 * non-virtualized 64-bit hash MMU systems don't have a limitation 1940 * on real mode access. 1941 * 1942 * For guests on platforms before POWER9, we clamp the it limit to 1G 1943 * to avoid some funky things such as RTAS bugs etc... 1944 * 1945 * On POWER9 we limit to 1TB in case the host erroneously told us that 1946 * the RMA was >1TB. Effective address bits 0:23 are treated as zero 1947 * (meaning the access is aliased to zero i.e. addr = addr % 1TB) 1948 * for virtual real mode addressing and so it doesn't make sense to 1949 * have an area larger than 1TB as it can't be addressed. 1950 */ 1951 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { 1952 ppc64_rma_size = first_memblock_size; 1953 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) 1954 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); 1955 else 1956 ppc64_rma_size = min_t(u64, ppc64_rma_size, 1957 1UL << SID_SHIFT_1T); 1958 1959 /* Finally limit subsequent allocations */ 1960 memblock_set_current_limit(ppc64_rma_size); 1961 } else { 1962 ppc64_rma_size = ULONG_MAX; 1963 } 1964 } 1965 1966 #ifdef CONFIG_DEBUG_FS 1967 1968 static int hpt_order_get(void *data, u64 *val) 1969 { 1970 *val = ppc64_pft_size; 1971 return 0; 1972 } 1973 1974 static int hpt_order_set(void *data, u64 val) 1975 { 1976 int ret; 1977 1978 if (!mmu_hash_ops.resize_hpt) 1979 return -ENODEV; 1980 1981 cpus_read_lock(); 1982 ret = mmu_hash_ops.resize_hpt(val); 1983 cpus_read_unlock(); 1984 1985 return ret; 1986 } 1987 1988 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); 1989 1990 static int __init hash64_debugfs(void) 1991 { 1992 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL, 1993 &fops_hpt_order); 1994 return 0; 1995 } 1996 machine_device_initcall(pseries, hash64_debugfs); 1997 #endif /* CONFIG_DEBUG_FS */ 1998 1999 void __init print_system_hash_info(void) 2000 { 2001 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 2002 2003 if (htab_hash_mask) 2004 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 2005 } 2006