1 /* 2 * Single-step support. 3 * 4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/kprobes.h> 13 #include <linux/ptrace.h> 14 #include <linux/prefetch.h> 15 #include <asm/sstep.h> 16 #include <asm/processor.h> 17 #include <linux/uaccess.h> 18 #include <asm/cpu_has_feature.h> 19 #include <asm/cputable.h> 20 21 extern char system_call_common[]; 22 23 #ifdef CONFIG_PPC64 24 /* Bits in SRR1 that are copied from MSR */ 25 #define MSR_MASK 0xffffffff87c0ffffUL 26 #else 27 #define MSR_MASK 0x87c0ffff 28 #endif 29 30 /* Bits in XER */ 31 #define XER_SO 0x80000000U 32 #define XER_OV 0x40000000U 33 #define XER_CA 0x20000000U 34 #define XER_OV32 0x00080000U 35 #define XER_CA32 0x00040000U 36 37 #ifdef CONFIG_PPC_FPU 38 /* 39 * Functions in ldstfp.S 40 */ 41 extern void get_fpr(int rn, double *p); 42 extern void put_fpr(int rn, const double *p); 43 extern void get_vr(int rn, __vector128 *p); 44 extern void put_vr(int rn, __vector128 *p); 45 extern void load_vsrn(int vsr, const void *p); 46 extern void store_vsrn(int vsr, void *p); 47 extern void conv_sp_to_dp(const float *sp, double *dp); 48 extern void conv_dp_to_sp(const double *dp, float *sp); 49 #endif 50 51 #ifdef __powerpc64__ 52 /* 53 * Functions in quad.S 54 */ 55 extern int do_lq(unsigned long ea, unsigned long *regs); 56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1); 57 extern int do_lqarx(unsigned long ea, unsigned long *regs); 58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1, 59 unsigned int *crp); 60 #endif 61 62 #ifdef __LITTLE_ENDIAN__ 63 #define IS_LE 1 64 #define IS_BE 0 65 #else 66 #define IS_LE 0 67 #define IS_BE 1 68 #endif 69 70 /* 71 * Emulate the truncation of 64 bit values in 32-bit mode. 72 */ 73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, 74 unsigned long val) 75 { 76 #ifdef __powerpc64__ 77 if ((msr & MSR_64BIT) == 0) 78 val &= 0xffffffffUL; 79 #endif 80 return val; 81 } 82 83 /* 84 * Determine whether a conditional branch instruction would branch. 85 */ 86 static nokprobe_inline int branch_taken(unsigned int instr, 87 const struct pt_regs *regs, 88 struct instruction_op *op) 89 { 90 unsigned int bo = (instr >> 21) & 0x1f; 91 unsigned int bi; 92 93 if ((bo & 4) == 0) { 94 /* decrement counter */ 95 op->type |= DECCTR; 96 if (((bo >> 1) & 1) ^ (regs->ctr == 1)) 97 return 0; 98 } 99 if ((bo & 0x10) == 0) { 100 /* check bit from CR */ 101 bi = (instr >> 16) & 0x1f; 102 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) 103 return 0; 104 } 105 return 1; 106 } 107 108 static nokprobe_inline long address_ok(struct pt_regs *regs, 109 unsigned long ea, int nb) 110 { 111 if (!user_mode(regs)) 112 return 1; 113 if (__access_ok(ea, nb, USER_DS)) 114 return 1; 115 if (__access_ok(ea, 1, USER_DS)) 116 /* Access overlaps the end of the user region */ 117 regs->dar = USER_DS.seg; 118 else 119 regs->dar = ea; 120 return 0; 121 } 122 123 /* 124 * Calculate effective address for a D-form instruction 125 */ 126 static nokprobe_inline unsigned long dform_ea(unsigned int instr, 127 const struct pt_regs *regs) 128 { 129 int ra; 130 unsigned long ea; 131 132 ra = (instr >> 16) & 0x1f; 133 ea = (signed short) instr; /* sign-extend */ 134 if (ra) 135 ea += regs->gpr[ra]; 136 137 return ea; 138 } 139 140 #ifdef __powerpc64__ 141 /* 142 * Calculate effective address for a DS-form instruction 143 */ 144 static nokprobe_inline unsigned long dsform_ea(unsigned int instr, 145 const struct pt_regs *regs) 146 { 147 int ra; 148 unsigned long ea; 149 150 ra = (instr >> 16) & 0x1f; 151 ea = (signed short) (instr & ~3); /* sign-extend */ 152 if (ra) 153 ea += regs->gpr[ra]; 154 155 return ea; 156 } 157 158 /* 159 * Calculate effective address for a DQ-form instruction 160 */ 161 static nokprobe_inline unsigned long dqform_ea(unsigned int instr, 162 const struct pt_regs *regs) 163 { 164 int ra; 165 unsigned long ea; 166 167 ra = (instr >> 16) & 0x1f; 168 ea = (signed short) (instr & ~0xf); /* sign-extend */ 169 if (ra) 170 ea += regs->gpr[ra]; 171 172 return ea; 173 } 174 #endif /* __powerpc64 */ 175 176 /* 177 * Calculate effective address for an X-form instruction 178 */ 179 static nokprobe_inline unsigned long xform_ea(unsigned int instr, 180 const struct pt_regs *regs) 181 { 182 int ra, rb; 183 unsigned long ea; 184 185 ra = (instr >> 16) & 0x1f; 186 rb = (instr >> 11) & 0x1f; 187 ea = regs->gpr[rb]; 188 if (ra) 189 ea += regs->gpr[ra]; 190 191 return ea; 192 } 193 194 /* 195 * Return the largest power of 2, not greater than sizeof(unsigned long), 196 * such that x is a multiple of it. 197 */ 198 static nokprobe_inline unsigned long max_align(unsigned long x) 199 { 200 x |= sizeof(unsigned long); 201 return x & -x; /* isolates rightmost bit */ 202 } 203 204 static nokprobe_inline unsigned long byterev_2(unsigned long x) 205 { 206 return ((x >> 8) & 0xff) | ((x & 0xff) << 8); 207 } 208 209 static nokprobe_inline unsigned long byterev_4(unsigned long x) 210 { 211 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | 212 ((x & 0xff00) << 8) | ((x & 0xff) << 24); 213 } 214 215 #ifdef __powerpc64__ 216 static nokprobe_inline unsigned long byterev_8(unsigned long x) 217 { 218 return (byterev_4(x) << 32) | byterev_4(x >> 32); 219 } 220 #endif 221 222 static nokprobe_inline void do_byte_reverse(void *ptr, int nb) 223 { 224 switch (nb) { 225 case 2: 226 *(u16 *)ptr = byterev_2(*(u16 *)ptr); 227 break; 228 case 4: 229 *(u32 *)ptr = byterev_4(*(u32 *)ptr); 230 break; 231 #ifdef __powerpc64__ 232 case 8: 233 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr); 234 break; 235 case 16: { 236 unsigned long *up = (unsigned long *)ptr; 237 unsigned long tmp; 238 tmp = byterev_8(up[0]); 239 up[0] = byterev_8(up[1]); 240 up[1] = tmp; 241 break; 242 } 243 #endif 244 default: 245 WARN_ON_ONCE(1); 246 } 247 } 248 249 static nokprobe_inline int read_mem_aligned(unsigned long *dest, 250 unsigned long ea, int nb, 251 struct pt_regs *regs) 252 { 253 int err = 0; 254 unsigned long x = 0; 255 256 switch (nb) { 257 case 1: 258 err = __get_user(x, (unsigned char __user *) ea); 259 break; 260 case 2: 261 err = __get_user(x, (unsigned short __user *) ea); 262 break; 263 case 4: 264 err = __get_user(x, (unsigned int __user *) ea); 265 break; 266 #ifdef __powerpc64__ 267 case 8: 268 err = __get_user(x, (unsigned long __user *) ea); 269 break; 270 #endif 271 } 272 if (!err) 273 *dest = x; 274 else 275 regs->dar = ea; 276 return err; 277 } 278 279 /* 280 * Copy from userspace to a buffer, using the largest possible 281 * aligned accesses, up to sizeof(long). 282 */ 283 static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb, 284 struct pt_regs *regs) 285 { 286 int err = 0; 287 int c; 288 289 for (; nb > 0; nb -= c) { 290 c = max_align(ea); 291 if (c > nb) 292 c = max_align(nb); 293 switch (c) { 294 case 1: 295 err = __get_user(*dest, (unsigned char __user *) ea); 296 break; 297 case 2: 298 err = __get_user(*(u16 *)dest, 299 (unsigned short __user *) ea); 300 break; 301 case 4: 302 err = __get_user(*(u32 *)dest, 303 (unsigned int __user *) ea); 304 break; 305 #ifdef __powerpc64__ 306 case 8: 307 err = __get_user(*(unsigned long *)dest, 308 (unsigned long __user *) ea); 309 break; 310 #endif 311 } 312 if (err) { 313 regs->dar = ea; 314 return err; 315 } 316 dest += c; 317 ea += c; 318 } 319 return 0; 320 } 321 322 static nokprobe_inline int read_mem_unaligned(unsigned long *dest, 323 unsigned long ea, int nb, 324 struct pt_regs *regs) 325 { 326 union { 327 unsigned long ul; 328 u8 b[sizeof(unsigned long)]; 329 } u; 330 int i; 331 int err; 332 333 u.ul = 0; 334 i = IS_BE ? sizeof(unsigned long) - nb : 0; 335 err = copy_mem_in(&u.b[i], ea, nb, regs); 336 if (!err) 337 *dest = u.ul; 338 return err; 339 } 340 341 /* 342 * Read memory at address ea for nb bytes, return 0 for success 343 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 344 * If nb < sizeof(long), the result is right-justified on BE systems. 345 */ 346 static int read_mem(unsigned long *dest, unsigned long ea, int nb, 347 struct pt_regs *regs) 348 { 349 if (!address_ok(regs, ea, nb)) 350 return -EFAULT; 351 if ((ea & (nb - 1)) == 0) 352 return read_mem_aligned(dest, ea, nb, regs); 353 return read_mem_unaligned(dest, ea, nb, regs); 354 } 355 NOKPROBE_SYMBOL(read_mem); 356 357 static nokprobe_inline int write_mem_aligned(unsigned long val, 358 unsigned long ea, int nb, 359 struct pt_regs *regs) 360 { 361 int err = 0; 362 363 switch (nb) { 364 case 1: 365 err = __put_user(val, (unsigned char __user *) ea); 366 break; 367 case 2: 368 err = __put_user(val, (unsigned short __user *) ea); 369 break; 370 case 4: 371 err = __put_user(val, (unsigned int __user *) ea); 372 break; 373 #ifdef __powerpc64__ 374 case 8: 375 err = __put_user(val, (unsigned long __user *) ea); 376 break; 377 #endif 378 } 379 if (err) 380 regs->dar = ea; 381 return err; 382 } 383 384 /* 385 * Copy from a buffer to userspace, using the largest possible 386 * aligned accesses, up to sizeof(long). 387 */ 388 static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb, 389 struct pt_regs *regs) 390 { 391 int err = 0; 392 int c; 393 394 for (; nb > 0; nb -= c) { 395 c = max_align(ea); 396 if (c > nb) 397 c = max_align(nb); 398 switch (c) { 399 case 1: 400 err = __put_user(*dest, (unsigned char __user *) ea); 401 break; 402 case 2: 403 err = __put_user(*(u16 *)dest, 404 (unsigned short __user *) ea); 405 break; 406 case 4: 407 err = __put_user(*(u32 *)dest, 408 (unsigned int __user *) ea); 409 break; 410 #ifdef __powerpc64__ 411 case 8: 412 err = __put_user(*(unsigned long *)dest, 413 (unsigned long __user *) ea); 414 break; 415 #endif 416 } 417 if (err) { 418 regs->dar = ea; 419 return err; 420 } 421 dest += c; 422 ea += c; 423 } 424 return 0; 425 } 426 427 static nokprobe_inline int write_mem_unaligned(unsigned long val, 428 unsigned long ea, int nb, 429 struct pt_regs *regs) 430 { 431 union { 432 unsigned long ul; 433 u8 b[sizeof(unsigned long)]; 434 } u; 435 int i; 436 437 u.ul = val; 438 i = IS_BE ? sizeof(unsigned long) - nb : 0; 439 return copy_mem_out(&u.b[i], ea, nb, regs); 440 } 441 442 /* 443 * Write memory at address ea for nb bytes, return 0 for success 444 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 445 */ 446 static int write_mem(unsigned long val, unsigned long ea, int nb, 447 struct pt_regs *regs) 448 { 449 if (!address_ok(regs, ea, nb)) 450 return -EFAULT; 451 if ((ea & (nb - 1)) == 0) 452 return write_mem_aligned(val, ea, nb, regs); 453 return write_mem_unaligned(val, ea, nb, regs); 454 } 455 NOKPROBE_SYMBOL(write_mem); 456 457 #ifdef CONFIG_PPC_FPU 458 /* 459 * These access either the real FP register or the image in the 460 * thread_struct, depending on regs->msr & MSR_FP. 461 */ 462 static int do_fp_load(struct instruction_op *op, unsigned long ea, 463 struct pt_regs *regs, bool cross_endian) 464 { 465 int err, rn, nb; 466 union { 467 int i; 468 unsigned int u; 469 float f; 470 double d[2]; 471 unsigned long l[2]; 472 u8 b[2 * sizeof(double)]; 473 } u; 474 475 nb = GETSIZE(op->type); 476 if (!address_ok(regs, ea, nb)) 477 return -EFAULT; 478 rn = op->reg; 479 err = copy_mem_in(u.b, ea, nb, regs); 480 if (err) 481 return err; 482 if (unlikely(cross_endian)) { 483 do_byte_reverse(u.b, min(nb, 8)); 484 if (nb == 16) 485 do_byte_reverse(&u.b[8], 8); 486 } 487 preempt_disable(); 488 if (nb == 4) { 489 if (op->type & FPCONV) 490 conv_sp_to_dp(&u.f, &u.d[0]); 491 else if (op->type & SIGNEXT) 492 u.l[0] = u.i; 493 else 494 u.l[0] = u.u; 495 } 496 if (regs->msr & MSR_FP) 497 put_fpr(rn, &u.d[0]); 498 else 499 current->thread.TS_FPR(rn) = u.l[0]; 500 if (nb == 16) { 501 /* lfdp */ 502 rn |= 1; 503 if (regs->msr & MSR_FP) 504 put_fpr(rn, &u.d[1]); 505 else 506 current->thread.TS_FPR(rn) = u.l[1]; 507 } 508 preempt_enable(); 509 return 0; 510 } 511 NOKPROBE_SYMBOL(do_fp_load); 512 513 static int do_fp_store(struct instruction_op *op, unsigned long ea, 514 struct pt_regs *regs, bool cross_endian) 515 { 516 int rn, nb; 517 union { 518 unsigned int u; 519 float f; 520 double d[2]; 521 unsigned long l[2]; 522 u8 b[2 * sizeof(double)]; 523 } u; 524 525 nb = GETSIZE(op->type); 526 if (!address_ok(regs, ea, nb)) 527 return -EFAULT; 528 rn = op->reg; 529 preempt_disable(); 530 if (regs->msr & MSR_FP) 531 get_fpr(rn, &u.d[0]); 532 else 533 u.l[0] = current->thread.TS_FPR(rn); 534 if (nb == 4) { 535 if (op->type & FPCONV) 536 conv_dp_to_sp(&u.d[0], &u.f); 537 else 538 u.u = u.l[0]; 539 } 540 if (nb == 16) { 541 rn |= 1; 542 if (regs->msr & MSR_FP) 543 get_fpr(rn, &u.d[1]); 544 else 545 u.l[1] = current->thread.TS_FPR(rn); 546 } 547 preempt_enable(); 548 if (unlikely(cross_endian)) { 549 do_byte_reverse(u.b, min(nb, 8)); 550 if (nb == 16) 551 do_byte_reverse(&u.b[8], 8); 552 } 553 return copy_mem_out(u.b, ea, nb, regs); 554 } 555 NOKPROBE_SYMBOL(do_fp_store); 556 #endif 557 558 #ifdef CONFIG_ALTIVEC 559 /* For Altivec/VMX, no need to worry about alignment */ 560 static nokprobe_inline int do_vec_load(int rn, unsigned long ea, 561 int size, struct pt_regs *regs, 562 bool cross_endian) 563 { 564 int err; 565 union { 566 __vector128 v; 567 u8 b[sizeof(__vector128)]; 568 } u = {}; 569 570 if (!address_ok(regs, ea & ~0xfUL, 16)) 571 return -EFAULT; 572 /* align to multiple of size */ 573 ea &= ~(size - 1); 574 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs); 575 if (err) 576 return err; 577 if (unlikely(cross_endian)) 578 do_byte_reverse(&u.b[ea & 0xf], size); 579 preempt_disable(); 580 if (regs->msr & MSR_VEC) 581 put_vr(rn, &u.v); 582 else 583 current->thread.vr_state.vr[rn] = u.v; 584 preempt_enable(); 585 return 0; 586 } 587 588 static nokprobe_inline int do_vec_store(int rn, unsigned long ea, 589 int size, struct pt_regs *regs, 590 bool cross_endian) 591 { 592 union { 593 __vector128 v; 594 u8 b[sizeof(__vector128)]; 595 } u; 596 597 if (!address_ok(regs, ea & ~0xfUL, 16)) 598 return -EFAULT; 599 /* align to multiple of size */ 600 ea &= ~(size - 1); 601 602 preempt_disable(); 603 if (regs->msr & MSR_VEC) 604 get_vr(rn, &u.v); 605 else 606 u.v = current->thread.vr_state.vr[rn]; 607 preempt_enable(); 608 if (unlikely(cross_endian)) 609 do_byte_reverse(&u.b[ea & 0xf], size); 610 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs); 611 } 612 #endif /* CONFIG_ALTIVEC */ 613 614 #ifdef __powerpc64__ 615 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea, 616 int reg, bool cross_endian) 617 { 618 int err; 619 620 if (!address_ok(regs, ea, 16)) 621 return -EFAULT; 622 /* if aligned, should be atomic */ 623 if ((ea & 0xf) == 0) { 624 err = do_lq(ea, ®s->gpr[reg]); 625 } else { 626 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); 627 if (!err) 628 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); 629 } 630 if (!err && unlikely(cross_endian)) 631 do_byte_reverse(®s->gpr[reg], 16); 632 return err; 633 } 634 635 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea, 636 int reg, bool cross_endian) 637 { 638 int err; 639 unsigned long vals[2]; 640 641 if (!address_ok(regs, ea, 16)) 642 return -EFAULT; 643 vals[0] = regs->gpr[reg]; 644 vals[1] = regs->gpr[reg + 1]; 645 if (unlikely(cross_endian)) 646 do_byte_reverse(vals, 16); 647 648 /* if aligned, should be atomic */ 649 if ((ea & 0xf) == 0) 650 return do_stq(ea, vals[0], vals[1]); 651 652 err = write_mem(vals[IS_LE], ea, 8, regs); 653 if (!err) 654 err = write_mem(vals[IS_BE], ea + 8, 8, regs); 655 return err; 656 } 657 #endif /* __powerpc64 */ 658 659 #ifdef CONFIG_VSX 660 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 661 const void *mem, bool rev) 662 { 663 int size, read_size; 664 int i, j; 665 const unsigned int *wp; 666 const unsigned short *hp; 667 const unsigned char *bp; 668 669 size = GETSIZE(op->type); 670 reg->d[0] = reg->d[1] = 0; 671 672 switch (op->element_size) { 673 case 16: 674 /* whole vector; lxv[x] or lxvl[l] */ 675 if (size == 0) 676 break; 677 memcpy(reg, mem, size); 678 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 679 rev = !rev; 680 if (rev) 681 do_byte_reverse(reg, 16); 682 break; 683 case 8: 684 /* scalar loads, lxvd2x, lxvdsx */ 685 read_size = (size >= 8) ? 8 : size; 686 i = IS_LE ? 8 : 8 - read_size; 687 memcpy(®->b[i], mem, read_size); 688 if (rev) 689 do_byte_reverse(®->b[i], 8); 690 if (size < 8) { 691 if (op->type & SIGNEXT) { 692 /* size == 4 is the only case here */ 693 reg->d[IS_LE] = (signed int) reg->d[IS_LE]; 694 } else if (op->vsx_flags & VSX_FPCONV) { 695 preempt_disable(); 696 conv_sp_to_dp(®->fp[1 + IS_LE], 697 ®->dp[IS_LE]); 698 preempt_enable(); 699 } 700 } else { 701 if (size == 16) { 702 unsigned long v = *(unsigned long *)(mem + 8); 703 reg->d[IS_BE] = !rev ? v : byterev_8(v); 704 } else if (op->vsx_flags & VSX_SPLAT) 705 reg->d[IS_BE] = reg->d[IS_LE]; 706 } 707 break; 708 case 4: 709 /* lxvw4x, lxvwsx */ 710 wp = mem; 711 for (j = 0; j < size / 4; ++j) { 712 i = IS_LE ? 3 - j : j; 713 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); 714 } 715 if (op->vsx_flags & VSX_SPLAT) { 716 u32 val = reg->w[IS_LE ? 3 : 0]; 717 for (; j < 4; ++j) { 718 i = IS_LE ? 3 - j : j; 719 reg->w[i] = val; 720 } 721 } 722 break; 723 case 2: 724 /* lxvh8x */ 725 hp = mem; 726 for (j = 0; j < size / 2; ++j) { 727 i = IS_LE ? 7 - j : j; 728 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++); 729 } 730 break; 731 case 1: 732 /* lxvb16x */ 733 bp = mem; 734 for (j = 0; j < size; ++j) { 735 i = IS_LE ? 15 - j : j; 736 reg->b[i] = *bp++; 737 } 738 break; 739 } 740 } 741 EXPORT_SYMBOL_GPL(emulate_vsx_load); 742 NOKPROBE_SYMBOL(emulate_vsx_load); 743 744 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, 745 void *mem, bool rev) 746 { 747 int size, write_size; 748 int i, j; 749 union vsx_reg buf; 750 unsigned int *wp; 751 unsigned short *hp; 752 unsigned char *bp; 753 754 size = GETSIZE(op->type); 755 756 switch (op->element_size) { 757 case 16: 758 /* stxv, stxvx, stxvl, stxvll */ 759 if (size == 0) 760 break; 761 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 762 rev = !rev; 763 if (rev) { 764 /* reverse 16 bytes */ 765 buf.d[0] = byterev_8(reg->d[1]); 766 buf.d[1] = byterev_8(reg->d[0]); 767 reg = &buf; 768 } 769 memcpy(mem, reg, size); 770 break; 771 case 8: 772 /* scalar stores, stxvd2x */ 773 write_size = (size >= 8) ? 8 : size; 774 i = IS_LE ? 8 : 8 - write_size; 775 if (size < 8 && op->vsx_flags & VSX_FPCONV) { 776 buf.d[0] = buf.d[1] = 0; 777 preempt_disable(); 778 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); 779 preempt_enable(); 780 reg = &buf; 781 } 782 memcpy(mem, ®->b[i], write_size); 783 if (size == 16) 784 memcpy(mem + 8, ®->d[IS_BE], 8); 785 if (unlikely(rev)) { 786 do_byte_reverse(mem, write_size); 787 if (size == 16) 788 do_byte_reverse(mem + 8, 8); 789 } 790 break; 791 case 4: 792 /* stxvw4x */ 793 wp = mem; 794 for (j = 0; j < size / 4; ++j) { 795 i = IS_LE ? 3 - j : j; 796 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); 797 } 798 break; 799 case 2: 800 /* stxvh8x */ 801 hp = mem; 802 for (j = 0; j < size / 2; ++j) { 803 i = IS_LE ? 7 - j : j; 804 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]); 805 } 806 break; 807 case 1: 808 /* stvxb16x */ 809 bp = mem; 810 for (j = 0; j < size; ++j) { 811 i = IS_LE ? 15 - j : j; 812 *bp++ = reg->b[i]; 813 } 814 break; 815 } 816 } 817 EXPORT_SYMBOL_GPL(emulate_vsx_store); 818 NOKPROBE_SYMBOL(emulate_vsx_store); 819 820 static nokprobe_inline int do_vsx_load(struct instruction_op *op, 821 unsigned long ea, struct pt_regs *regs, 822 bool cross_endian) 823 { 824 int reg = op->reg; 825 u8 mem[16]; 826 union vsx_reg buf; 827 int size = GETSIZE(op->type); 828 829 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) 830 return -EFAULT; 831 832 emulate_vsx_load(op, &buf, mem, cross_endian); 833 preempt_disable(); 834 if (reg < 32) { 835 /* FP regs + extensions */ 836 if (regs->msr & MSR_FP) { 837 load_vsrn(reg, &buf); 838 } else { 839 current->thread.fp_state.fpr[reg][0] = buf.d[0]; 840 current->thread.fp_state.fpr[reg][1] = buf.d[1]; 841 } 842 } else { 843 if (regs->msr & MSR_VEC) 844 load_vsrn(reg, &buf); 845 else 846 current->thread.vr_state.vr[reg - 32] = buf.v; 847 } 848 preempt_enable(); 849 return 0; 850 } 851 852 static nokprobe_inline int do_vsx_store(struct instruction_op *op, 853 unsigned long ea, struct pt_regs *regs, 854 bool cross_endian) 855 { 856 int reg = op->reg; 857 u8 mem[16]; 858 union vsx_reg buf; 859 int size = GETSIZE(op->type); 860 861 if (!address_ok(regs, ea, size)) 862 return -EFAULT; 863 864 preempt_disable(); 865 if (reg < 32) { 866 /* FP regs + extensions */ 867 if (regs->msr & MSR_FP) { 868 store_vsrn(reg, &buf); 869 } else { 870 buf.d[0] = current->thread.fp_state.fpr[reg][0]; 871 buf.d[1] = current->thread.fp_state.fpr[reg][1]; 872 } 873 } else { 874 if (regs->msr & MSR_VEC) 875 store_vsrn(reg, &buf); 876 else 877 buf.v = current->thread.vr_state.vr[reg - 32]; 878 } 879 preempt_enable(); 880 emulate_vsx_store(op, &buf, mem, cross_endian); 881 return copy_mem_out(mem, ea, size, regs); 882 } 883 #endif /* CONFIG_VSX */ 884 885 int emulate_dcbz(unsigned long ea, struct pt_regs *regs) 886 { 887 int err; 888 unsigned long i, size; 889 890 #ifdef __powerpc64__ 891 size = ppc64_caches.l1d.block_size; 892 if (!(regs->msr & MSR_64BIT)) 893 ea &= 0xffffffffUL; 894 #else 895 size = L1_CACHE_BYTES; 896 #endif 897 ea &= ~(size - 1); 898 if (!address_ok(regs, ea, size)) 899 return -EFAULT; 900 for (i = 0; i < size; i += sizeof(long)) { 901 err = __put_user(0, (unsigned long __user *) (ea + i)); 902 if (err) { 903 regs->dar = ea; 904 return err; 905 } 906 } 907 return 0; 908 } 909 NOKPROBE_SYMBOL(emulate_dcbz); 910 911 #define __put_user_asmx(x, addr, err, op, cr) \ 912 __asm__ __volatile__( \ 913 "1: " op " %2,0,%3\n" \ 914 " mfcr %1\n" \ 915 "2:\n" \ 916 ".section .fixup,\"ax\"\n" \ 917 "3: li %0,%4\n" \ 918 " b 2b\n" \ 919 ".previous\n" \ 920 EX_TABLE(1b, 3b) \ 921 : "=r" (err), "=r" (cr) \ 922 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) 923 924 #define __get_user_asmx(x, addr, err, op) \ 925 __asm__ __volatile__( \ 926 "1: "op" %1,0,%2\n" \ 927 "2:\n" \ 928 ".section .fixup,\"ax\"\n" \ 929 "3: li %0,%3\n" \ 930 " b 2b\n" \ 931 ".previous\n" \ 932 EX_TABLE(1b, 3b) \ 933 : "=r" (err), "=r" (x) \ 934 : "r" (addr), "i" (-EFAULT), "0" (err)) 935 936 #define __cacheop_user_asmx(addr, err, op) \ 937 __asm__ __volatile__( \ 938 "1: "op" 0,%1\n" \ 939 "2:\n" \ 940 ".section .fixup,\"ax\"\n" \ 941 "3: li %0,%3\n" \ 942 " b 2b\n" \ 943 ".previous\n" \ 944 EX_TABLE(1b, 3b) \ 945 : "=r" (err) \ 946 : "r" (addr), "i" (-EFAULT), "0" (err)) 947 948 static nokprobe_inline void set_cr0(const struct pt_regs *regs, 949 struct instruction_op *op) 950 { 951 long val = op->val; 952 953 op->type |= SETCC; 954 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); 955 #ifdef __powerpc64__ 956 if (!(regs->msr & MSR_64BIT)) 957 val = (int) val; 958 #endif 959 if (val < 0) 960 op->ccval |= 0x80000000; 961 else if (val > 0) 962 op->ccval |= 0x40000000; 963 else 964 op->ccval |= 0x20000000; 965 } 966 967 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val) 968 { 969 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 970 if (val) 971 op->xerval |= XER_CA32; 972 else 973 op->xerval &= ~XER_CA32; 974 } 975 } 976 977 static nokprobe_inline void add_with_carry(const struct pt_regs *regs, 978 struct instruction_op *op, int rd, 979 unsigned long val1, unsigned long val2, 980 unsigned long carry_in) 981 { 982 unsigned long val = val1 + val2; 983 984 if (carry_in) 985 ++val; 986 op->type = COMPUTE + SETREG + SETXER; 987 op->reg = rd; 988 op->val = val; 989 #ifdef __powerpc64__ 990 if (!(regs->msr & MSR_64BIT)) { 991 val = (unsigned int) val; 992 val1 = (unsigned int) val1; 993 } 994 #endif 995 op->xerval = regs->xer; 996 if (val < val1 || (carry_in && val == val1)) 997 op->xerval |= XER_CA; 998 else 999 op->xerval &= ~XER_CA; 1000 1001 set_ca32(op, (unsigned int)val < (unsigned int)val1 || 1002 (carry_in && (unsigned int)val == (unsigned int)val1)); 1003 } 1004 1005 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs, 1006 struct instruction_op *op, 1007 long v1, long v2, int crfld) 1008 { 1009 unsigned int crval, shift; 1010 1011 op->type = COMPUTE + SETCC; 1012 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1013 if (v1 < v2) 1014 crval |= 8; 1015 else if (v1 > v2) 1016 crval |= 4; 1017 else 1018 crval |= 2; 1019 shift = (7 - crfld) * 4; 1020 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1021 } 1022 1023 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs, 1024 struct instruction_op *op, 1025 unsigned long v1, 1026 unsigned long v2, int crfld) 1027 { 1028 unsigned int crval, shift; 1029 1030 op->type = COMPUTE + SETCC; 1031 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1032 if (v1 < v2) 1033 crval |= 8; 1034 else if (v1 > v2) 1035 crval |= 4; 1036 else 1037 crval |= 2; 1038 shift = (7 - crfld) * 4; 1039 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1040 } 1041 1042 static nokprobe_inline void do_cmpb(const struct pt_regs *regs, 1043 struct instruction_op *op, 1044 unsigned long v1, unsigned long v2) 1045 { 1046 unsigned long long out_val, mask; 1047 int i; 1048 1049 out_val = 0; 1050 for (i = 0; i < 8; i++) { 1051 mask = 0xffUL << (i * 8); 1052 if ((v1 & mask) == (v2 & mask)) 1053 out_val |= mask; 1054 } 1055 op->val = out_val; 1056 } 1057 1058 /* 1059 * The size parameter is used to adjust the equivalent popcnt instruction. 1060 * popcntb = 8, popcntw = 32, popcntd = 64 1061 */ 1062 static nokprobe_inline void do_popcnt(const struct pt_regs *regs, 1063 struct instruction_op *op, 1064 unsigned long v1, int size) 1065 { 1066 unsigned long long out = v1; 1067 1068 out -= (out >> 1) & 0x5555555555555555; 1069 out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2)); 1070 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f; 1071 1072 if (size == 8) { /* popcntb */ 1073 op->val = out; 1074 return; 1075 } 1076 out += out >> 8; 1077 out += out >> 16; 1078 if (size == 32) { /* popcntw */ 1079 op->val = out & 0x0000003f0000003f; 1080 return; 1081 } 1082 1083 out = (out + (out >> 32)) & 0x7f; 1084 op->val = out; /* popcntd */ 1085 } 1086 1087 #ifdef CONFIG_PPC64 1088 static nokprobe_inline void do_bpermd(const struct pt_regs *regs, 1089 struct instruction_op *op, 1090 unsigned long v1, unsigned long v2) 1091 { 1092 unsigned char perm, idx; 1093 unsigned int i; 1094 1095 perm = 0; 1096 for (i = 0; i < 8; i++) { 1097 idx = (v1 >> (i * 8)) & 0xff; 1098 if (idx < 64) 1099 if (v2 & PPC_BIT(idx)) 1100 perm |= 1 << i; 1101 } 1102 op->val = perm; 1103 } 1104 #endif /* CONFIG_PPC64 */ 1105 /* 1106 * The size parameter adjusts the equivalent prty instruction. 1107 * prtyw = 32, prtyd = 64 1108 */ 1109 static nokprobe_inline void do_prty(const struct pt_regs *regs, 1110 struct instruction_op *op, 1111 unsigned long v, int size) 1112 { 1113 unsigned long long res = v ^ (v >> 8); 1114 1115 res ^= res >> 16; 1116 if (size == 32) { /* prtyw */ 1117 op->val = res & 0x0000000100000001; 1118 return; 1119 } 1120 1121 res ^= res >> 32; 1122 op->val = res & 1; /*prtyd */ 1123 } 1124 1125 static nokprobe_inline int trap_compare(long v1, long v2) 1126 { 1127 int ret = 0; 1128 1129 if (v1 < v2) 1130 ret |= 0x10; 1131 else if (v1 > v2) 1132 ret |= 0x08; 1133 else 1134 ret |= 0x04; 1135 if ((unsigned long)v1 < (unsigned long)v2) 1136 ret |= 0x02; 1137 else if ((unsigned long)v1 > (unsigned long)v2) 1138 ret |= 0x01; 1139 return ret; 1140 } 1141 1142 /* 1143 * Elements of 32-bit rotate and mask instructions. 1144 */ 1145 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ 1146 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) 1147 #ifdef __powerpc64__ 1148 #define MASK64_L(mb) (~0UL >> (mb)) 1149 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) 1150 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) 1151 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) 1152 #else 1153 #define DATA32(x) (x) 1154 #endif 1155 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) 1156 1157 /* 1158 * Decode an instruction, and return information about it in *op 1159 * without changing *regs. 1160 * Integer arithmetic and logical instructions, branches, and barrier 1161 * instructions can be emulated just using the information in *op. 1162 * 1163 * Return value is 1 if the instruction can be emulated just by 1164 * updating *regs with the information in *op, -1 if we need the 1165 * GPRs but *regs doesn't contain the full register set, or 0 1166 * otherwise. 1167 */ 1168 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 1169 unsigned int instr) 1170 { 1171 unsigned int opcode, ra, rb, rd, spr, u; 1172 unsigned long int imm; 1173 unsigned long int val, val2; 1174 unsigned int mb, me, sh; 1175 long ival; 1176 1177 op->type = COMPUTE; 1178 1179 opcode = instr >> 26; 1180 switch (opcode) { 1181 case 16: /* bc */ 1182 op->type = BRANCH; 1183 imm = (signed short)(instr & 0xfffc); 1184 if ((instr & 2) == 0) 1185 imm += regs->nip; 1186 op->val = truncate_if_32bit(regs->msr, imm); 1187 if (instr & 1) 1188 op->type |= SETLK; 1189 if (branch_taken(instr, regs, op)) 1190 op->type |= BRTAKEN; 1191 return 1; 1192 #ifdef CONFIG_PPC64 1193 case 17: /* sc */ 1194 if ((instr & 0xfe2) == 2) 1195 op->type = SYSCALL; 1196 else 1197 op->type = UNKNOWN; 1198 return 0; 1199 #endif 1200 case 18: /* b */ 1201 op->type = BRANCH | BRTAKEN; 1202 imm = instr & 0x03fffffc; 1203 if (imm & 0x02000000) 1204 imm -= 0x04000000; 1205 if ((instr & 2) == 0) 1206 imm += regs->nip; 1207 op->val = truncate_if_32bit(regs->msr, imm); 1208 if (instr & 1) 1209 op->type |= SETLK; 1210 return 1; 1211 case 19: 1212 switch ((instr >> 1) & 0x3ff) { 1213 case 0: /* mcrf */ 1214 op->type = COMPUTE + SETCC; 1215 rd = 7 - ((instr >> 23) & 0x7); 1216 ra = 7 - ((instr >> 18) & 0x7); 1217 rd *= 4; 1218 ra *= 4; 1219 val = (regs->ccr >> ra) & 0xf; 1220 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); 1221 return 1; 1222 1223 case 16: /* bclr */ 1224 case 528: /* bcctr */ 1225 op->type = BRANCH; 1226 imm = (instr & 0x400)? regs->ctr: regs->link; 1227 op->val = truncate_if_32bit(regs->msr, imm); 1228 if (instr & 1) 1229 op->type |= SETLK; 1230 if (branch_taken(instr, regs, op)) 1231 op->type |= BRTAKEN; 1232 return 1; 1233 1234 case 18: /* rfid, scary */ 1235 if (regs->msr & MSR_PR) 1236 goto priv; 1237 op->type = RFI; 1238 return 0; 1239 1240 case 150: /* isync */ 1241 op->type = BARRIER | BARRIER_ISYNC; 1242 return 1; 1243 1244 case 33: /* crnor */ 1245 case 129: /* crandc */ 1246 case 193: /* crxor */ 1247 case 225: /* crnand */ 1248 case 257: /* crand */ 1249 case 289: /* creqv */ 1250 case 417: /* crorc */ 1251 case 449: /* cror */ 1252 op->type = COMPUTE + SETCC; 1253 ra = (instr >> 16) & 0x1f; 1254 rb = (instr >> 11) & 0x1f; 1255 rd = (instr >> 21) & 0x1f; 1256 ra = (regs->ccr >> (31 - ra)) & 1; 1257 rb = (regs->ccr >> (31 - rb)) & 1; 1258 val = (instr >> (6 + ra * 2 + rb)) & 1; 1259 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | 1260 (val << (31 - rd)); 1261 return 1; 1262 } 1263 break; 1264 case 31: 1265 switch ((instr >> 1) & 0x3ff) { 1266 case 598: /* sync */ 1267 op->type = BARRIER + BARRIER_SYNC; 1268 #ifdef __powerpc64__ 1269 switch ((instr >> 21) & 3) { 1270 case 1: /* lwsync */ 1271 op->type = BARRIER + BARRIER_LWSYNC; 1272 break; 1273 case 2: /* ptesync */ 1274 op->type = BARRIER + BARRIER_PTESYNC; 1275 break; 1276 } 1277 #endif 1278 return 1; 1279 1280 case 854: /* eieio */ 1281 op->type = BARRIER + BARRIER_EIEIO; 1282 return 1; 1283 } 1284 break; 1285 } 1286 1287 /* Following cases refer to regs->gpr[], so we need all regs */ 1288 if (!FULL_REGS(regs)) 1289 return -1; 1290 1291 rd = (instr >> 21) & 0x1f; 1292 ra = (instr >> 16) & 0x1f; 1293 rb = (instr >> 11) & 0x1f; 1294 1295 switch (opcode) { 1296 #ifdef __powerpc64__ 1297 case 2: /* tdi */ 1298 if (rd & trap_compare(regs->gpr[ra], (short) instr)) 1299 goto trap; 1300 return 1; 1301 #endif 1302 case 3: /* twi */ 1303 if (rd & trap_compare((int)regs->gpr[ra], (short) instr)) 1304 goto trap; 1305 return 1; 1306 1307 case 7: /* mulli */ 1308 op->val = regs->gpr[ra] * (short) instr; 1309 goto compute_done; 1310 1311 case 8: /* subfic */ 1312 imm = (short) instr; 1313 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); 1314 return 1; 1315 1316 case 10: /* cmpli */ 1317 imm = (unsigned short) instr; 1318 val = regs->gpr[ra]; 1319 #ifdef __powerpc64__ 1320 if ((rd & 1) == 0) 1321 val = (unsigned int) val; 1322 #endif 1323 do_cmp_unsigned(regs, op, val, imm, rd >> 2); 1324 return 1; 1325 1326 case 11: /* cmpi */ 1327 imm = (short) instr; 1328 val = regs->gpr[ra]; 1329 #ifdef __powerpc64__ 1330 if ((rd & 1) == 0) 1331 val = (int) val; 1332 #endif 1333 do_cmp_signed(regs, op, val, imm, rd >> 2); 1334 return 1; 1335 1336 case 12: /* addic */ 1337 imm = (short) instr; 1338 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1339 return 1; 1340 1341 case 13: /* addic. */ 1342 imm = (short) instr; 1343 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1344 set_cr0(regs, op); 1345 return 1; 1346 1347 case 14: /* addi */ 1348 imm = (short) instr; 1349 if (ra) 1350 imm += regs->gpr[ra]; 1351 op->val = imm; 1352 goto compute_done; 1353 1354 case 15: /* addis */ 1355 imm = ((short) instr) << 16; 1356 if (ra) 1357 imm += regs->gpr[ra]; 1358 op->val = imm; 1359 goto compute_done; 1360 1361 case 19: 1362 if (((instr >> 1) & 0x1f) == 2) { 1363 /* addpcis */ 1364 imm = (short) (instr & 0xffc1); /* d0 + d2 fields */ 1365 imm |= (instr >> 15) & 0x3e; /* d1 field */ 1366 op->val = regs->nip + (imm << 16) + 4; 1367 goto compute_done; 1368 } 1369 op->type = UNKNOWN; 1370 return 0; 1371 1372 case 20: /* rlwimi */ 1373 mb = (instr >> 6) & 0x1f; 1374 me = (instr >> 1) & 0x1f; 1375 val = DATA32(regs->gpr[rd]); 1376 imm = MASK32(mb, me); 1377 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); 1378 goto logical_done; 1379 1380 case 21: /* rlwinm */ 1381 mb = (instr >> 6) & 0x1f; 1382 me = (instr >> 1) & 0x1f; 1383 val = DATA32(regs->gpr[rd]); 1384 op->val = ROTATE(val, rb) & MASK32(mb, me); 1385 goto logical_done; 1386 1387 case 23: /* rlwnm */ 1388 mb = (instr >> 6) & 0x1f; 1389 me = (instr >> 1) & 0x1f; 1390 rb = regs->gpr[rb] & 0x1f; 1391 val = DATA32(regs->gpr[rd]); 1392 op->val = ROTATE(val, rb) & MASK32(mb, me); 1393 goto logical_done; 1394 1395 case 24: /* ori */ 1396 op->val = regs->gpr[rd] | (unsigned short) instr; 1397 goto logical_done_nocc; 1398 1399 case 25: /* oris */ 1400 imm = (unsigned short) instr; 1401 op->val = regs->gpr[rd] | (imm << 16); 1402 goto logical_done_nocc; 1403 1404 case 26: /* xori */ 1405 op->val = regs->gpr[rd] ^ (unsigned short) instr; 1406 goto logical_done_nocc; 1407 1408 case 27: /* xoris */ 1409 imm = (unsigned short) instr; 1410 op->val = regs->gpr[rd] ^ (imm << 16); 1411 goto logical_done_nocc; 1412 1413 case 28: /* andi. */ 1414 op->val = regs->gpr[rd] & (unsigned short) instr; 1415 set_cr0(regs, op); 1416 goto logical_done_nocc; 1417 1418 case 29: /* andis. */ 1419 imm = (unsigned short) instr; 1420 op->val = regs->gpr[rd] & (imm << 16); 1421 set_cr0(regs, op); 1422 goto logical_done_nocc; 1423 1424 #ifdef __powerpc64__ 1425 case 30: /* rld* */ 1426 mb = ((instr >> 6) & 0x1f) | (instr & 0x20); 1427 val = regs->gpr[rd]; 1428 if ((instr & 0x10) == 0) { 1429 sh = rb | ((instr & 2) << 4); 1430 val = ROTATE(val, sh); 1431 switch ((instr >> 2) & 3) { 1432 case 0: /* rldicl */ 1433 val &= MASK64_L(mb); 1434 break; 1435 case 1: /* rldicr */ 1436 val &= MASK64_R(mb); 1437 break; 1438 case 2: /* rldic */ 1439 val &= MASK64(mb, 63 - sh); 1440 break; 1441 case 3: /* rldimi */ 1442 imm = MASK64(mb, 63 - sh); 1443 val = (regs->gpr[ra] & ~imm) | 1444 (val & imm); 1445 } 1446 op->val = val; 1447 goto logical_done; 1448 } else { 1449 sh = regs->gpr[rb] & 0x3f; 1450 val = ROTATE(val, sh); 1451 switch ((instr >> 1) & 7) { 1452 case 0: /* rldcl */ 1453 op->val = val & MASK64_L(mb); 1454 goto logical_done; 1455 case 1: /* rldcr */ 1456 op->val = val & MASK64_R(mb); 1457 goto logical_done; 1458 } 1459 } 1460 #endif 1461 op->type = UNKNOWN; /* illegal instruction */ 1462 return 0; 1463 1464 case 31: 1465 /* isel occupies 32 minor opcodes */ 1466 if (((instr >> 1) & 0x1f) == 15) { 1467 mb = (instr >> 6) & 0x1f; /* bc field */ 1468 val = (regs->ccr >> (31 - mb)) & 1; 1469 val2 = (ra) ? regs->gpr[ra] : 0; 1470 1471 op->val = (val) ? val2 : regs->gpr[rb]; 1472 goto compute_done; 1473 } 1474 1475 switch ((instr >> 1) & 0x3ff) { 1476 case 4: /* tw */ 1477 if (rd == 0x1f || 1478 (rd & trap_compare((int)regs->gpr[ra], 1479 (int)regs->gpr[rb]))) 1480 goto trap; 1481 return 1; 1482 #ifdef __powerpc64__ 1483 case 68: /* td */ 1484 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) 1485 goto trap; 1486 return 1; 1487 #endif 1488 case 83: /* mfmsr */ 1489 if (regs->msr & MSR_PR) 1490 goto priv; 1491 op->type = MFMSR; 1492 op->reg = rd; 1493 return 0; 1494 case 146: /* mtmsr */ 1495 if (regs->msr & MSR_PR) 1496 goto priv; 1497 op->type = MTMSR; 1498 op->reg = rd; 1499 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); 1500 return 0; 1501 #ifdef CONFIG_PPC64 1502 case 178: /* mtmsrd */ 1503 if (regs->msr & MSR_PR) 1504 goto priv; 1505 op->type = MTMSR; 1506 op->reg = rd; 1507 /* only MSR_EE and MSR_RI get changed if bit 15 set */ 1508 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ 1509 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL; 1510 op->val = imm; 1511 return 0; 1512 #endif 1513 1514 case 19: /* mfcr */ 1515 imm = 0xffffffffUL; 1516 if ((instr >> 20) & 1) { 1517 imm = 0xf0000000UL; 1518 for (sh = 0; sh < 8; ++sh) { 1519 if (instr & (0x80000 >> sh)) 1520 break; 1521 imm >>= 4; 1522 } 1523 } 1524 op->val = regs->ccr & imm; 1525 goto compute_done; 1526 1527 case 144: /* mtcrf */ 1528 op->type = COMPUTE + SETCC; 1529 imm = 0xf0000000UL; 1530 val = regs->gpr[rd]; 1531 op->ccval = regs->ccr; 1532 for (sh = 0; sh < 8; ++sh) { 1533 if (instr & (0x80000 >> sh)) 1534 op->ccval = (op->ccval & ~imm) | 1535 (val & imm); 1536 imm >>= 4; 1537 } 1538 return 1; 1539 1540 case 339: /* mfspr */ 1541 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1542 op->type = MFSPR; 1543 op->reg = rd; 1544 op->spr = spr; 1545 if (spr == SPRN_XER || spr == SPRN_LR || 1546 spr == SPRN_CTR) 1547 return 1; 1548 return 0; 1549 1550 case 467: /* mtspr */ 1551 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1552 op->type = MTSPR; 1553 op->val = regs->gpr[rd]; 1554 op->spr = spr; 1555 if (spr == SPRN_XER || spr == SPRN_LR || 1556 spr == SPRN_CTR) 1557 return 1; 1558 return 0; 1559 1560 /* 1561 * Compare instructions 1562 */ 1563 case 0: /* cmp */ 1564 val = regs->gpr[ra]; 1565 val2 = regs->gpr[rb]; 1566 #ifdef __powerpc64__ 1567 if ((rd & 1) == 0) { 1568 /* word (32-bit) compare */ 1569 val = (int) val; 1570 val2 = (int) val2; 1571 } 1572 #endif 1573 do_cmp_signed(regs, op, val, val2, rd >> 2); 1574 return 1; 1575 1576 case 32: /* cmpl */ 1577 val = regs->gpr[ra]; 1578 val2 = regs->gpr[rb]; 1579 #ifdef __powerpc64__ 1580 if ((rd & 1) == 0) { 1581 /* word (32-bit) compare */ 1582 val = (unsigned int) val; 1583 val2 = (unsigned int) val2; 1584 } 1585 #endif 1586 do_cmp_unsigned(regs, op, val, val2, rd >> 2); 1587 return 1; 1588 1589 case 508: /* cmpb */ 1590 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); 1591 goto logical_done_nocc; 1592 1593 /* 1594 * Arithmetic instructions 1595 */ 1596 case 8: /* subfc */ 1597 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1598 regs->gpr[rb], 1); 1599 goto arith_done; 1600 #ifdef __powerpc64__ 1601 case 9: /* mulhdu */ 1602 asm("mulhdu %0,%1,%2" : "=r" (op->val) : 1603 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1604 goto arith_done; 1605 #endif 1606 case 10: /* addc */ 1607 add_with_carry(regs, op, rd, regs->gpr[ra], 1608 regs->gpr[rb], 0); 1609 goto arith_done; 1610 1611 case 11: /* mulhwu */ 1612 asm("mulhwu %0,%1,%2" : "=r" (op->val) : 1613 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1614 goto arith_done; 1615 1616 case 40: /* subf */ 1617 op->val = regs->gpr[rb] - regs->gpr[ra]; 1618 goto arith_done; 1619 #ifdef __powerpc64__ 1620 case 73: /* mulhd */ 1621 asm("mulhd %0,%1,%2" : "=r" (op->val) : 1622 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1623 goto arith_done; 1624 #endif 1625 case 75: /* mulhw */ 1626 asm("mulhw %0,%1,%2" : "=r" (op->val) : 1627 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1628 goto arith_done; 1629 1630 case 104: /* neg */ 1631 op->val = -regs->gpr[ra]; 1632 goto arith_done; 1633 1634 case 136: /* subfe */ 1635 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1636 regs->gpr[rb], regs->xer & XER_CA); 1637 goto arith_done; 1638 1639 case 138: /* adde */ 1640 add_with_carry(regs, op, rd, regs->gpr[ra], 1641 regs->gpr[rb], regs->xer & XER_CA); 1642 goto arith_done; 1643 1644 case 200: /* subfze */ 1645 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, 1646 regs->xer & XER_CA); 1647 goto arith_done; 1648 1649 case 202: /* addze */ 1650 add_with_carry(regs, op, rd, regs->gpr[ra], 0L, 1651 regs->xer & XER_CA); 1652 goto arith_done; 1653 1654 case 232: /* subfme */ 1655 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, 1656 regs->xer & XER_CA); 1657 goto arith_done; 1658 #ifdef __powerpc64__ 1659 case 233: /* mulld */ 1660 op->val = regs->gpr[ra] * regs->gpr[rb]; 1661 goto arith_done; 1662 #endif 1663 case 234: /* addme */ 1664 add_with_carry(regs, op, rd, regs->gpr[ra], -1L, 1665 regs->xer & XER_CA); 1666 goto arith_done; 1667 1668 case 235: /* mullw */ 1669 op->val = (long)(int) regs->gpr[ra] * 1670 (int) regs->gpr[rb]; 1671 1672 goto arith_done; 1673 1674 case 266: /* add */ 1675 op->val = regs->gpr[ra] + regs->gpr[rb]; 1676 goto arith_done; 1677 #ifdef __powerpc64__ 1678 case 457: /* divdu */ 1679 op->val = regs->gpr[ra] / regs->gpr[rb]; 1680 goto arith_done; 1681 #endif 1682 case 459: /* divwu */ 1683 op->val = (unsigned int) regs->gpr[ra] / 1684 (unsigned int) regs->gpr[rb]; 1685 goto arith_done; 1686 #ifdef __powerpc64__ 1687 case 489: /* divd */ 1688 op->val = (long int) regs->gpr[ra] / 1689 (long int) regs->gpr[rb]; 1690 goto arith_done; 1691 #endif 1692 case 491: /* divw */ 1693 op->val = (int) regs->gpr[ra] / 1694 (int) regs->gpr[rb]; 1695 goto arith_done; 1696 1697 1698 /* 1699 * Logical instructions 1700 */ 1701 case 26: /* cntlzw */ 1702 op->val = __builtin_clz((unsigned int) regs->gpr[rd]); 1703 goto logical_done; 1704 #ifdef __powerpc64__ 1705 case 58: /* cntlzd */ 1706 op->val = __builtin_clzl(regs->gpr[rd]); 1707 goto logical_done; 1708 #endif 1709 case 28: /* and */ 1710 op->val = regs->gpr[rd] & regs->gpr[rb]; 1711 goto logical_done; 1712 1713 case 60: /* andc */ 1714 op->val = regs->gpr[rd] & ~regs->gpr[rb]; 1715 goto logical_done; 1716 1717 case 122: /* popcntb */ 1718 do_popcnt(regs, op, regs->gpr[rd], 8); 1719 goto logical_done_nocc; 1720 1721 case 124: /* nor */ 1722 op->val = ~(regs->gpr[rd] | regs->gpr[rb]); 1723 goto logical_done; 1724 1725 case 154: /* prtyw */ 1726 do_prty(regs, op, regs->gpr[rd], 32); 1727 goto logical_done_nocc; 1728 1729 case 186: /* prtyd */ 1730 do_prty(regs, op, regs->gpr[rd], 64); 1731 goto logical_done_nocc; 1732 #ifdef CONFIG_PPC64 1733 case 252: /* bpermd */ 1734 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); 1735 goto logical_done_nocc; 1736 #endif 1737 case 284: /* xor */ 1738 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); 1739 goto logical_done; 1740 1741 case 316: /* xor */ 1742 op->val = regs->gpr[rd] ^ regs->gpr[rb]; 1743 goto logical_done; 1744 1745 case 378: /* popcntw */ 1746 do_popcnt(regs, op, regs->gpr[rd], 32); 1747 goto logical_done_nocc; 1748 1749 case 412: /* orc */ 1750 op->val = regs->gpr[rd] | ~regs->gpr[rb]; 1751 goto logical_done; 1752 1753 case 444: /* or */ 1754 op->val = regs->gpr[rd] | regs->gpr[rb]; 1755 goto logical_done; 1756 1757 case 476: /* nand */ 1758 op->val = ~(regs->gpr[rd] & regs->gpr[rb]); 1759 goto logical_done; 1760 #ifdef CONFIG_PPC64 1761 case 506: /* popcntd */ 1762 do_popcnt(regs, op, regs->gpr[rd], 64); 1763 goto logical_done_nocc; 1764 #endif 1765 case 922: /* extsh */ 1766 op->val = (signed short) regs->gpr[rd]; 1767 goto logical_done; 1768 1769 case 954: /* extsb */ 1770 op->val = (signed char) regs->gpr[rd]; 1771 goto logical_done; 1772 #ifdef __powerpc64__ 1773 case 986: /* extsw */ 1774 op->val = (signed int) regs->gpr[rd]; 1775 goto logical_done; 1776 #endif 1777 1778 /* 1779 * Shift instructions 1780 */ 1781 case 24: /* slw */ 1782 sh = regs->gpr[rb] & 0x3f; 1783 if (sh < 32) 1784 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; 1785 else 1786 op->val = 0; 1787 goto logical_done; 1788 1789 case 536: /* srw */ 1790 sh = regs->gpr[rb] & 0x3f; 1791 if (sh < 32) 1792 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; 1793 else 1794 op->val = 0; 1795 goto logical_done; 1796 1797 case 792: /* sraw */ 1798 op->type = COMPUTE + SETREG + SETXER; 1799 sh = regs->gpr[rb] & 0x3f; 1800 ival = (signed int) regs->gpr[rd]; 1801 op->val = ival >> (sh < 32 ? sh : 31); 1802 op->xerval = regs->xer; 1803 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) 1804 op->xerval |= XER_CA; 1805 else 1806 op->xerval &= ~XER_CA; 1807 set_ca32(op, op->xerval & XER_CA); 1808 goto logical_done; 1809 1810 case 824: /* srawi */ 1811 op->type = COMPUTE + SETREG + SETXER; 1812 sh = rb; 1813 ival = (signed int) regs->gpr[rd]; 1814 op->val = ival >> sh; 1815 op->xerval = regs->xer; 1816 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1817 op->xerval |= XER_CA; 1818 else 1819 op->xerval &= ~XER_CA; 1820 set_ca32(op, op->xerval & XER_CA); 1821 goto logical_done; 1822 1823 #ifdef __powerpc64__ 1824 case 27: /* sld */ 1825 sh = regs->gpr[rb] & 0x7f; 1826 if (sh < 64) 1827 op->val = regs->gpr[rd] << sh; 1828 else 1829 op->val = 0; 1830 goto logical_done; 1831 1832 case 539: /* srd */ 1833 sh = regs->gpr[rb] & 0x7f; 1834 if (sh < 64) 1835 op->val = regs->gpr[rd] >> sh; 1836 else 1837 op->val = 0; 1838 goto logical_done; 1839 1840 case 794: /* srad */ 1841 op->type = COMPUTE + SETREG + SETXER; 1842 sh = regs->gpr[rb] & 0x7f; 1843 ival = (signed long int) regs->gpr[rd]; 1844 op->val = ival >> (sh < 64 ? sh : 63); 1845 op->xerval = regs->xer; 1846 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) 1847 op->xerval |= XER_CA; 1848 else 1849 op->xerval &= ~XER_CA; 1850 set_ca32(op, op->xerval & XER_CA); 1851 goto logical_done; 1852 1853 case 826: /* sradi with sh_5 = 0 */ 1854 case 827: /* sradi with sh_5 = 1 */ 1855 op->type = COMPUTE + SETREG + SETXER; 1856 sh = rb | ((instr & 2) << 4); 1857 ival = (signed long int) regs->gpr[rd]; 1858 op->val = ival >> sh; 1859 op->xerval = regs->xer; 1860 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1861 op->xerval |= XER_CA; 1862 else 1863 op->xerval &= ~XER_CA; 1864 set_ca32(op, op->xerval & XER_CA); 1865 goto logical_done; 1866 #endif /* __powerpc64__ */ 1867 1868 /* 1869 * Cache instructions 1870 */ 1871 case 54: /* dcbst */ 1872 op->type = MKOP(CACHEOP, DCBST, 0); 1873 op->ea = xform_ea(instr, regs); 1874 return 0; 1875 1876 case 86: /* dcbf */ 1877 op->type = MKOP(CACHEOP, DCBF, 0); 1878 op->ea = xform_ea(instr, regs); 1879 return 0; 1880 1881 case 246: /* dcbtst */ 1882 op->type = MKOP(CACHEOP, DCBTST, 0); 1883 op->ea = xform_ea(instr, regs); 1884 op->reg = rd; 1885 return 0; 1886 1887 case 278: /* dcbt */ 1888 op->type = MKOP(CACHEOP, DCBTST, 0); 1889 op->ea = xform_ea(instr, regs); 1890 op->reg = rd; 1891 return 0; 1892 1893 case 982: /* icbi */ 1894 op->type = MKOP(CACHEOP, ICBI, 0); 1895 op->ea = xform_ea(instr, regs); 1896 return 0; 1897 1898 case 1014: /* dcbz */ 1899 op->type = MKOP(CACHEOP, DCBZ, 0); 1900 op->ea = xform_ea(instr, regs); 1901 return 0; 1902 } 1903 break; 1904 } 1905 1906 /* 1907 * Loads and stores. 1908 */ 1909 op->type = UNKNOWN; 1910 op->update_reg = ra; 1911 op->reg = rd; 1912 op->val = regs->gpr[rd]; 1913 u = (instr >> 20) & UPDATE; 1914 op->vsx_flags = 0; 1915 1916 switch (opcode) { 1917 case 31: 1918 u = instr & UPDATE; 1919 op->ea = xform_ea(instr, regs); 1920 switch ((instr >> 1) & 0x3ff) { 1921 case 20: /* lwarx */ 1922 op->type = MKOP(LARX, 0, 4); 1923 break; 1924 1925 case 150: /* stwcx. */ 1926 op->type = MKOP(STCX, 0, 4); 1927 break; 1928 1929 #ifdef __powerpc64__ 1930 case 84: /* ldarx */ 1931 op->type = MKOP(LARX, 0, 8); 1932 break; 1933 1934 case 214: /* stdcx. */ 1935 op->type = MKOP(STCX, 0, 8); 1936 break; 1937 1938 case 52: /* lbarx */ 1939 op->type = MKOP(LARX, 0, 1); 1940 break; 1941 1942 case 694: /* stbcx. */ 1943 op->type = MKOP(STCX, 0, 1); 1944 break; 1945 1946 case 116: /* lharx */ 1947 op->type = MKOP(LARX, 0, 2); 1948 break; 1949 1950 case 726: /* sthcx. */ 1951 op->type = MKOP(STCX, 0, 2); 1952 break; 1953 1954 case 276: /* lqarx */ 1955 if (!((rd & 1) || rd == ra || rd == rb)) 1956 op->type = MKOP(LARX, 0, 16); 1957 break; 1958 1959 case 182: /* stqcx. */ 1960 if (!(rd & 1)) 1961 op->type = MKOP(STCX, 0, 16); 1962 break; 1963 #endif 1964 1965 case 23: /* lwzx */ 1966 case 55: /* lwzux */ 1967 op->type = MKOP(LOAD, u, 4); 1968 break; 1969 1970 case 87: /* lbzx */ 1971 case 119: /* lbzux */ 1972 op->type = MKOP(LOAD, u, 1); 1973 break; 1974 1975 #ifdef CONFIG_ALTIVEC 1976 /* 1977 * Note: for the load/store vector element instructions, 1978 * bits of the EA say which field of the VMX register to use. 1979 */ 1980 case 7: /* lvebx */ 1981 op->type = MKOP(LOAD_VMX, 0, 1); 1982 op->element_size = 1; 1983 break; 1984 1985 case 39: /* lvehx */ 1986 op->type = MKOP(LOAD_VMX, 0, 2); 1987 op->element_size = 2; 1988 break; 1989 1990 case 71: /* lvewx */ 1991 op->type = MKOP(LOAD_VMX, 0, 4); 1992 op->element_size = 4; 1993 break; 1994 1995 case 103: /* lvx */ 1996 case 359: /* lvxl */ 1997 op->type = MKOP(LOAD_VMX, 0, 16); 1998 op->element_size = 16; 1999 break; 2000 2001 case 135: /* stvebx */ 2002 op->type = MKOP(STORE_VMX, 0, 1); 2003 op->element_size = 1; 2004 break; 2005 2006 case 167: /* stvehx */ 2007 op->type = MKOP(STORE_VMX, 0, 2); 2008 op->element_size = 2; 2009 break; 2010 2011 case 199: /* stvewx */ 2012 op->type = MKOP(STORE_VMX, 0, 4); 2013 op->element_size = 4; 2014 break; 2015 2016 case 231: /* stvx */ 2017 case 487: /* stvxl */ 2018 op->type = MKOP(STORE_VMX, 0, 16); 2019 break; 2020 #endif /* CONFIG_ALTIVEC */ 2021 2022 #ifdef __powerpc64__ 2023 case 21: /* ldx */ 2024 case 53: /* ldux */ 2025 op->type = MKOP(LOAD, u, 8); 2026 break; 2027 2028 case 149: /* stdx */ 2029 case 181: /* stdux */ 2030 op->type = MKOP(STORE, u, 8); 2031 break; 2032 #endif 2033 2034 case 151: /* stwx */ 2035 case 183: /* stwux */ 2036 op->type = MKOP(STORE, u, 4); 2037 break; 2038 2039 case 215: /* stbx */ 2040 case 247: /* stbux */ 2041 op->type = MKOP(STORE, u, 1); 2042 break; 2043 2044 case 279: /* lhzx */ 2045 case 311: /* lhzux */ 2046 op->type = MKOP(LOAD, u, 2); 2047 break; 2048 2049 #ifdef __powerpc64__ 2050 case 341: /* lwax */ 2051 case 373: /* lwaux */ 2052 op->type = MKOP(LOAD, SIGNEXT | u, 4); 2053 break; 2054 #endif 2055 2056 case 343: /* lhax */ 2057 case 375: /* lhaux */ 2058 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2059 break; 2060 2061 case 407: /* sthx */ 2062 case 439: /* sthux */ 2063 op->type = MKOP(STORE, u, 2); 2064 break; 2065 2066 #ifdef __powerpc64__ 2067 case 532: /* ldbrx */ 2068 op->type = MKOP(LOAD, BYTEREV, 8); 2069 break; 2070 2071 #endif 2072 case 533: /* lswx */ 2073 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); 2074 break; 2075 2076 case 534: /* lwbrx */ 2077 op->type = MKOP(LOAD, BYTEREV, 4); 2078 break; 2079 2080 case 597: /* lswi */ 2081 if (rb == 0) 2082 rb = 32; /* # bytes to load */ 2083 op->type = MKOP(LOAD_MULTI, 0, rb); 2084 op->ea = ra ? regs->gpr[ra] : 0; 2085 break; 2086 2087 #ifdef CONFIG_PPC_FPU 2088 case 535: /* lfsx */ 2089 case 567: /* lfsux */ 2090 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2091 break; 2092 2093 case 599: /* lfdx */ 2094 case 631: /* lfdux */ 2095 op->type = MKOP(LOAD_FP, u, 8); 2096 break; 2097 2098 case 663: /* stfsx */ 2099 case 695: /* stfsux */ 2100 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2101 break; 2102 2103 case 727: /* stfdx */ 2104 case 759: /* stfdux */ 2105 op->type = MKOP(STORE_FP, u, 8); 2106 break; 2107 2108 #ifdef __powerpc64__ 2109 case 791: /* lfdpx */ 2110 op->type = MKOP(LOAD_FP, 0, 16); 2111 break; 2112 2113 case 855: /* lfiwax */ 2114 op->type = MKOP(LOAD_FP, SIGNEXT, 4); 2115 break; 2116 2117 case 887: /* lfiwzx */ 2118 op->type = MKOP(LOAD_FP, 0, 4); 2119 break; 2120 2121 case 919: /* stfdpx */ 2122 op->type = MKOP(STORE_FP, 0, 16); 2123 break; 2124 2125 case 983: /* stfiwx */ 2126 op->type = MKOP(STORE_FP, 0, 4); 2127 break; 2128 #endif /* __powerpc64 */ 2129 #endif /* CONFIG_PPC_FPU */ 2130 2131 #ifdef __powerpc64__ 2132 case 660: /* stdbrx */ 2133 op->type = MKOP(STORE, BYTEREV, 8); 2134 op->val = byterev_8(regs->gpr[rd]); 2135 break; 2136 2137 #endif 2138 case 661: /* stswx */ 2139 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); 2140 break; 2141 2142 case 662: /* stwbrx */ 2143 op->type = MKOP(STORE, BYTEREV, 4); 2144 op->val = byterev_4(regs->gpr[rd]); 2145 break; 2146 2147 case 725: /* stswi */ 2148 if (rb == 0) 2149 rb = 32; /* # bytes to store */ 2150 op->type = MKOP(STORE_MULTI, 0, rb); 2151 op->ea = ra ? regs->gpr[ra] : 0; 2152 break; 2153 2154 case 790: /* lhbrx */ 2155 op->type = MKOP(LOAD, BYTEREV, 2); 2156 break; 2157 2158 case 918: /* sthbrx */ 2159 op->type = MKOP(STORE, BYTEREV, 2); 2160 op->val = byterev_2(regs->gpr[rd]); 2161 break; 2162 2163 #ifdef CONFIG_VSX 2164 case 12: /* lxsiwzx */ 2165 op->reg = rd | ((instr & 1) << 5); 2166 op->type = MKOP(LOAD_VSX, 0, 4); 2167 op->element_size = 8; 2168 break; 2169 2170 case 76: /* lxsiwax */ 2171 op->reg = rd | ((instr & 1) << 5); 2172 op->type = MKOP(LOAD_VSX, SIGNEXT, 4); 2173 op->element_size = 8; 2174 break; 2175 2176 case 140: /* stxsiwx */ 2177 op->reg = rd | ((instr & 1) << 5); 2178 op->type = MKOP(STORE_VSX, 0, 4); 2179 op->element_size = 8; 2180 break; 2181 2182 case 268: /* lxvx */ 2183 op->reg = rd | ((instr & 1) << 5); 2184 op->type = MKOP(LOAD_VSX, 0, 16); 2185 op->element_size = 16; 2186 op->vsx_flags = VSX_CHECK_VEC; 2187 break; 2188 2189 case 269: /* lxvl */ 2190 case 301: { /* lxvll */ 2191 int nb; 2192 op->reg = rd | ((instr & 1) << 5); 2193 op->ea = ra ? regs->gpr[ra] : 0; 2194 nb = regs->gpr[rb] & 0xff; 2195 if (nb > 16) 2196 nb = 16; 2197 op->type = MKOP(LOAD_VSX, 0, nb); 2198 op->element_size = 16; 2199 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | 2200 VSX_CHECK_VEC; 2201 break; 2202 } 2203 case 332: /* lxvdsx */ 2204 op->reg = rd | ((instr & 1) << 5); 2205 op->type = MKOP(LOAD_VSX, 0, 8); 2206 op->element_size = 8; 2207 op->vsx_flags = VSX_SPLAT; 2208 break; 2209 2210 case 364: /* lxvwsx */ 2211 op->reg = rd | ((instr & 1) << 5); 2212 op->type = MKOP(LOAD_VSX, 0, 4); 2213 op->element_size = 4; 2214 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; 2215 break; 2216 2217 case 396: /* stxvx */ 2218 op->reg = rd | ((instr & 1) << 5); 2219 op->type = MKOP(STORE_VSX, 0, 16); 2220 op->element_size = 16; 2221 op->vsx_flags = VSX_CHECK_VEC; 2222 break; 2223 2224 case 397: /* stxvl */ 2225 case 429: { /* stxvll */ 2226 int nb; 2227 op->reg = rd | ((instr & 1) << 5); 2228 op->ea = ra ? regs->gpr[ra] : 0; 2229 nb = regs->gpr[rb] & 0xff; 2230 if (nb > 16) 2231 nb = 16; 2232 op->type = MKOP(STORE_VSX, 0, nb); 2233 op->element_size = 16; 2234 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | 2235 VSX_CHECK_VEC; 2236 break; 2237 } 2238 case 524: /* lxsspx */ 2239 op->reg = rd | ((instr & 1) << 5); 2240 op->type = MKOP(LOAD_VSX, 0, 4); 2241 op->element_size = 8; 2242 op->vsx_flags = VSX_FPCONV; 2243 break; 2244 2245 case 588: /* lxsdx */ 2246 op->reg = rd | ((instr & 1) << 5); 2247 op->type = MKOP(LOAD_VSX, 0, 8); 2248 op->element_size = 8; 2249 break; 2250 2251 case 652: /* stxsspx */ 2252 op->reg = rd | ((instr & 1) << 5); 2253 op->type = MKOP(STORE_VSX, 0, 4); 2254 op->element_size = 8; 2255 op->vsx_flags = VSX_FPCONV; 2256 break; 2257 2258 case 716: /* stxsdx */ 2259 op->reg = rd | ((instr & 1) << 5); 2260 op->type = MKOP(STORE_VSX, 0, 8); 2261 op->element_size = 8; 2262 break; 2263 2264 case 780: /* lxvw4x */ 2265 op->reg = rd | ((instr & 1) << 5); 2266 op->type = MKOP(LOAD_VSX, 0, 16); 2267 op->element_size = 4; 2268 break; 2269 2270 case 781: /* lxsibzx */ 2271 op->reg = rd | ((instr & 1) << 5); 2272 op->type = MKOP(LOAD_VSX, 0, 1); 2273 op->element_size = 8; 2274 op->vsx_flags = VSX_CHECK_VEC; 2275 break; 2276 2277 case 812: /* lxvh8x */ 2278 op->reg = rd | ((instr & 1) << 5); 2279 op->type = MKOP(LOAD_VSX, 0, 16); 2280 op->element_size = 2; 2281 op->vsx_flags = VSX_CHECK_VEC; 2282 break; 2283 2284 case 813: /* lxsihzx */ 2285 op->reg = rd | ((instr & 1) << 5); 2286 op->type = MKOP(LOAD_VSX, 0, 2); 2287 op->element_size = 8; 2288 op->vsx_flags = VSX_CHECK_VEC; 2289 break; 2290 2291 case 844: /* lxvd2x */ 2292 op->reg = rd | ((instr & 1) << 5); 2293 op->type = MKOP(LOAD_VSX, 0, 16); 2294 op->element_size = 8; 2295 break; 2296 2297 case 876: /* lxvb16x */ 2298 op->reg = rd | ((instr & 1) << 5); 2299 op->type = MKOP(LOAD_VSX, 0, 16); 2300 op->element_size = 1; 2301 op->vsx_flags = VSX_CHECK_VEC; 2302 break; 2303 2304 case 908: /* stxvw4x */ 2305 op->reg = rd | ((instr & 1) << 5); 2306 op->type = MKOP(STORE_VSX, 0, 16); 2307 op->element_size = 4; 2308 break; 2309 2310 case 909: /* stxsibx */ 2311 op->reg = rd | ((instr & 1) << 5); 2312 op->type = MKOP(STORE_VSX, 0, 1); 2313 op->element_size = 8; 2314 op->vsx_flags = VSX_CHECK_VEC; 2315 break; 2316 2317 case 940: /* stxvh8x */ 2318 op->reg = rd | ((instr & 1) << 5); 2319 op->type = MKOP(STORE_VSX, 0, 16); 2320 op->element_size = 2; 2321 op->vsx_flags = VSX_CHECK_VEC; 2322 break; 2323 2324 case 941: /* stxsihx */ 2325 op->reg = rd | ((instr & 1) << 5); 2326 op->type = MKOP(STORE_VSX, 0, 2); 2327 op->element_size = 8; 2328 op->vsx_flags = VSX_CHECK_VEC; 2329 break; 2330 2331 case 972: /* stxvd2x */ 2332 op->reg = rd | ((instr & 1) << 5); 2333 op->type = MKOP(STORE_VSX, 0, 16); 2334 op->element_size = 8; 2335 break; 2336 2337 case 1004: /* stxvb16x */ 2338 op->reg = rd | ((instr & 1) << 5); 2339 op->type = MKOP(STORE_VSX, 0, 16); 2340 op->element_size = 1; 2341 op->vsx_flags = VSX_CHECK_VEC; 2342 break; 2343 2344 #endif /* CONFIG_VSX */ 2345 } 2346 break; 2347 2348 case 32: /* lwz */ 2349 case 33: /* lwzu */ 2350 op->type = MKOP(LOAD, u, 4); 2351 op->ea = dform_ea(instr, regs); 2352 break; 2353 2354 case 34: /* lbz */ 2355 case 35: /* lbzu */ 2356 op->type = MKOP(LOAD, u, 1); 2357 op->ea = dform_ea(instr, regs); 2358 break; 2359 2360 case 36: /* stw */ 2361 case 37: /* stwu */ 2362 op->type = MKOP(STORE, u, 4); 2363 op->ea = dform_ea(instr, regs); 2364 break; 2365 2366 case 38: /* stb */ 2367 case 39: /* stbu */ 2368 op->type = MKOP(STORE, u, 1); 2369 op->ea = dform_ea(instr, regs); 2370 break; 2371 2372 case 40: /* lhz */ 2373 case 41: /* lhzu */ 2374 op->type = MKOP(LOAD, u, 2); 2375 op->ea = dform_ea(instr, regs); 2376 break; 2377 2378 case 42: /* lha */ 2379 case 43: /* lhau */ 2380 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2381 op->ea = dform_ea(instr, regs); 2382 break; 2383 2384 case 44: /* sth */ 2385 case 45: /* sthu */ 2386 op->type = MKOP(STORE, u, 2); 2387 op->ea = dform_ea(instr, regs); 2388 break; 2389 2390 case 46: /* lmw */ 2391 if (ra >= rd) 2392 break; /* invalid form, ra in range to load */ 2393 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); 2394 op->ea = dform_ea(instr, regs); 2395 break; 2396 2397 case 47: /* stmw */ 2398 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); 2399 op->ea = dform_ea(instr, regs); 2400 break; 2401 2402 #ifdef CONFIG_PPC_FPU 2403 case 48: /* lfs */ 2404 case 49: /* lfsu */ 2405 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2406 op->ea = dform_ea(instr, regs); 2407 break; 2408 2409 case 50: /* lfd */ 2410 case 51: /* lfdu */ 2411 op->type = MKOP(LOAD_FP, u, 8); 2412 op->ea = dform_ea(instr, regs); 2413 break; 2414 2415 case 52: /* stfs */ 2416 case 53: /* stfsu */ 2417 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2418 op->ea = dform_ea(instr, regs); 2419 break; 2420 2421 case 54: /* stfd */ 2422 case 55: /* stfdu */ 2423 op->type = MKOP(STORE_FP, u, 8); 2424 op->ea = dform_ea(instr, regs); 2425 break; 2426 #endif 2427 2428 #ifdef __powerpc64__ 2429 case 56: /* lq */ 2430 if (!((rd & 1) || (rd == ra))) 2431 op->type = MKOP(LOAD, 0, 16); 2432 op->ea = dqform_ea(instr, regs); 2433 break; 2434 #endif 2435 2436 #ifdef CONFIG_VSX 2437 case 57: /* lfdp, lxsd, lxssp */ 2438 op->ea = dsform_ea(instr, regs); 2439 switch (instr & 3) { 2440 case 0: /* lfdp */ 2441 if (rd & 1) 2442 break; /* reg must be even */ 2443 op->type = MKOP(LOAD_FP, 0, 16); 2444 break; 2445 case 2: /* lxsd */ 2446 op->reg = rd + 32; 2447 op->type = MKOP(LOAD_VSX, 0, 8); 2448 op->element_size = 8; 2449 op->vsx_flags = VSX_CHECK_VEC; 2450 break; 2451 case 3: /* lxssp */ 2452 op->reg = rd + 32; 2453 op->type = MKOP(LOAD_VSX, 0, 4); 2454 op->element_size = 8; 2455 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2456 break; 2457 } 2458 break; 2459 #endif /* CONFIG_VSX */ 2460 2461 #ifdef __powerpc64__ 2462 case 58: /* ld[u], lwa */ 2463 op->ea = dsform_ea(instr, regs); 2464 switch (instr & 3) { 2465 case 0: /* ld */ 2466 op->type = MKOP(LOAD, 0, 8); 2467 break; 2468 case 1: /* ldu */ 2469 op->type = MKOP(LOAD, UPDATE, 8); 2470 break; 2471 case 2: /* lwa */ 2472 op->type = MKOP(LOAD, SIGNEXT, 4); 2473 break; 2474 } 2475 break; 2476 #endif 2477 2478 #ifdef CONFIG_VSX 2479 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */ 2480 switch (instr & 7) { 2481 case 0: /* stfdp with LSB of DS field = 0 */ 2482 case 4: /* stfdp with LSB of DS field = 1 */ 2483 op->ea = dsform_ea(instr, regs); 2484 op->type = MKOP(STORE_FP, 0, 16); 2485 break; 2486 2487 case 1: /* lxv */ 2488 op->ea = dqform_ea(instr, regs); 2489 if (instr & 8) 2490 op->reg = rd + 32; 2491 op->type = MKOP(LOAD_VSX, 0, 16); 2492 op->element_size = 16; 2493 op->vsx_flags = VSX_CHECK_VEC; 2494 break; 2495 2496 case 2: /* stxsd with LSB of DS field = 0 */ 2497 case 6: /* stxsd with LSB of DS field = 1 */ 2498 op->ea = dsform_ea(instr, regs); 2499 op->reg = rd + 32; 2500 op->type = MKOP(STORE_VSX, 0, 8); 2501 op->element_size = 8; 2502 op->vsx_flags = VSX_CHECK_VEC; 2503 break; 2504 2505 case 3: /* stxssp with LSB of DS field = 0 */ 2506 case 7: /* stxssp with LSB of DS field = 1 */ 2507 op->ea = dsform_ea(instr, regs); 2508 op->reg = rd + 32; 2509 op->type = MKOP(STORE_VSX, 0, 4); 2510 op->element_size = 8; 2511 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2512 break; 2513 2514 case 5: /* stxv */ 2515 op->ea = dqform_ea(instr, regs); 2516 if (instr & 8) 2517 op->reg = rd + 32; 2518 op->type = MKOP(STORE_VSX, 0, 16); 2519 op->element_size = 16; 2520 op->vsx_flags = VSX_CHECK_VEC; 2521 break; 2522 } 2523 break; 2524 #endif /* CONFIG_VSX */ 2525 2526 #ifdef __powerpc64__ 2527 case 62: /* std[u] */ 2528 op->ea = dsform_ea(instr, regs); 2529 switch (instr & 3) { 2530 case 0: /* std */ 2531 op->type = MKOP(STORE, 0, 8); 2532 break; 2533 case 1: /* stdu */ 2534 op->type = MKOP(STORE, UPDATE, 8); 2535 break; 2536 case 2: /* stq */ 2537 if (!(rd & 1)) 2538 op->type = MKOP(STORE, 0, 16); 2539 break; 2540 } 2541 break; 2542 #endif /* __powerpc64__ */ 2543 2544 } 2545 return 0; 2546 2547 logical_done: 2548 if (instr & 1) 2549 set_cr0(regs, op); 2550 logical_done_nocc: 2551 op->reg = ra; 2552 op->type |= SETREG; 2553 return 1; 2554 2555 arith_done: 2556 if (instr & 1) 2557 set_cr0(regs, op); 2558 compute_done: 2559 op->reg = rd; 2560 op->type |= SETREG; 2561 return 1; 2562 2563 priv: 2564 op->type = INTERRUPT | 0x700; 2565 op->val = SRR1_PROGPRIV; 2566 return 0; 2567 2568 trap: 2569 op->type = INTERRUPT | 0x700; 2570 op->val = SRR1_PROGTRAP; 2571 return 0; 2572 } 2573 EXPORT_SYMBOL_GPL(analyse_instr); 2574 NOKPROBE_SYMBOL(analyse_instr); 2575 2576 /* 2577 * For PPC32 we always use stwu with r1 to change the stack pointer. 2578 * So this emulated store may corrupt the exception frame, now we 2579 * have to provide the exception frame trampoline, which is pushed 2580 * below the kprobed function stack. So we only update gpr[1] but 2581 * don't emulate the real store operation. We will do real store 2582 * operation safely in exception return code by checking this flag. 2583 */ 2584 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) 2585 { 2586 #ifdef CONFIG_PPC32 2587 /* 2588 * Check if we will touch kernel stack overflow 2589 */ 2590 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { 2591 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); 2592 return -EINVAL; 2593 } 2594 #endif /* CONFIG_PPC32 */ 2595 /* 2596 * Check if we already set since that means we'll 2597 * lose the previous value. 2598 */ 2599 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); 2600 set_thread_flag(TIF_EMULATE_STACK_STORE); 2601 return 0; 2602 } 2603 2604 static nokprobe_inline void do_signext(unsigned long *valp, int size) 2605 { 2606 switch (size) { 2607 case 2: 2608 *valp = (signed short) *valp; 2609 break; 2610 case 4: 2611 *valp = (signed int) *valp; 2612 break; 2613 } 2614 } 2615 2616 static nokprobe_inline void do_byterev(unsigned long *valp, int size) 2617 { 2618 switch (size) { 2619 case 2: 2620 *valp = byterev_2(*valp); 2621 break; 2622 case 4: 2623 *valp = byterev_4(*valp); 2624 break; 2625 #ifdef __powerpc64__ 2626 case 8: 2627 *valp = byterev_8(*valp); 2628 break; 2629 #endif 2630 } 2631 } 2632 2633 /* 2634 * Emulate an instruction that can be executed just by updating 2635 * fields in *regs. 2636 */ 2637 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) 2638 { 2639 unsigned long next_pc; 2640 2641 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); 2642 switch (op->type & INSTR_TYPE_MASK) { 2643 case COMPUTE: 2644 if (op->type & SETREG) 2645 regs->gpr[op->reg] = op->val; 2646 if (op->type & SETCC) 2647 regs->ccr = op->ccval; 2648 if (op->type & SETXER) 2649 regs->xer = op->xerval; 2650 break; 2651 2652 case BRANCH: 2653 if (op->type & SETLK) 2654 regs->link = next_pc; 2655 if (op->type & BRTAKEN) 2656 next_pc = op->val; 2657 if (op->type & DECCTR) 2658 --regs->ctr; 2659 break; 2660 2661 case BARRIER: 2662 switch (op->type & BARRIER_MASK) { 2663 case BARRIER_SYNC: 2664 mb(); 2665 break; 2666 case BARRIER_ISYNC: 2667 isync(); 2668 break; 2669 case BARRIER_EIEIO: 2670 eieio(); 2671 break; 2672 case BARRIER_LWSYNC: 2673 asm volatile("lwsync" : : : "memory"); 2674 break; 2675 case BARRIER_PTESYNC: 2676 asm volatile("ptesync" : : : "memory"); 2677 break; 2678 } 2679 break; 2680 2681 case MFSPR: 2682 switch (op->spr) { 2683 case SPRN_XER: 2684 regs->gpr[op->reg] = regs->xer & 0xffffffffUL; 2685 break; 2686 case SPRN_LR: 2687 regs->gpr[op->reg] = regs->link; 2688 break; 2689 case SPRN_CTR: 2690 regs->gpr[op->reg] = regs->ctr; 2691 break; 2692 default: 2693 WARN_ON_ONCE(1); 2694 } 2695 break; 2696 2697 case MTSPR: 2698 switch (op->spr) { 2699 case SPRN_XER: 2700 regs->xer = op->val & 0xffffffffUL; 2701 break; 2702 case SPRN_LR: 2703 regs->link = op->val; 2704 break; 2705 case SPRN_CTR: 2706 regs->ctr = op->val; 2707 break; 2708 default: 2709 WARN_ON_ONCE(1); 2710 } 2711 break; 2712 2713 default: 2714 WARN_ON_ONCE(1); 2715 } 2716 regs->nip = next_pc; 2717 } 2718 2719 /* 2720 * Emulate a previously-analysed load or store instruction. 2721 * Return values are: 2722 * 0 = instruction emulated successfully 2723 * -EFAULT = address out of range or access faulted (regs->dar 2724 * contains the faulting address) 2725 * -EACCES = misaligned access, instruction requires alignment 2726 * -EINVAL = unknown operation in *op 2727 */ 2728 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op) 2729 { 2730 int err, size, type; 2731 int i, rd, nb; 2732 unsigned int cr; 2733 unsigned long val; 2734 unsigned long ea; 2735 bool cross_endian; 2736 2737 err = 0; 2738 size = GETSIZE(op->type); 2739 type = op->type & INSTR_TYPE_MASK; 2740 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 2741 ea = truncate_if_32bit(regs->msr, op->ea); 2742 2743 switch (type) { 2744 case LARX: 2745 if (ea & (size - 1)) 2746 return -EACCES; /* can't handle misaligned */ 2747 if (!address_ok(regs, ea, size)) 2748 return -EFAULT; 2749 err = 0; 2750 val = 0; 2751 switch (size) { 2752 #ifdef __powerpc64__ 2753 case 1: 2754 __get_user_asmx(val, ea, err, "lbarx"); 2755 break; 2756 case 2: 2757 __get_user_asmx(val, ea, err, "lharx"); 2758 break; 2759 #endif 2760 case 4: 2761 __get_user_asmx(val, ea, err, "lwarx"); 2762 break; 2763 #ifdef __powerpc64__ 2764 case 8: 2765 __get_user_asmx(val, ea, err, "ldarx"); 2766 break; 2767 case 16: 2768 err = do_lqarx(ea, ®s->gpr[op->reg]); 2769 break; 2770 #endif 2771 default: 2772 return -EINVAL; 2773 } 2774 if (err) { 2775 regs->dar = ea; 2776 break; 2777 } 2778 if (size < 16) 2779 regs->gpr[op->reg] = val; 2780 break; 2781 2782 case STCX: 2783 if (ea & (size - 1)) 2784 return -EACCES; /* can't handle misaligned */ 2785 if (!address_ok(regs, ea, size)) 2786 return -EFAULT; 2787 err = 0; 2788 switch (size) { 2789 #ifdef __powerpc64__ 2790 case 1: 2791 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 2792 break; 2793 case 2: 2794 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 2795 break; 2796 #endif 2797 case 4: 2798 __put_user_asmx(op->val, ea, err, "stwcx.", cr); 2799 break; 2800 #ifdef __powerpc64__ 2801 case 8: 2802 __put_user_asmx(op->val, ea, err, "stdcx.", cr); 2803 break; 2804 case 16: 2805 err = do_stqcx(ea, regs->gpr[op->reg], 2806 regs->gpr[op->reg + 1], &cr); 2807 break; 2808 #endif 2809 default: 2810 return -EINVAL; 2811 } 2812 if (!err) 2813 regs->ccr = (regs->ccr & 0x0fffffff) | 2814 (cr & 0xe0000000) | 2815 ((regs->xer >> 3) & 0x10000000); 2816 else 2817 regs->dar = ea; 2818 break; 2819 2820 case LOAD: 2821 #ifdef __powerpc64__ 2822 if (size == 16) { 2823 err = emulate_lq(regs, ea, op->reg, cross_endian); 2824 break; 2825 } 2826 #endif 2827 err = read_mem(®s->gpr[op->reg], ea, size, regs); 2828 if (!err) { 2829 if (op->type & SIGNEXT) 2830 do_signext(®s->gpr[op->reg], size); 2831 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV)) 2832 do_byterev(®s->gpr[op->reg], size); 2833 } 2834 break; 2835 2836 #ifdef CONFIG_PPC_FPU 2837 case LOAD_FP: 2838 /* 2839 * If the instruction is in userspace, we can emulate it even 2840 * if the VMX state is not live, because we have the state 2841 * stored in the thread_struct. If the instruction is in 2842 * the kernel, we must not touch the state in the thread_struct. 2843 */ 2844 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 2845 return 0; 2846 err = do_fp_load(op, ea, regs, cross_endian); 2847 break; 2848 #endif 2849 #ifdef CONFIG_ALTIVEC 2850 case LOAD_VMX: 2851 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 2852 return 0; 2853 err = do_vec_load(op->reg, ea, size, regs, cross_endian); 2854 break; 2855 #endif 2856 #ifdef CONFIG_VSX 2857 case LOAD_VSX: { 2858 unsigned long msrbit = MSR_VSX; 2859 2860 /* 2861 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 2862 * when the target of the instruction is a vector register. 2863 */ 2864 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 2865 msrbit = MSR_VEC; 2866 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 2867 return 0; 2868 err = do_vsx_load(op, ea, regs, cross_endian); 2869 break; 2870 } 2871 #endif 2872 case LOAD_MULTI: 2873 if (!address_ok(regs, ea, size)) 2874 return -EFAULT; 2875 rd = op->reg; 2876 for (i = 0; i < size; i += 4) { 2877 unsigned int v32 = 0; 2878 2879 nb = size - i; 2880 if (nb > 4) 2881 nb = 4; 2882 err = copy_mem_in((u8 *) &v32, ea, nb, regs); 2883 if (err) 2884 break; 2885 if (unlikely(cross_endian)) 2886 v32 = byterev_4(v32); 2887 regs->gpr[rd] = v32; 2888 ea += 4; 2889 /* reg number wraps from 31 to 0 for lsw[ix] */ 2890 rd = (rd + 1) & 0x1f; 2891 } 2892 break; 2893 2894 case STORE: 2895 #ifdef __powerpc64__ 2896 if (size == 16) { 2897 err = emulate_stq(regs, ea, op->reg, cross_endian); 2898 break; 2899 } 2900 #endif 2901 if ((op->type & UPDATE) && size == sizeof(long) && 2902 op->reg == 1 && op->update_reg == 1 && 2903 !(regs->msr & MSR_PR) && 2904 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { 2905 err = handle_stack_update(ea, regs); 2906 break; 2907 } 2908 if (unlikely(cross_endian)) 2909 do_byterev(&op->val, size); 2910 err = write_mem(op->val, ea, size, regs); 2911 break; 2912 2913 #ifdef CONFIG_PPC_FPU 2914 case STORE_FP: 2915 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 2916 return 0; 2917 err = do_fp_store(op, ea, regs, cross_endian); 2918 break; 2919 #endif 2920 #ifdef CONFIG_ALTIVEC 2921 case STORE_VMX: 2922 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 2923 return 0; 2924 err = do_vec_store(op->reg, ea, size, regs, cross_endian); 2925 break; 2926 #endif 2927 #ifdef CONFIG_VSX 2928 case STORE_VSX: { 2929 unsigned long msrbit = MSR_VSX; 2930 2931 /* 2932 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 2933 * when the target of the instruction is a vector register. 2934 */ 2935 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 2936 msrbit = MSR_VEC; 2937 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 2938 return 0; 2939 err = do_vsx_store(op, ea, regs, cross_endian); 2940 break; 2941 } 2942 #endif 2943 case STORE_MULTI: 2944 if (!address_ok(regs, ea, size)) 2945 return -EFAULT; 2946 rd = op->reg; 2947 for (i = 0; i < size; i += 4) { 2948 unsigned int v32 = regs->gpr[rd]; 2949 2950 nb = size - i; 2951 if (nb > 4) 2952 nb = 4; 2953 if (unlikely(cross_endian)) 2954 v32 = byterev_4(v32); 2955 err = copy_mem_out((u8 *) &v32, ea, nb, regs); 2956 if (err) 2957 break; 2958 ea += 4; 2959 /* reg number wraps from 31 to 0 for stsw[ix] */ 2960 rd = (rd + 1) & 0x1f; 2961 } 2962 break; 2963 2964 default: 2965 return -EINVAL; 2966 } 2967 2968 if (err) 2969 return err; 2970 2971 if (op->type & UPDATE) 2972 regs->gpr[op->update_reg] = op->ea; 2973 2974 return 0; 2975 } 2976 NOKPROBE_SYMBOL(emulate_loadstore); 2977 2978 /* 2979 * Emulate instructions that cause a transfer of control, 2980 * loads and stores, and a few other instructions. 2981 * Returns 1 if the step was emulated, 0 if not, 2982 * or -1 if the instruction is one that should not be stepped, 2983 * such as an rfid, or a mtmsrd that would clear MSR_RI. 2984 */ 2985 int emulate_step(struct pt_regs *regs, unsigned int instr) 2986 { 2987 struct instruction_op op; 2988 int r, err, type; 2989 unsigned long val; 2990 unsigned long ea; 2991 2992 r = analyse_instr(&op, regs, instr); 2993 if (r < 0) 2994 return r; 2995 if (r > 0) { 2996 emulate_update_regs(regs, &op); 2997 return 1; 2998 } 2999 3000 err = 0; 3001 type = op.type & INSTR_TYPE_MASK; 3002 3003 if (OP_IS_LOAD_STORE(type)) { 3004 err = emulate_loadstore(regs, &op); 3005 if (err) 3006 return 0; 3007 goto instr_done; 3008 } 3009 3010 switch (type) { 3011 case CACHEOP: 3012 ea = truncate_if_32bit(regs->msr, op.ea); 3013 if (!address_ok(regs, ea, 8)) 3014 return 0; 3015 switch (op.type & CACHEOP_MASK) { 3016 case DCBST: 3017 __cacheop_user_asmx(ea, err, "dcbst"); 3018 break; 3019 case DCBF: 3020 __cacheop_user_asmx(ea, err, "dcbf"); 3021 break; 3022 case DCBTST: 3023 if (op.reg == 0) 3024 prefetchw((void *) ea); 3025 break; 3026 case DCBT: 3027 if (op.reg == 0) 3028 prefetch((void *) ea); 3029 break; 3030 case ICBI: 3031 __cacheop_user_asmx(ea, err, "icbi"); 3032 break; 3033 case DCBZ: 3034 err = emulate_dcbz(ea, regs); 3035 break; 3036 } 3037 if (err) { 3038 regs->dar = ea; 3039 return 0; 3040 } 3041 goto instr_done; 3042 3043 case MFMSR: 3044 regs->gpr[op.reg] = regs->msr & MSR_MASK; 3045 goto instr_done; 3046 3047 case MTMSR: 3048 val = regs->gpr[op.reg]; 3049 if ((val & MSR_RI) == 0) 3050 /* can't step mtmsr[d] that would clear MSR_RI */ 3051 return -1; 3052 /* here op.val is the mask of bits to change */ 3053 regs->msr = (regs->msr & ~op.val) | (val & op.val); 3054 goto instr_done; 3055 3056 #ifdef CONFIG_PPC64 3057 case SYSCALL: /* sc */ 3058 /* 3059 * N.B. this uses knowledge about how the syscall 3060 * entry code works. If that is changed, this will 3061 * need to be changed also. 3062 */ 3063 if (regs->gpr[0] == 0x1ebe && 3064 cpu_has_feature(CPU_FTR_REAL_LE)) { 3065 regs->msr ^= MSR_LE; 3066 goto instr_done; 3067 } 3068 regs->gpr[9] = regs->gpr[13]; 3069 regs->gpr[10] = MSR_KERNEL; 3070 regs->gpr[11] = regs->nip + 4; 3071 regs->gpr[12] = regs->msr & MSR_MASK; 3072 regs->gpr[13] = (unsigned long) get_paca(); 3073 regs->nip = (unsigned long) &system_call_common; 3074 regs->msr = MSR_KERNEL; 3075 return 1; 3076 3077 case RFI: 3078 return -1; 3079 #endif 3080 } 3081 return 0; 3082 3083 instr_done: 3084 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); 3085 return 1; 3086 } 3087 NOKPROBE_SYMBOL(emulate_step); 3088