1 /* 2 * Single-step support. 3 * 4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/kprobes.h> 13 #include <linux/ptrace.h> 14 #include <linux/prefetch.h> 15 #include <asm/sstep.h> 16 #include <asm/processor.h> 17 #include <linux/uaccess.h> 18 #include <asm/cpu_has_feature.h> 19 #include <asm/cputable.h> 20 21 extern char system_call_common[]; 22 23 #ifdef CONFIG_PPC64 24 /* Bits in SRR1 that are copied from MSR */ 25 #define MSR_MASK 0xffffffff87c0ffffUL 26 #else 27 #define MSR_MASK 0x87c0ffff 28 #endif 29 30 /* Bits in XER */ 31 #define XER_SO 0x80000000U 32 #define XER_OV 0x40000000U 33 #define XER_CA 0x20000000U 34 35 #ifdef CONFIG_PPC_FPU 36 /* 37 * Functions in ldstfp.S 38 */ 39 extern int do_lfs(int rn, unsigned long ea); 40 extern int do_lfd(int rn, unsigned long ea); 41 extern int do_stfs(int rn, unsigned long ea); 42 extern int do_stfd(int rn, unsigned long ea); 43 extern int do_lvx(int rn, unsigned long ea); 44 extern int do_stvx(int rn, unsigned long ea); 45 extern void load_vsrn(int vsr, const void *p); 46 extern void store_vsrn(int vsr, void *p); 47 extern void conv_sp_to_dp(const float *sp, double *dp); 48 extern void conv_dp_to_sp(const double *dp, float *sp); 49 #endif 50 51 #ifdef __powerpc64__ 52 /* 53 * Functions in quad.S 54 */ 55 extern int do_lq(unsigned long ea, unsigned long *regs); 56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1); 57 extern int do_lqarx(unsigned long ea, unsigned long *regs); 58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1, 59 unsigned int *crp); 60 #endif 61 62 #ifdef __LITTLE_ENDIAN__ 63 #define IS_LE 1 64 #define IS_BE 0 65 #else 66 #define IS_LE 0 67 #define IS_BE 1 68 #endif 69 70 /* 71 * Emulate the truncation of 64 bit values in 32-bit mode. 72 */ 73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, 74 unsigned long val) 75 { 76 #ifdef __powerpc64__ 77 if ((msr & MSR_64BIT) == 0) 78 val &= 0xffffffffUL; 79 #endif 80 return val; 81 } 82 83 /* 84 * Determine whether a conditional branch instruction would branch. 85 */ 86 static nokprobe_inline int branch_taken(unsigned int instr, 87 const struct pt_regs *regs, 88 struct instruction_op *op) 89 { 90 unsigned int bo = (instr >> 21) & 0x1f; 91 unsigned int bi; 92 93 if ((bo & 4) == 0) { 94 /* decrement counter */ 95 op->type |= DECCTR; 96 if (((bo >> 1) & 1) ^ (regs->ctr == 1)) 97 return 0; 98 } 99 if ((bo & 0x10) == 0) { 100 /* check bit from CR */ 101 bi = (instr >> 16) & 0x1f; 102 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) 103 return 0; 104 } 105 return 1; 106 } 107 108 static nokprobe_inline long address_ok(struct pt_regs *regs, unsigned long ea, int nb) 109 { 110 if (!user_mode(regs)) 111 return 1; 112 return __access_ok(ea, nb, USER_DS); 113 } 114 115 /* 116 * Calculate effective address for a D-form instruction 117 */ 118 static nokprobe_inline unsigned long dform_ea(unsigned int instr, 119 const struct pt_regs *regs) 120 { 121 int ra; 122 unsigned long ea; 123 124 ra = (instr >> 16) & 0x1f; 125 ea = (signed short) instr; /* sign-extend */ 126 if (ra) 127 ea += regs->gpr[ra]; 128 129 return truncate_if_32bit(regs->msr, ea); 130 } 131 132 #ifdef __powerpc64__ 133 /* 134 * Calculate effective address for a DS-form instruction 135 */ 136 static nokprobe_inline unsigned long dsform_ea(unsigned int instr, 137 const struct pt_regs *regs) 138 { 139 int ra; 140 unsigned long ea; 141 142 ra = (instr >> 16) & 0x1f; 143 ea = (signed short) (instr & ~3); /* sign-extend */ 144 if (ra) 145 ea += regs->gpr[ra]; 146 147 return truncate_if_32bit(regs->msr, ea); 148 } 149 150 /* 151 * Calculate effective address for a DQ-form instruction 152 */ 153 static nokprobe_inline unsigned long dqform_ea(unsigned int instr, 154 const struct pt_regs *regs) 155 { 156 int ra; 157 unsigned long ea; 158 159 ra = (instr >> 16) & 0x1f; 160 ea = (signed short) (instr & ~0xf); /* sign-extend */ 161 if (ra) 162 ea += regs->gpr[ra]; 163 164 return truncate_if_32bit(regs->msr, ea); 165 } 166 #endif /* __powerpc64 */ 167 168 /* 169 * Calculate effective address for an X-form instruction 170 */ 171 static nokprobe_inline unsigned long xform_ea(unsigned int instr, 172 const struct pt_regs *regs) 173 { 174 int ra, rb; 175 unsigned long ea; 176 177 ra = (instr >> 16) & 0x1f; 178 rb = (instr >> 11) & 0x1f; 179 ea = regs->gpr[rb]; 180 if (ra) 181 ea += regs->gpr[ra]; 182 183 return truncate_if_32bit(regs->msr, ea); 184 } 185 186 /* 187 * Return the largest power of 2, not greater than sizeof(unsigned long), 188 * such that x is a multiple of it. 189 */ 190 static nokprobe_inline unsigned long max_align(unsigned long x) 191 { 192 x |= sizeof(unsigned long); 193 return x & -x; /* isolates rightmost bit */ 194 } 195 196 197 static nokprobe_inline unsigned long byterev_2(unsigned long x) 198 { 199 return ((x >> 8) & 0xff) | ((x & 0xff) << 8); 200 } 201 202 static nokprobe_inline unsigned long byterev_4(unsigned long x) 203 { 204 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | 205 ((x & 0xff00) << 8) | ((x & 0xff) << 24); 206 } 207 208 #ifdef __powerpc64__ 209 static nokprobe_inline unsigned long byterev_8(unsigned long x) 210 { 211 return (byterev_4(x) << 32) | byterev_4(x >> 32); 212 } 213 #endif 214 215 static nokprobe_inline int read_mem_aligned(unsigned long *dest, 216 unsigned long ea, int nb) 217 { 218 int err = 0; 219 unsigned long x = 0; 220 221 switch (nb) { 222 case 1: 223 err = __get_user(x, (unsigned char __user *) ea); 224 break; 225 case 2: 226 err = __get_user(x, (unsigned short __user *) ea); 227 break; 228 case 4: 229 err = __get_user(x, (unsigned int __user *) ea); 230 break; 231 #ifdef __powerpc64__ 232 case 8: 233 err = __get_user(x, (unsigned long __user *) ea); 234 break; 235 #endif 236 } 237 if (!err) 238 *dest = x; 239 return err; 240 } 241 242 static nokprobe_inline int read_mem_unaligned(unsigned long *dest, 243 unsigned long ea, int nb, struct pt_regs *regs) 244 { 245 int err; 246 unsigned long x, b, c; 247 #ifdef __LITTLE_ENDIAN__ 248 int len = nb; /* save a copy of the length for byte reversal */ 249 #endif 250 251 /* unaligned, do this in pieces */ 252 x = 0; 253 for (; nb > 0; nb -= c) { 254 #ifdef __LITTLE_ENDIAN__ 255 c = 1; 256 #endif 257 #ifdef __BIG_ENDIAN__ 258 c = max_align(ea); 259 #endif 260 if (c > nb) 261 c = max_align(nb); 262 err = read_mem_aligned(&b, ea, c); 263 if (err) 264 return err; 265 x = (x << (8 * c)) + b; 266 ea += c; 267 } 268 #ifdef __LITTLE_ENDIAN__ 269 switch (len) { 270 case 2: 271 *dest = byterev_2(x); 272 break; 273 case 4: 274 *dest = byterev_4(x); 275 break; 276 #ifdef __powerpc64__ 277 case 8: 278 *dest = byterev_8(x); 279 break; 280 #endif 281 } 282 #endif 283 #ifdef __BIG_ENDIAN__ 284 *dest = x; 285 #endif 286 return 0; 287 } 288 289 /* 290 * Read memory at address ea for nb bytes, return 0 for success 291 * or -EFAULT if an error occurred. 292 */ 293 static int read_mem(unsigned long *dest, unsigned long ea, int nb, 294 struct pt_regs *regs) 295 { 296 if (!address_ok(regs, ea, nb)) 297 return -EFAULT; 298 if ((ea & (nb - 1)) == 0) 299 return read_mem_aligned(dest, ea, nb); 300 return read_mem_unaligned(dest, ea, nb, regs); 301 } 302 NOKPROBE_SYMBOL(read_mem); 303 304 static nokprobe_inline int write_mem_aligned(unsigned long val, 305 unsigned long ea, int nb) 306 { 307 int err = 0; 308 309 switch (nb) { 310 case 1: 311 err = __put_user(val, (unsigned char __user *) ea); 312 break; 313 case 2: 314 err = __put_user(val, (unsigned short __user *) ea); 315 break; 316 case 4: 317 err = __put_user(val, (unsigned int __user *) ea); 318 break; 319 #ifdef __powerpc64__ 320 case 8: 321 err = __put_user(val, (unsigned long __user *) ea); 322 break; 323 #endif 324 } 325 return err; 326 } 327 328 static nokprobe_inline int write_mem_unaligned(unsigned long val, 329 unsigned long ea, int nb, struct pt_regs *regs) 330 { 331 int err; 332 unsigned long c; 333 334 #ifdef __LITTLE_ENDIAN__ 335 switch (nb) { 336 case 2: 337 val = byterev_2(val); 338 break; 339 case 4: 340 val = byterev_4(val); 341 break; 342 #ifdef __powerpc64__ 343 case 8: 344 val = byterev_8(val); 345 break; 346 #endif 347 } 348 #endif 349 /* unaligned or little-endian, do this in pieces */ 350 for (; nb > 0; nb -= c) { 351 #ifdef __LITTLE_ENDIAN__ 352 c = 1; 353 #endif 354 #ifdef __BIG_ENDIAN__ 355 c = max_align(ea); 356 #endif 357 if (c > nb) 358 c = max_align(nb); 359 err = write_mem_aligned(val >> (nb - c) * 8, ea, c); 360 if (err) 361 return err; 362 ea += c; 363 } 364 return 0; 365 } 366 367 /* 368 * Write memory at address ea for nb bytes, return 0 for success 369 * or -EFAULT if an error occurred. 370 */ 371 static int write_mem(unsigned long val, unsigned long ea, int nb, 372 struct pt_regs *regs) 373 { 374 if (!address_ok(regs, ea, nb)) 375 return -EFAULT; 376 if ((ea & (nb - 1)) == 0) 377 return write_mem_aligned(val, ea, nb); 378 return write_mem_unaligned(val, ea, nb, regs); 379 } 380 NOKPROBE_SYMBOL(write_mem); 381 382 #ifdef CONFIG_PPC_FPU 383 /* 384 * Check the address and alignment, and call func to do the actual 385 * load or store. 386 */ 387 static int do_fp_load(int rn, int (*func)(int, unsigned long), 388 unsigned long ea, int nb, 389 struct pt_regs *regs) 390 { 391 int err; 392 union { 393 double dbl; 394 unsigned long ul[2]; 395 struct { 396 #ifdef __BIG_ENDIAN__ 397 unsigned _pad_; 398 unsigned word; 399 #endif 400 #ifdef __LITTLE_ENDIAN__ 401 unsigned word; 402 unsigned _pad_; 403 #endif 404 } single; 405 } data; 406 unsigned long ptr; 407 408 if (!address_ok(regs, ea, nb)) 409 return -EFAULT; 410 if ((ea & 3) == 0) 411 return (*func)(rn, ea); 412 ptr = (unsigned long) &data.ul; 413 if (sizeof(unsigned long) == 8 || nb == 4) { 414 err = read_mem_unaligned(&data.ul[0], ea, nb, regs); 415 if (nb == 4) 416 ptr = (unsigned long)&(data.single.word); 417 } else { 418 /* reading a double on 32-bit */ 419 err = read_mem_unaligned(&data.ul[0], ea, 4, regs); 420 if (!err) 421 err = read_mem_unaligned(&data.ul[1], ea + 4, 4, regs); 422 } 423 if (err) 424 return err; 425 return (*func)(rn, ptr); 426 } 427 NOKPROBE_SYMBOL(do_fp_load); 428 429 static int do_fp_store(int rn, int (*func)(int, unsigned long), 430 unsigned long ea, int nb, 431 struct pt_regs *regs) 432 { 433 int err; 434 union { 435 double dbl; 436 unsigned long ul[2]; 437 struct { 438 #ifdef __BIG_ENDIAN__ 439 unsigned _pad_; 440 unsigned word; 441 #endif 442 #ifdef __LITTLE_ENDIAN__ 443 unsigned word; 444 unsigned _pad_; 445 #endif 446 } single; 447 } data; 448 unsigned long ptr; 449 450 if (!address_ok(regs, ea, nb)) 451 return -EFAULT; 452 if ((ea & 3) == 0) 453 return (*func)(rn, ea); 454 ptr = (unsigned long) &data.ul[0]; 455 if (sizeof(unsigned long) == 8 || nb == 4) { 456 if (nb == 4) 457 ptr = (unsigned long)&(data.single.word); 458 err = (*func)(rn, ptr); 459 if (err) 460 return err; 461 err = write_mem_unaligned(data.ul[0], ea, nb, regs); 462 } else { 463 /* writing a double on 32-bit */ 464 err = (*func)(rn, ptr); 465 if (err) 466 return err; 467 err = write_mem_unaligned(data.ul[0], ea, 4, regs); 468 if (!err) 469 err = write_mem_unaligned(data.ul[1], ea + 4, 4, regs); 470 } 471 return err; 472 } 473 NOKPROBE_SYMBOL(do_fp_store); 474 #endif 475 476 #ifdef CONFIG_ALTIVEC 477 /* For Altivec/VMX, no need to worry about alignment */ 478 static nokprobe_inline int do_vec_load(int rn, int (*func)(int, unsigned long), 479 unsigned long ea, struct pt_regs *regs) 480 { 481 if (!address_ok(regs, ea & ~0xfUL, 16)) 482 return -EFAULT; 483 return (*func)(rn, ea); 484 } 485 486 static nokprobe_inline int do_vec_store(int rn, int (*func)(int, unsigned long), 487 unsigned long ea, struct pt_regs *regs) 488 { 489 if (!address_ok(regs, ea & ~0xfUL, 16)) 490 return -EFAULT; 491 return (*func)(rn, ea); 492 } 493 #endif /* CONFIG_ALTIVEC */ 494 495 #ifdef __powerpc64__ 496 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea, 497 int reg) 498 { 499 int err; 500 501 if (!address_ok(regs, ea, 16)) 502 return -EFAULT; 503 /* if aligned, should be atomic */ 504 if ((ea & 0xf) == 0) 505 return do_lq(ea, ®s->gpr[reg]); 506 507 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); 508 if (!err) 509 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); 510 return err; 511 } 512 513 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea, 514 int reg) 515 { 516 int err; 517 518 if (!address_ok(regs, ea, 16)) 519 return -EFAULT; 520 /* if aligned, should be atomic */ 521 if ((ea & 0xf) == 0) 522 return do_stq(ea, regs->gpr[reg], regs->gpr[reg + 1]); 523 524 err = write_mem(regs->gpr[reg + IS_LE], ea, 8, regs); 525 if (!err) 526 err = write_mem(regs->gpr[reg + IS_BE], ea + 8, 8, regs); 527 return err; 528 } 529 #endif /* __powerpc64 */ 530 531 #ifdef CONFIG_VSX 532 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 533 const void *mem) 534 { 535 int size, read_size; 536 int i, j; 537 const unsigned int *wp; 538 const unsigned short *hp; 539 const unsigned char *bp; 540 541 size = GETSIZE(op->type); 542 reg->d[0] = reg->d[1] = 0; 543 544 switch (op->element_size) { 545 case 16: 546 /* whole vector; lxv[x] or lxvl[l] */ 547 if (size == 0) 548 break; 549 memcpy(reg, mem, size); 550 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) { 551 /* reverse 16 bytes */ 552 unsigned long tmp; 553 tmp = byterev_8(reg->d[0]); 554 reg->d[0] = byterev_8(reg->d[1]); 555 reg->d[1] = tmp; 556 } 557 break; 558 case 8: 559 /* scalar loads, lxvd2x, lxvdsx */ 560 read_size = (size >= 8) ? 8 : size; 561 i = IS_LE ? 8 : 8 - read_size; 562 memcpy(®->b[i], mem, read_size); 563 if (size < 8) { 564 if (op->type & SIGNEXT) { 565 /* size == 4 is the only case here */ 566 reg->d[IS_LE] = (signed int) reg->d[IS_LE]; 567 } else if (op->vsx_flags & VSX_FPCONV) { 568 preempt_disable(); 569 conv_sp_to_dp(®->fp[1 + IS_LE], 570 ®->dp[IS_LE]); 571 preempt_enable(); 572 } 573 } else { 574 if (size == 16) 575 reg->d[IS_BE] = *(unsigned long *)(mem + 8); 576 else if (op->vsx_flags & VSX_SPLAT) 577 reg->d[IS_BE] = reg->d[IS_LE]; 578 } 579 break; 580 case 4: 581 /* lxvw4x, lxvwsx */ 582 wp = mem; 583 for (j = 0; j < size / 4; ++j) { 584 i = IS_LE ? 3 - j : j; 585 reg->w[i] = *wp++; 586 } 587 if (op->vsx_flags & VSX_SPLAT) { 588 u32 val = reg->w[IS_LE ? 3 : 0]; 589 for (; j < 4; ++j) { 590 i = IS_LE ? 3 - j : j; 591 reg->w[i] = val; 592 } 593 } 594 break; 595 case 2: 596 /* lxvh8x */ 597 hp = mem; 598 for (j = 0; j < size / 2; ++j) { 599 i = IS_LE ? 7 - j : j; 600 reg->h[i] = *hp++; 601 } 602 break; 603 case 1: 604 /* lxvb16x */ 605 bp = mem; 606 for (j = 0; j < size; ++j) { 607 i = IS_LE ? 15 - j : j; 608 reg->b[i] = *bp++; 609 } 610 break; 611 } 612 } 613 EXPORT_SYMBOL_GPL(emulate_vsx_load); 614 NOKPROBE_SYMBOL(emulate_vsx_load); 615 616 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, 617 void *mem) 618 { 619 int size, write_size; 620 int i, j; 621 union vsx_reg buf; 622 unsigned int *wp; 623 unsigned short *hp; 624 unsigned char *bp; 625 626 size = GETSIZE(op->type); 627 628 switch (op->element_size) { 629 case 16: 630 /* stxv, stxvx, stxvl, stxvll */ 631 if (size == 0) 632 break; 633 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) { 634 /* reverse 16 bytes */ 635 buf.d[0] = byterev_8(reg->d[1]); 636 buf.d[1] = byterev_8(reg->d[0]); 637 reg = &buf; 638 } 639 memcpy(mem, reg, size); 640 break; 641 case 8: 642 /* scalar stores, stxvd2x */ 643 write_size = (size >= 8) ? 8 : size; 644 i = IS_LE ? 8 : 8 - write_size; 645 if (size < 8 && op->vsx_flags & VSX_FPCONV) { 646 buf.d[0] = buf.d[1] = 0; 647 preempt_disable(); 648 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); 649 preempt_enable(); 650 reg = &buf; 651 } 652 memcpy(mem, ®->b[i], write_size); 653 if (size == 16) 654 memcpy(mem + 8, ®->d[IS_BE], 8); 655 break; 656 case 4: 657 /* stxvw4x */ 658 wp = mem; 659 for (j = 0; j < size / 4; ++j) { 660 i = IS_LE ? 3 - j : j; 661 *wp++ = reg->w[i]; 662 } 663 break; 664 case 2: 665 /* stxvh8x */ 666 hp = mem; 667 for (j = 0; j < size / 2; ++j) { 668 i = IS_LE ? 7 - j : j; 669 *hp++ = reg->h[i]; 670 } 671 break; 672 case 1: 673 /* stvxb16x */ 674 bp = mem; 675 for (j = 0; j < size; ++j) { 676 i = IS_LE ? 15 - j : j; 677 *bp++ = reg->b[i]; 678 } 679 break; 680 } 681 } 682 EXPORT_SYMBOL_GPL(emulate_vsx_store); 683 NOKPROBE_SYMBOL(emulate_vsx_store); 684 #endif /* CONFIG_VSX */ 685 686 #define __put_user_asmx(x, addr, err, op, cr) \ 687 __asm__ __volatile__( \ 688 "1: " op " %2,0,%3\n" \ 689 " mfcr %1\n" \ 690 "2:\n" \ 691 ".section .fixup,\"ax\"\n" \ 692 "3: li %0,%4\n" \ 693 " b 2b\n" \ 694 ".previous\n" \ 695 EX_TABLE(1b, 3b) \ 696 : "=r" (err), "=r" (cr) \ 697 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) 698 699 #define __get_user_asmx(x, addr, err, op) \ 700 __asm__ __volatile__( \ 701 "1: "op" %1,0,%2\n" \ 702 "2:\n" \ 703 ".section .fixup,\"ax\"\n" \ 704 "3: li %0,%3\n" \ 705 " b 2b\n" \ 706 ".previous\n" \ 707 EX_TABLE(1b, 3b) \ 708 : "=r" (err), "=r" (x) \ 709 : "r" (addr), "i" (-EFAULT), "0" (err)) 710 711 #define __cacheop_user_asmx(addr, err, op) \ 712 __asm__ __volatile__( \ 713 "1: "op" 0,%1\n" \ 714 "2:\n" \ 715 ".section .fixup,\"ax\"\n" \ 716 "3: li %0,%3\n" \ 717 " b 2b\n" \ 718 ".previous\n" \ 719 EX_TABLE(1b, 3b) \ 720 : "=r" (err) \ 721 : "r" (addr), "i" (-EFAULT), "0" (err)) 722 723 static nokprobe_inline void set_cr0(const struct pt_regs *regs, 724 struct instruction_op *op, int rd) 725 { 726 long val = regs->gpr[rd]; 727 728 op->type |= SETCC; 729 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); 730 #ifdef __powerpc64__ 731 if (!(regs->msr & MSR_64BIT)) 732 val = (int) val; 733 #endif 734 if (val < 0) 735 op->ccval |= 0x80000000; 736 else if (val > 0) 737 op->ccval |= 0x40000000; 738 else 739 op->ccval |= 0x20000000; 740 } 741 742 static nokprobe_inline void add_with_carry(const struct pt_regs *regs, 743 struct instruction_op *op, int rd, 744 unsigned long val1, unsigned long val2, 745 unsigned long carry_in) 746 { 747 unsigned long val = val1 + val2; 748 749 if (carry_in) 750 ++val; 751 op->type = COMPUTE + SETREG + SETXER; 752 op->reg = rd; 753 op->val = val; 754 #ifdef __powerpc64__ 755 if (!(regs->msr & MSR_64BIT)) { 756 val = (unsigned int) val; 757 val1 = (unsigned int) val1; 758 } 759 #endif 760 op->xerval = regs->xer; 761 if (val < val1 || (carry_in && val == val1)) 762 op->xerval |= XER_CA; 763 else 764 op->xerval &= ~XER_CA; 765 } 766 767 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs, 768 struct instruction_op *op, 769 long v1, long v2, int crfld) 770 { 771 unsigned int crval, shift; 772 773 op->type = COMPUTE + SETCC; 774 crval = (regs->xer >> 31) & 1; /* get SO bit */ 775 if (v1 < v2) 776 crval |= 8; 777 else if (v1 > v2) 778 crval |= 4; 779 else 780 crval |= 2; 781 shift = (7 - crfld) * 4; 782 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 783 } 784 785 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs, 786 struct instruction_op *op, 787 unsigned long v1, 788 unsigned long v2, int crfld) 789 { 790 unsigned int crval, shift; 791 792 op->type = COMPUTE + SETCC; 793 crval = (regs->xer >> 31) & 1; /* get SO bit */ 794 if (v1 < v2) 795 crval |= 8; 796 else if (v1 > v2) 797 crval |= 4; 798 else 799 crval |= 2; 800 shift = (7 - crfld) * 4; 801 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 802 } 803 804 static nokprobe_inline void do_cmpb(const struct pt_regs *regs, 805 struct instruction_op *op, 806 unsigned long v1, unsigned long v2) 807 { 808 unsigned long long out_val, mask; 809 int i; 810 811 out_val = 0; 812 for (i = 0; i < 8; i++) { 813 mask = 0xffUL << (i * 8); 814 if ((v1 & mask) == (v2 & mask)) 815 out_val |= mask; 816 } 817 op->val = out_val; 818 } 819 820 /* 821 * The size parameter is used to adjust the equivalent popcnt instruction. 822 * popcntb = 8, popcntw = 32, popcntd = 64 823 */ 824 static nokprobe_inline void do_popcnt(const struct pt_regs *regs, 825 struct instruction_op *op, 826 unsigned long v1, int size) 827 { 828 unsigned long long out = v1; 829 830 out -= (out >> 1) & 0x5555555555555555; 831 out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2)); 832 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f; 833 834 if (size == 8) { /* popcntb */ 835 op->val = out; 836 return; 837 } 838 out += out >> 8; 839 out += out >> 16; 840 if (size == 32) { /* popcntw */ 841 op->val = out & 0x0000003f0000003f; 842 return; 843 } 844 845 out = (out + (out >> 32)) & 0x7f; 846 op->val = out; /* popcntd */ 847 } 848 849 #ifdef CONFIG_PPC64 850 static nokprobe_inline void do_bpermd(const struct pt_regs *regs, 851 struct instruction_op *op, 852 unsigned long v1, unsigned long v2) 853 { 854 unsigned char perm, idx; 855 unsigned int i; 856 857 perm = 0; 858 for (i = 0; i < 8; i++) { 859 idx = (v1 >> (i * 8)) & 0xff; 860 if (idx < 64) 861 if (v2 & PPC_BIT(idx)) 862 perm |= 1 << i; 863 } 864 op->val = perm; 865 } 866 #endif /* CONFIG_PPC64 */ 867 /* 868 * The size parameter adjusts the equivalent prty instruction. 869 * prtyw = 32, prtyd = 64 870 */ 871 static nokprobe_inline void do_prty(const struct pt_regs *regs, 872 struct instruction_op *op, 873 unsigned long v, int size) 874 { 875 unsigned long long res = v ^ (v >> 8); 876 877 res ^= res >> 16; 878 if (size == 32) { /* prtyw */ 879 op->val = res & 0x0000000100000001; 880 return; 881 } 882 883 res ^= res >> 32; 884 op->val = res & 1; /*prtyd */ 885 } 886 887 static nokprobe_inline int trap_compare(long v1, long v2) 888 { 889 int ret = 0; 890 891 if (v1 < v2) 892 ret |= 0x10; 893 else if (v1 > v2) 894 ret |= 0x08; 895 else 896 ret |= 0x04; 897 if ((unsigned long)v1 < (unsigned long)v2) 898 ret |= 0x02; 899 else if ((unsigned long)v1 > (unsigned long)v2) 900 ret |= 0x01; 901 return ret; 902 } 903 904 /* 905 * Elements of 32-bit rotate and mask instructions. 906 */ 907 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ 908 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) 909 #ifdef __powerpc64__ 910 #define MASK64_L(mb) (~0UL >> (mb)) 911 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) 912 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) 913 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) 914 #else 915 #define DATA32(x) (x) 916 #endif 917 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) 918 919 /* 920 * Decode an instruction, and return information about it in *op 921 * without changing *regs. 922 * Integer arithmetic and logical instructions, branches, and barrier 923 * instructions can be emulated just using the information in *op. 924 * 925 * Return value is 1 if the instruction can be emulated just by 926 * updating *regs with the information in *op, -1 if we need the 927 * GPRs but *regs doesn't contain the full register set, or 0 928 * otherwise. 929 */ 930 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 931 unsigned int instr) 932 { 933 unsigned int opcode, ra, rb, rd, spr, u; 934 unsigned long int imm; 935 unsigned long int val, val2; 936 unsigned int mb, me, sh; 937 long ival; 938 939 op->type = COMPUTE; 940 941 opcode = instr >> 26; 942 switch (opcode) { 943 case 16: /* bc */ 944 op->type = BRANCH; 945 imm = (signed short)(instr & 0xfffc); 946 if ((instr & 2) == 0) 947 imm += regs->nip; 948 op->val = truncate_if_32bit(regs->msr, imm); 949 if (instr & 1) 950 op->type |= SETLK; 951 if (branch_taken(instr, regs, op)) 952 op->type |= BRTAKEN; 953 return 1; 954 #ifdef CONFIG_PPC64 955 case 17: /* sc */ 956 if ((instr & 0xfe2) == 2) 957 op->type = SYSCALL; 958 else 959 op->type = UNKNOWN; 960 return 0; 961 #endif 962 case 18: /* b */ 963 op->type = BRANCH | BRTAKEN; 964 imm = instr & 0x03fffffc; 965 if (imm & 0x02000000) 966 imm -= 0x04000000; 967 if ((instr & 2) == 0) 968 imm += regs->nip; 969 op->val = truncate_if_32bit(regs->msr, imm); 970 if (instr & 1) 971 op->type |= SETLK; 972 return 1; 973 case 19: 974 switch ((instr >> 1) & 0x3ff) { 975 case 0: /* mcrf */ 976 op->type = COMPUTE + SETCC; 977 rd = 7 - ((instr >> 23) & 0x7); 978 ra = 7 - ((instr >> 18) & 0x7); 979 rd *= 4; 980 ra *= 4; 981 val = (regs->ccr >> ra) & 0xf; 982 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); 983 return 1; 984 985 case 16: /* bclr */ 986 case 528: /* bcctr */ 987 op->type = BRANCH; 988 imm = (instr & 0x400)? regs->ctr: regs->link; 989 op->val = truncate_if_32bit(regs->msr, imm); 990 if (instr & 1) 991 op->type |= SETLK; 992 if (branch_taken(instr, regs, op)) 993 op->type |= BRTAKEN; 994 return 1; 995 996 case 18: /* rfid, scary */ 997 if (regs->msr & MSR_PR) 998 goto priv; 999 op->type = RFI; 1000 return 0; 1001 1002 case 150: /* isync */ 1003 op->type = BARRIER | BARRIER_ISYNC; 1004 return 1; 1005 1006 case 33: /* crnor */ 1007 case 129: /* crandc */ 1008 case 193: /* crxor */ 1009 case 225: /* crnand */ 1010 case 257: /* crand */ 1011 case 289: /* creqv */ 1012 case 417: /* crorc */ 1013 case 449: /* cror */ 1014 op->type = COMPUTE + SETCC; 1015 ra = (instr >> 16) & 0x1f; 1016 rb = (instr >> 11) & 0x1f; 1017 rd = (instr >> 21) & 0x1f; 1018 ra = (regs->ccr >> (31 - ra)) & 1; 1019 rb = (regs->ccr >> (31 - rb)) & 1; 1020 val = (instr >> (6 + ra * 2 + rb)) & 1; 1021 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | 1022 (val << (31 - rd)); 1023 return 1; 1024 default: 1025 op->type = UNKNOWN; 1026 return 0; 1027 } 1028 break; 1029 case 31: 1030 switch ((instr >> 1) & 0x3ff) { 1031 case 598: /* sync */ 1032 op->type = BARRIER + BARRIER_SYNC; 1033 #ifdef __powerpc64__ 1034 switch ((instr >> 21) & 3) { 1035 case 1: /* lwsync */ 1036 op->type = BARRIER + BARRIER_LWSYNC; 1037 break; 1038 case 2: /* ptesync */ 1039 op->type = BARRIER + BARRIER_PTESYNC; 1040 break; 1041 } 1042 #endif 1043 return 1; 1044 1045 case 854: /* eieio */ 1046 op->type = BARRIER + BARRIER_EIEIO; 1047 return 1; 1048 } 1049 break; 1050 } 1051 1052 /* Following cases refer to regs->gpr[], so we need all regs */ 1053 if (!FULL_REGS(regs)) 1054 return -1; 1055 1056 rd = (instr >> 21) & 0x1f; 1057 ra = (instr >> 16) & 0x1f; 1058 rb = (instr >> 11) & 0x1f; 1059 1060 switch (opcode) { 1061 #ifdef __powerpc64__ 1062 case 2: /* tdi */ 1063 if (rd & trap_compare(regs->gpr[ra], (short) instr)) 1064 goto trap; 1065 return 1; 1066 #endif 1067 case 3: /* twi */ 1068 if (rd & trap_compare((int)regs->gpr[ra], (short) instr)) 1069 goto trap; 1070 return 1; 1071 1072 case 7: /* mulli */ 1073 op->val = regs->gpr[ra] * (short) instr; 1074 goto compute_done; 1075 1076 case 8: /* subfic */ 1077 imm = (short) instr; 1078 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); 1079 return 1; 1080 1081 case 10: /* cmpli */ 1082 imm = (unsigned short) instr; 1083 val = regs->gpr[ra]; 1084 #ifdef __powerpc64__ 1085 if ((rd & 1) == 0) 1086 val = (unsigned int) val; 1087 #endif 1088 do_cmp_unsigned(regs, op, val, imm, rd >> 2); 1089 return 1; 1090 1091 case 11: /* cmpi */ 1092 imm = (short) instr; 1093 val = regs->gpr[ra]; 1094 #ifdef __powerpc64__ 1095 if ((rd & 1) == 0) 1096 val = (int) val; 1097 #endif 1098 do_cmp_signed(regs, op, val, imm, rd >> 2); 1099 return 1; 1100 1101 case 12: /* addic */ 1102 imm = (short) instr; 1103 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1104 return 1; 1105 1106 case 13: /* addic. */ 1107 imm = (short) instr; 1108 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1109 set_cr0(regs, op, rd); 1110 return 1; 1111 1112 case 14: /* addi */ 1113 imm = (short) instr; 1114 if (ra) 1115 imm += regs->gpr[ra]; 1116 op->val = imm; 1117 goto compute_done; 1118 1119 case 15: /* addis */ 1120 imm = ((short) instr) << 16; 1121 if (ra) 1122 imm += regs->gpr[ra]; 1123 op->val = imm; 1124 goto compute_done; 1125 1126 case 20: /* rlwimi */ 1127 mb = (instr >> 6) & 0x1f; 1128 me = (instr >> 1) & 0x1f; 1129 val = DATA32(regs->gpr[rd]); 1130 imm = MASK32(mb, me); 1131 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); 1132 goto logical_done; 1133 1134 case 21: /* rlwinm */ 1135 mb = (instr >> 6) & 0x1f; 1136 me = (instr >> 1) & 0x1f; 1137 val = DATA32(regs->gpr[rd]); 1138 op->val = ROTATE(val, rb) & MASK32(mb, me); 1139 goto logical_done; 1140 1141 case 23: /* rlwnm */ 1142 mb = (instr >> 6) & 0x1f; 1143 me = (instr >> 1) & 0x1f; 1144 rb = regs->gpr[rb] & 0x1f; 1145 val = DATA32(regs->gpr[rd]); 1146 op->val = ROTATE(val, rb) & MASK32(mb, me); 1147 goto logical_done; 1148 1149 case 24: /* ori */ 1150 op->val = regs->gpr[rd] | (unsigned short) instr; 1151 goto logical_done_nocc; 1152 1153 case 25: /* oris */ 1154 imm = (unsigned short) instr; 1155 op->val = regs->gpr[rd] | (imm << 16); 1156 goto logical_done_nocc; 1157 1158 case 26: /* xori */ 1159 op->val = regs->gpr[rd] ^ (unsigned short) instr; 1160 goto logical_done_nocc; 1161 1162 case 27: /* xoris */ 1163 imm = (unsigned short) instr; 1164 op->val = regs->gpr[rd] ^ (imm << 16); 1165 goto logical_done_nocc; 1166 1167 case 28: /* andi. */ 1168 op->val = regs->gpr[rd] & (unsigned short) instr; 1169 set_cr0(regs, op, ra); 1170 goto logical_done_nocc; 1171 1172 case 29: /* andis. */ 1173 imm = (unsigned short) instr; 1174 op->val = regs->gpr[rd] & (imm << 16); 1175 set_cr0(regs, op, ra); 1176 goto logical_done_nocc; 1177 1178 #ifdef __powerpc64__ 1179 case 30: /* rld* */ 1180 mb = ((instr >> 6) & 0x1f) | (instr & 0x20); 1181 val = regs->gpr[rd]; 1182 if ((instr & 0x10) == 0) { 1183 sh = rb | ((instr & 2) << 4); 1184 val = ROTATE(val, sh); 1185 switch ((instr >> 2) & 3) { 1186 case 0: /* rldicl */ 1187 val &= MASK64_L(mb); 1188 break; 1189 case 1: /* rldicr */ 1190 val &= MASK64_R(mb); 1191 break; 1192 case 2: /* rldic */ 1193 val &= MASK64(mb, 63 - sh); 1194 break; 1195 case 3: /* rldimi */ 1196 imm = MASK64(mb, 63 - sh); 1197 val = (regs->gpr[ra] & ~imm) | 1198 (val & imm); 1199 } 1200 op->val = val; 1201 goto logical_done; 1202 } else { 1203 sh = regs->gpr[rb] & 0x3f; 1204 val = ROTATE(val, sh); 1205 switch ((instr >> 1) & 7) { 1206 case 0: /* rldcl */ 1207 op->val = val & MASK64_L(mb); 1208 goto logical_done; 1209 case 1: /* rldcr */ 1210 op->val = val & MASK64_R(mb); 1211 goto logical_done; 1212 } 1213 } 1214 #endif 1215 op->type = UNKNOWN; /* illegal instruction */ 1216 return 0; 1217 1218 case 31: 1219 switch ((instr >> 1) & 0x3ff) { 1220 case 4: /* tw */ 1221 if (rd == 0x1f || 1222 (rd & trap_compare((int)regs->gpr[ra], 1223 (int)regs->gpr[rb]))) 1224 goto trap; 1225 return 1; 1226 #ifdef __powerpc64__ 1227 case 68: /* td */ 1228 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) 1229 goto trap; 1230 return 1; 1231 #endif 1232 case 83: /* mfmsr */ 1233 if (regs->msr & MSR_PR) 1234 goto priv; 1235 op->type = MFMSR; 1236 op->reg = rd; 1237 return 0; 1238 case 146: /* mtmsr */ 1239 if (regs->msr & MSR_PR) 1240 goto priv; 1241 op->type = MTMSR; 1242 op->reg = rd; 1243 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); 1244 return 0; 1245 #ifdef CONFIG_PPC64 1246 case 178: /* mtmsrd */ 1247 if (regs->msr & MSR_PR) 1248 goto priv; 1249 op->type = MTMSR; 1250 op->reg = rd; 1251 /* only MSR_EE and MSR_RI get changed if bit 15 set */ 1252 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ 1253 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL; 1254 op->val = imm; 1255 return 0; 1256 #endif 1257 1258 case 19: /* mfcr */ 1259 imm = 0xffffffffUL; 1260 if ((instr >> 20) & 1) { 1261 imm = 0xf0000000UL; 1262 for (sh = 0; sh < 8; ++sh) { 1263 if (instr & (0x80000 >> sh)) 1264 break; 1265 imm >>= 4; 1266 } 1267 } 1268 op->val = regs->ccr & imm; 1269 goto compute_done; 1270 1271 case 144: /* mtcrf */ 1272 op->type = COMPUTE + SETCC; 1273 imm = 0xf0000000UL; 1274 val = regs->gpr[rd]; 1275 op->val = regs->ccr; 1276 for (sh = 0; sh < 8; ++sh) { 1277 if (instr & (0x80000 >> sh)) 1278 op->val = (op->val & ~imm) | 1279 (val & imm); 1280 imm >>= 4; 1281 } 1282 return 1; 1283 1284 case 339: /* mfspr */ 1285 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1286 op->type = MFSPR; 1287 op->reg = rd; 1288 op->spr = spr; 1289 if (spr == SPRN_XER || spr == SPRN_LR || 1290 spr == SPRN_CTR) 1291 return 1; 1292 return 0; 1293 1294 case 467: /* mtspr */ 1295 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1296 op->type = MTSPR; 1297 op->val = regs->gpr[rd]; 1298 op->spr = spr; 1299 if (spr == SPRN_XER || spr == SPRN_LR || 1300 spr == SPRN_CTR) 1301 return 1; 1302 return 0; 1303 1304 /* 1305 * Compare instructions 1306 */ 1307 case 0: /* cmp */ 1308 val = regs->gpr[ra]; 1309 val2 = regs->gpr[rb]; 1310 #ifdef __powerpc64__ 1311 if ((rd & 1) == 0) { 1312 /* word (32-bit) compare */ 1313 val = (int) val; 1314 val2 = (int) val2; 1315 } 1316 #endif 1317 do_cmp_signed(regs, op, val, val2, rd >> 2); 1318 return 1; 1319 1320 case 32: /* cmpl */ 1321 val = regs->gpr[ra]; 1322 val2 = regs->gpr[rb]; 1323 #ifdef __powerpc64__ 1324 if ((rd & 1) == 0) { 1325 /* word (32-bit) compare */ 1326 val = (unsigned int) val; 1327 val2 = (unsigned int) val2; 1328 } 1329 #endif 1330 do_cmp_unsigned(regs, op, val, val2, rd >> 2); 1331 return 1; 1332 1333 case 508: /* cmpb */ 1334 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); 1335 goto logical_done_nocc; 1336 1337 /* 1338 * Arithmetic instructions 1339 */ 1340 case 8: /* subfc */ 1341 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1342 regs->gpr[rb], 1); 1343 goto arith_done; 1344 #ifdef __powerpc64__ 1345 case 9: /* mulhdu */ 1346 asm("mulhdu %0,%1,%2" : "=r" (op->val) : 1347 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1348 goto arith_done; 1349 #endif 1350 case 10: /* addc */ 1351 add_with_carry(regs, op, rd, regs->gpr[ra], 1352 regs->gpr[rb], 0); 1353 goto arith_done; 1354 1355 case 11: /* mulhwu */ 1356 asm("mulhwu %0,%1,%2" : "=r" (op->val) : 1357 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1358 goto arith_done; 1359 1360 case 40: /* subf */ 1361 op->val = regs->gpr[rb] - regs->gpr[ra]; 1362 goto arith_done; 1363 #ifdef __powerpc64__ 1364 case 73: /* mulhd */ 1365 asm("mulhd %0,%1,%2" : "=r" (op->val) : 1366 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1367 goto arith_done; 1368 #endif 1369 case 75: /* mulhw */ 1370 asm("mulhw %0,%1,%2" : "=r" (op->val) : 1371 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1372 goto arith_done; 1373 1374 case 104: /* neg */ 1375 op->val = -regs->gpr[ra]; 1376 goto arith_done; 1377 1378 case 136: /* subfe */ 1379 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1380 regs->gpr[rb], regs->xer & XER_CA); 1381 goto arith_done; 1382 1383 case 138: /* adde */ 1384 add_with_carry(regs, op, rd, regs->gpr[ra], 1385 regs->gpr[rb], regs->xer & XER_CA); 1386 goto arith_done; 1387 1388 case 200: /* subfze */ 1389 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, 1390 regs->xer & XER_CA); 1391 goto arith_done; 1392 1393 case 202: /* addze */ 1394 add_with_carry(regs, op, rd, regs->gpr[ra], 0L, 1395 regs->xer & XER_CA); 1396 goto arith_done; 1397 1398 case 232: /* subfme */ 1399 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, 1400 regs->xer & XER_CA); 1401 goto arith_done; 1402 #ifdef __powerpc64__ 1403 case 233: /* mulld */ 1404 op->val = regs->gpr[ra] * regs->gpr[rb]; 1405 goto arith_done; 1406 #endif 1407 case 234: /* addme */ 1408 add_with_carry(regs, op, rd, regs->gpr[ra], -1L, 1409 regs->xer & XER_CA); 1410 goto arith_done; 1411 1412 case 235: /* mullw */ 1413 op->val = (unsigned int) regs->gpr[ra] * 1414 (unsigned int) regs->gpr[rb]; 1415 goto arith_done; 1416 1417 case 266: /* add */ 1418 op->val = regs->gpr[ra] + regs->gpr[rb]; 1419 goto arith_done; 1420 #ifdef __powerpc64__ 1421 case 457: /* divdu */ 1422 op->val = regs->gpr[ra] / regs->gpr[rb]; 1423 goto arith_done; 1424 #endif 1425 case 459: /* divwu */ 1426 op->val = (unsigned int) regs->gpr[ra] / 1427 (unsigned int) regs->gpr[rb]; 1428 goto arith_done; 1429 #ifdef __powerpc64__ 1430 case 489: /* divd */ 1431 op->val = (long int) regs->gpr[ra] / 1432 (long int) regs->gpr[rb]; 1433 goto arith_done; 1434 #endif 1435 case 491: /* divw */ 1436 op->val = (int) regs->gpr[ra] / 1437 (int) regs->gpr[rb]; 1438 goto arith_done; 1439 1440 1441 /* 1442 * Logical instructions 1443 */ 1444 case 15: /* isel */ 1445 mb = (instr >> 6) & 0x1f; /* bc */ 1446 val = (regs->ccr >> (31 - mb)) & 1; 1447 val2 = (ra) ? regs->gpr[ra] : 0; 1448 1449 op->val = (val) ? val2 : regs->gpr[rb]; 1450 goto compute_done; 1451 1452 case 26: /* cntlzw */ 1453 op->val = __builtin_clz((unsigned int) regs->gpr[rd]); 1454 goto logical_done; 1455 #ifdef __powerpc64__ 1456 case 58: /* cntlzd */ 1457 op->val = __builtin_clzl(regs->gpr[rd]); 1458 goto logical_done; 1459 #endif 1460 case 28: /* and */ 1461 op->val = regs->gpr[rd] & regs->gpr[rb]; 1462 goto logical_done; 1463 1464 case 60: /* andc */ 1465 op->val = regs->gpr[rd] & ~regs->gpr[rb]; 1466 goto logical_done; 1467 1468 case 122: /* popcntb */ 1469 do_popcnt(regs, op, regs->gpr[rd], 8); 1470 goto logical_done; 1471 1472 case 124: /* nor */ 1473 op->val = ~(regs->gpr[rd] | regs->gpr[rb]); 1474 goto logical_done; 1475 1476 case 154: /* prtyw */ 1477 do_prty(regs, op, regs->gpr[rd], 32); 1478 goto logical_done; 1479 1480 case 186: /* prtyd */ 1481 do_prty(regs, op, regs->gpr[rd], 64); 1482 goto logical_done; 1483 #ifdef CONFIG_PPC64 1484 case 252: /* bpermd */ 1485 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); 1486 goto logical_done; 1487 #endif 1488 case 284: /* xor */ 1489 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); 1490 goto logical_done; 1491 1492 case 316: /* xor */ 1493 op->val = regs->gpr[rd] ^ regs->gpr[rb]; 1494 goto logical_done; 1495 1496 case 378: /* popcntw */ 1497 do_popcnt(regs, op, regs->gpr[rd], 32); 1498 goto logical_done; 1499 1500 case 412: /* orc */ 1501 op->val = regs->gpr[rd] | ~regs->gpr[rb]; 1502 goto logical_done; 1503 1504 case 444: /* or */ 1505 op->val = regs->gpr[rd] | regs->gpr[rb]; 1506 goto logical_done; 1507 1508 case 476: /* nand */ 1509 op->val = ~(regs->gpr[rd] & regs->gpr[rb]); 1510 goto logical_done; 1511 #ifdef CONFIG_PPC64 1512 case 506: /* popcntd */ 1513 do_popcnt(regs, op, regs->gpr[rd], 64); 1514 goto logical_done; 1515 #endif 1516 case 922: /* extsh */ 1517 op->val = (signed short) regs->gpr[rd]; 1518 goto logical_done; 1519 1520 case 954: /* extsb */ 1521 op->val = (signed char) regs->gpr[rd]; 1522 goto logical_done; 1523 #ifdef __powerpc64__ 1524 case 986: /* extsw */ 1525 op->val = (signed int) regs->gpr[rd]; 1526 goto logical_done; 1527 #endif 1528 1529 /* 1530 * Shift instructions 1531 */ 1532 case 24: /* slw */ 1533 sh = regs->gpr[rb] & 0x3f; 1534 if (sh < 32) 1535 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; 1536 else 1537 op->val = 0; 1538 goto logical_done; 1539 1540 case 536: /* srw */ 1541 sh = regs->gpr[rb] & 0x3f; 1542 if (sh < 32) 1543 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; 1544 else 1545 op->val = 0; 1546 goto logical_done; 1547 1548 case 792: /* sraw */ 1549 op->type = COMPUTE + SETREG + SETXER; 1550 sh = regs->gpr[rb] & 0x3f; 1551 ival = (signed int) regs->gpr[rd]; 1552 op->val = ival >> (sh < 32 ? sh : 31); 1553 op->xerval = regs->xer; 1554 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) 1555 op->xerval |= XER_CA; 1556 else 1557 op->xerval &= ~XER_CA; 1558 goto logical_done; 1559 1560 case 824: /* srawi */ 1561 op->type = COMPUTE + SETREG + SETXER; 1562 sh = rb; 1563 ival = (signed int) regs->gpr[rd]; 1564 op->val = ival >> sh; 1565 op->xerval = regs->xer; 1566 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1567 op->xerval |= XER_CA; 1568 else 1569 op->xerval &= ~XER_CA; 1570 goto logical_done; 1571 1572 #ifdef __powerpc64__ 1573 case 27: /* sld */ 1574 sh = regs->gpr[rb] & 0x7f; 1575 if (sh < 64) 1576 op->val = regs->gpr[rd] << sh; 1577 else 1578 op->val = 0; 1579 goto logical_done; 1580 1581 case 539: /* srd */ 1582 sh = regs->gpr[rb] & 0x7f; 1583 if (sh < 64) 1584 op->val = regs->gpr[rd] >> sh; 1585 else 1586 op->val = 0; 1587 goto logical_done; 1588 1589 case 794: /* srad */ 1590 op->type = COMPUTE + SETREG + SETXER; 1591 sh = regs->gpr[rb] & 0x7f; 1592 ival = (signed long int) regs->gpr[rd]; 1593 op->val = ival >> (sh < 64 ? sh : 63); 1594 op->xerval = regs->xer; 1595 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) 1596 op->xerval |= XER_CA; 1597 else 1598 op->xerval &= ~XER_CA; 1599 goto logical_done; 1600 1601 case 826: /* sradi with sh_5 = 0 */ 1602 case 827: /* sradi with sh_5 = 1 */ 1603 op->type = COMPUTE + SETREG + SETXER; 1604 sh = rb | ((instr & 2) << 4); 1605 ival = (signed long int) regs->gpr[rd]; 1606 op->val = ival >> sh; 1607 op->xerval = regs->xer; 1608 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1609 op->xerval |= XER_CA; 1610 else 1611 op->xerval &= ~XER_CA; 1612 goto logical_done; 1613 #endif /* __powerpc64__ */ 1614 1615 /* 1616 * Cache instructions 1617 */ 1618 case 54: /* dcbst */ 1619 op->type = MKOP(CACHEOP, DCBST, 0); 1620 op->ea = xform_ea(instr, regs); 1621 return 0; 1622 1623 case 86: /* dcbf */ 1624 op->type = MKOP(CACHEOP, DCBF, 0); 1625 op->ea = xform_ea(instr, regs); 1626 return 0; 1627 1628 case 246: /* dcbtst */ 1629 op->type = MKOP(CACHEOP, DCBTST, 0); 1630 op->ea = xform_ea(instr, regs); 1631 op->reg = rd; 1632 return 0; 1633 1634 case 278: /* dcbt */ 1635 op->type = MKOP(CACHEOP, DCBTST, 0); 1636 op->ea = xform_ea(instr, regs); 1637 op->reg = rd; 1638 return 0; 1639 1640 case 982: /* icbi */ 1641 op->type = MKOP(CACHEOP, ICBI, 0); 1642 op->ea = xform_ea(instr, regs); 1643 return 0; 1644 } 1645 break; 1646 } 1647 1648 /* 1649 * Loads and stores. 1650 */ 1651 op->type = UNKNOWN; 1652 op->update_reg = ra; 1653 op->reg = rd; 1654 op->val = regs->gpr[rd]; 1655 u = (instr >> 20) & UPDATE; 1656 op->vsx_flags = 0; 1657 1658 switch (opcode) { 1659 case 31: 1660 u = instr & UPDATE; 1661 op->ea = xform_ea(instr, regs); 1662 switch ((instr >> 1) & 0x3ff) { 1663 case 20: /* lwarx */ 1664 op->type = MKOP(LARX, 0, 4); 1665 break; 1666 1667 case 150: /* stwcx. */ 1668 op->type = MKOP(STCX, 0, 4); 1669 break; 1670 1671 #ifdef __powerpc64__ 1672 case 84: /* ldarx */ 1673 op->type = MKOP(LARX, 0, 8); 1674 break; 1675 1676 case 214: /* stdcx. */ 1677 op->type = MKOP(STCX, 0, 8); 1678 break; 1679 1680 case 52: /* lbarx */ 1681 op->type = MKOP(LARX, 0, 1); 1682 break; 1683 1684 case 694: /* stbcx. */ 1685 op->type = MKOP(STCX, 0, 1); 1686 break; 1687 1688 case 116: /* lharx */ 1689 op->type = MKOP(LARX, 0, 2); 1690 break; 1691 1692 case 726: /* sthcx. */ 1693 op->type = MKOP(STCX, 0, 2); 1694 break; 1695 1696 case 276: /* lqarx */ 1697 if (!((rd & 1) || rd == ra || rd == rb)) 1698 op->type = MKOP(LARX, 0, 16); 1699 break; 1700 1701 case 182: /* stqcx. */ 1702 if (!(rd & 1)) 1703 op->type = MKOP(STCX, 0, 16); 1704 break; 1705 #endif 1706 1707 case 23: /* lwzx */ 1708 case 55: /* lwzux */ 1709 op->type = MKOP(LOAD, u, 4); 1710 break; 1711 1712 case 87: /* lbzx */ 1713 case 119: /* lbzux */ 1714 op->type = MKOP(LOAD, u, 1); 1715 break; 1716 1717 #ifdef CONFIG_ALTIVEC 1718 case 103: /* lvx */ 1719 case 359: /* lvxl */ 1720 op->type = MKOP(LOAD_VMX, 0, 16); 1721 op->element_size = 16; 1722 break; 1723 1724 case 231: /* stvx */ 1725 case 487: /* stvxl */ 1726 op->type = MKOP(STORE_VMX, 0, 16); 1727 break; 1728 #endif /* CONFIG_ALTIVEC */ 1729 1730 #ifdef __powerpc64__ 1731 case 21: /* ldx */ 1732 case 53: /* ldux */ 1733 op->type = MKOP(LOAD, u, 8); 1734 break; 1735 1736 case 149: /* stdx */ 1737 case 181: /* stdux */ 1738 op->type = MKOP(STORE, u, 8); 1739 break; 1740 #endif 1741 1742 case 151: /* stwx */ 1743 case 183: /* stwux */ 1744 op->type = MKOP(STORE, u, 4); 1745 break; 1746 1747 case 215: /* stbx */ 1748 case 247: /* stbux */ 1749 op->type = MKOP(STORE, u, 1); 1750 break; 1751 1752 case 279: /* lhzx */ 1753 case 311: /* lhzux */ 1754 op->type = MKOP(LOAD, u, 2); 1755 break; 1756 1757 #ifdef __powerpc64__ 1758 case 341: /* lwax */ 1759 case 373: /* lwaux */ 1760 op->type = MKOP(LOAD, SIGNEXT | u, 4); 1761 break; 1762 #endif 1763 1764 case 343: /* lhax */ 1765 case 375: /* lhaux */ 1766 op->type = MKOP(LOAD, SIGNEXT | u, 2); 1767 break; 1768 1769 case 407: /* sthx */ 1770 case 439: /* sthux */ 1771 op->type = MKOP(STORE, u, 2); 1772 break; 1773 1774 #ifdef __powerpc64__ 1775 case 532: /* ldbrx */ 1776 op->type = MKOP(LOAD, BYTEREV, 8); 1777 break; 1778 1779 #endif 1780 case 533: /* lswx */ 1781 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); 1782 break; 1783 1784 case 534: /* lwbrx */ 1785 op->type = MKOP(LOAD, BYTEREV, 4); 1786 break; 1787 1788 case 597: /* lswi */ 1789 if (rb == 0) 1790 rb = 32; /* # bytes to load */ 1791 op->type = MKOP(LOAD_MULTI, 0, rb); 1792 op->ea = 0; 1793 if (ra) 1794 op->ea = truncate_if_32bit(regs->msr, 1795 regs->gpr[ra]); 1796 break; 1797 1798 #ifdef CONFIG_PPC_FPU 1799 case 535: /* lfsx */ 1800 case 567: /* lfsux */ 1801 op->type = MKOP(LOAD_FP, u, 4); 1802 break; 1803 1804 case 599: /* lfdx */ 1805 case 631: /* lfdux */ 1806 op->type = MKOP(LOAD_FP, u, 8); 1807 break; 1808 1809 case 663: /* stfsx */ 1810 case 695: /* stfsux */ 1811 op->type = MKOP(STORE_FP, u, 4); 1812 break; 1813 1814 case 727: /* stfdx */ 1815 case 759: /* stfdux */ 1816 op->type = MKOP(STORE_FP, u, 8); 1817 break; 1818 #endif 1819 1820 #ifdef __powerpc64__ 1821 case 660: /* stdbrx */ 1822 op->type = MKOP(STORE, BYTEREV, 8); 1823 op->val = byterev_8(regs->gpr[rd]); 1824 break; 1825 1826 #endif 1827 case 661: /* stswx */ 1828 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); 1829 break; 1830 1831 case 662: /* stwbrx */ 1832 op->type = MKOP(STORE, BYTEREV, 4); 1833 op->val = byterev_4(regs->gpr[rd]); 1834 break; 1835 1836 case 725: 1837 if (rb == 0) 1838 rb = 32; /* # bytes to store */ 1839 op->type = MKOP(STORE_MULTI, 0, rb); 1840 op->ea = 0; 1841 if (ra) 1842 op->ea = truncate_if_32bit(regs->msr, 1843 regs->gpr[ra]); 1844 break; 1845 1846 case 790: /* lhbrx */ 1847 op->type = MKOP(LOAD, BYTEREV, 2); 1848 break; 1849 1850 case 918: /* sthbrx */ 1851 op->type = MKOP(STORE, BYTEREV, 2); 1852 op->val = byterev_2(regs->gpr[rd]); 1853 break; 1854 1855 #ifdef CONFIG_VSX 1856 case 12: /* lxsiwzx */ 1857 op->reg = rd | ((instr & 1) << 5); 1858 op->type = MKOP(LOAD_VSX, 0, 4); 1859 op->element_size = 8; 1860 break; 1861 1862 case 76: /* lxsiwax */ 1863 op->reg = rd | ((instr & 1) << 5); 1864 op->type = MKOP(LOAD_VSX, SIGNEXT, 4); 1865 op->element_size = 8; 1866 break; 1867 1868 case 140: /* stxsiwx */ 1869 op->reg = rd | ((instr & 1) << 5); 1870 op->type = MKOP(STORE_VSX, 0, 4); 1871 op->element_size = 8; 1872 break; 1873 1874 case 268: /* lxvx */ 1875 op->reg = rd | ((instr & 1) << 5); 1876 op->type = MKOP(LOAD_VSX, 0, 16); 1877 op->element_size = 16; 1878 op->vsx_flags = VSX_CHECK_VEC; 1879 break; 1880 1881 case 269: /* lxvl */ 1882 case 301: { /* lxvll */ 1883 int nb; 1884 op->reg = rd | ((instr & 1) << 5); 1885 op->ea = ra ? regs->gpr[ra] : 0; 1886 nb = regs->gpr[rb] & 0xff; 1887 if (nb > 16) 1888 nb = 16; 1889 op->type = MKOP(LOAD_VSX, 0, nb); 1890 op->element_size = 16; 1891 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | 1892 VSX_CHECK_VEC; 1893 break; 1894 } 1895 case 332: /* lxvdsx */ 1896 op->reg = rd | ((instr & 1) << 5); 1897 op->type = MKOP(LOAD_VSX, 0, 8); 1898 op->element_size = 8; 1899 op->vsx_flags = VSX_SPLAT; 1900 break; 1901 1902 case 364: /* lxvwsx */ 1903 op->reg = rd | ((instr & 1) << 5); 1904 op->type = MKOP(LOAD_VSX, 0, 4); 1905 op->element_size = 4; 1906 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; 1907 break; 1908 1909 case 396: /* stxvx */ 1910 op->reg = rd | ((instr & 1) << 5); 1911 op->type = MKOP(STORE_VSX, 0, 16); 1912 op->element_size = 16; 1913 op->vsx_flags = VSX_CHECK_VEC; 1914 break; 1915 1916 case 397: /* stxvl */ 1917 case 429: { /* stxvll */ 1918 int nb; 1919 op->reg = rd | ((instr & 1) << 5); 1920 op->ea = ra ? regs->gpr[ra] : 0; 1921 nb = regs->gpr[rb] & 0xff; 1922 if (nb > 16) 1923 nb = 16; 1924 op->type = MKOP(STORE_VSX, 0, nb); 1925 op->element_size = 16; 1926 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | 1927 VSX_CHECK_VEC; 1928 break; 1929 } 1930 case 524: /* lxsspx */ 1931 op->reg = rd | ((instr & 1) << 5); 1932 op->type = MKOP(LOAD_VSX, 0, 4); 1933 op->element_size = 8; 1934 op->vsx_flags = VSX_FPCONV; 1935 break; 1936 1937 case 588: /* lxsdx */ 1938 op->reg = rd | ((instr & 1) << 5); 1939 op->type = MKOP(LOAD_VSX, 0, 8); 1940 op->element_size = 8; 1941 break; 1942 1943 case 652: /* stxsspx */ 1944 op->reg = rd | ((instr & 1) << 5); 1945 op->type = MKOP(STORE_VSX, 0, 4); 1946 op->element_size = 8; 1947 op->vsx_flags = VSX_FPCONV; 1948 break; 1949 1950 case 716: /* stxsdx */ 1951 op->reg = rd | ((instr & 1) << 5); 1952 op->type = MKOP(STORE_VSX, 0, 8); 1953 op->element_size = 8; 1954 break; 1955 1956 case 780: /* lxvw4x */ 1957 op->reg = rd | ((instr & 1) << 5); 1958 op->type = MKOP(LOAD_VSX, 0, 16); 1959 op->element_size = 4; 1960 break; 1961 1962 case 781: /* lxsibzx */ 1963 op->reg = rd | ((instr & 1) << 5); 1964 op->type = MKOP(LOAD_VSX, 0, 1); 1965 op->element_size = 8; 1966 op->vsx_flags = VSX_CHECK_VEC; 1967 break; 1968 1969 case 812: /* lxvh8x */ 1970 op->reg = rd | ((instr & 1) << 5); 1971 op->type = MKOP(LOAD_VSX, 0, 16); 1972 op->element_size = 2; 1973 op->vsx_flags = VSX_CHECK_VEC; 1974 break; 1975 1976 case 813: /* lxsihzx */ 1977 op->reg = rd | ((instr & 1) << 5); 1978 op->type = MKOP(LOAD_VSX, 0, 2); 1979 op->element_size = 8; 1980 op->vsx_flags = VSX_CHECK_VEC; 1981 break; 1982 1983 case 844: /* lxvd2x */ 1984 op->reg = rd | ((instr & 1) << 5); 1985 op->type = MKOP(LOAD_VSX, 0, 16); 1986 op->element_size = 8; 1987 break; 1988 1989 case 876: /* lxvb16x */ 1990 op->reg = rd | ((instr & 1) << 5); 1991 op->type = MKOP(LOAD_VSX, 0, 16); 1992 op->element_size = 1; 1993 op->vsx_flags = VSX_CHECK_VEC; 1994 break; 1995 1996 case 908: /* stxvw4x */ 1997 op->reg = rd | ((instr & 1) << 5); 1998 op->type = MKOP(STORE_VSX, 0, 16); 1999 op->element_size = 4; 2000 break; 2001 2002 case 909: /* stxsibx */ 2003 op->reg = rd | ((instr & 1) << 5); 2004 op->type = MKOP(STORE_VSX, 0, 1); 2005 op->element_size = 8; 2006 op->vsx_flags = VSX_CHECK_VEC; 2007 break; 2008 2009 case 940: /* stxvh8x */ 2010 op->reg = rd | ((instr & 1) << 5); 2011 op->type = MKOP(STORE_VSX, 0, 16); 2012 op->element_size = 2; 2013 op->vsx_flags = VSX_CHECK_VEC; 2014 break; 2015 2016 case 941: /* stxsihx */ 2017 op->reg = rd | ((instr & 1) << 5); 2018 op->type = MKOP(STORE_VSX, 0, 2); 2019 op->element_size = 8; 2020 op->vsx_flags = VSX_CHECK_VEC; 2021 break; 2022 2023 case 972: /* stxvd2x */ 2024 op->reg = rd | ((instr & 1) << 5); 2025 op->type = MKOP(STORE_VSX, 0, 16); 2026 op->element_size = 8; 2027 break; 2028 2029 case 1004: /* stxvb16x */ 2030 op->reg = rd | ((instr & 1) << 5); 2031 op->type = MKOP(STORE_VSX, 0, 16); 2032 op->element_size = 1; 2033 op->vsx_flags = VSX_CHECK_VEC; 2034 break; 2035 2036 #endif /* CONFIG_VSX */ 2037 } 2038 break; 2039 2040 case 32: /* lwz */ 2041 case 33: /* lwzu */ 2042 op->type = MKOP(LOAD, u, 4); 2043 op->ea = dform_ea(instr, regs); 2044 break; 2045 2046 case 34: /* lbz */ 2047 case 35: /* lbzu */ 2048 op->type = MKOP(LOAD, u, 1); 2049 op->ea = dform_ea(instr, regs); 2050 break; 2051 2052 case 36: /* stw */ 2053 case 37: /* stwu */ 2054 op->type = MKOP(STORE, u, 4); 2055 op->ea = dform_ea(instr, regs); 2056 break; 2057 2058 case 38: /* stb */ 2059 case 39: /* stbu */ 2060 op->type = MKOP(STORE, u, 1); 2061 op->ea = dform_ea(instr, regs); 2062 break; 2063 2064 case 40: /* lhz */ 2065 case 41: /* lhzu */ 2066 op->type = MKOP(LOAD, u, 2); 2067 op->ea = dform_ea(instr, regs); 2068 break; 2069 2070 case 42: /* lha */ 2071 case 43: /* lhau */ 2072 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2073 op->ea = dform_ea(instr, regs); 2074 break; 2075 2076 case 44: /* sth */ 2077 case 45: /* sthu */ 2078 op->type = MKOP(STORE, u, 2); 2079 op->ea = dform_ea(instr, regs); 2080 break; 2081 2082 case 46: /* lmw */ 2083 if (ra >= rd) 2084 break; /* invalid form, ra in range to load */ 2085 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); 2086 op->ea = dform_ea(instr, regs); 2087 break; 2088 2089 case 47: /* stmw */ 2090 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); 2091 op->ea = dform_ea(instr, regs); 2092 break; 2093 2094 #ifdef CONFIG_PPC_FPU 2095 case 48: /* lfs */ 2096 case 49: /* lfsu */ 2097 op->type = MKOP(LOAD_FP, u, 4); 2098 op->ea = dform_ea(instr, regs); 2099 break; 2100 2101 case 50: /* lfd */ 2102 case 51: /* lfdu */ 2103 op->type = MKOP(LOAD_FP, u, 8); 2104 op->ea = dform_ea(instr, regs); 2105 break; 2106 2107 case 52: /* stfs */ 2108 case 53: /* stfsu */ 2109 op->type = MKOP(STORE_FP, u, 4); 2110 op->ea = dform_ea(instr, regs); 2111 break; 2112 2113 case 54: /* stfd */ 2114 case 55: /* stfdu */ 2115 op->type = MKOP(STORE_FP, u, 8); 2116 op->ea = dform_ea(instr, regs); 2117 break; 2118 #endif 2119 2120 #ifdef __powerpc64__ 2121 case 56: /* lq */ 2122 if (!((rd & 1) || (rd == ra))) 2123 op->type = MKOP(LOAD, 0, 16); 2124 op->ea = dqform_ea(instr, regs); 2125 break; 2126 #endif 2127 2128 #ifdef CONFIG_VSX 2129 case 57: /* lxsd, lxssp */ 2130 op->ea = dsform_ea(instr, regs); 2131 switch (instr & 3) { 2132 case 2: /* lxsd */ 2133 op->reg = rd + 32; 2134 op->type = MKOP(LOAD_VSX, 0, 8); 2135 op->element_size = 8; 2136 op->vsx_flags = VSX_CHECK_VEC; 2137 break; 2138 case 3: /* lxssp */ 2139 op->reg = rd + 32; 2140 op->type = MKOP(LOAD_VSX, 0, 4); 2141 op->element_size = 8; 2142 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2143 break; 2144 } 2145 break; 2146 #endif /* CONFIG_VSX */ 2147 2148 #ifdef __powerpc64__ 2149 case 58: /* ld[u], lwa */ 2150 op->ea = dsform_ea(instr, regs); 2151 switch (instr & 3) { 2152 case 0: /* ld */ 2153 op->type = MKOP(LOAD, 0, 8); 2154 break; 2155 case 1: /* ldu */ 2156 op->type = MKOP(LOAD, UPDATE, 8); 2157 break; 2158 case 2: /* lwa */ 2159 op->type = MKOP(LOAD, SIGNEXT, 4); 2160 break; 2161 } 2162 break; 2163 #endif 2164 2165 #ifdef CONFIG_VSX 2166 case 61: /* lxv, stxsd, stxssp, stxv */ 2167 switch (instr & 7) { 2168 case 1: /* lxv */ 2169 op->ea = dqform_ea(instr, regs); 2170 if (instr & 8) 2171 op->reg = rd + 32; 2172 op->type = MKOP(LOAD_VSX, 0, 16); 2173 op->element_size = 16; 2174 op->vsx_flags = VSX_CHECK_VEC; 2175 break; 2176 2177 case 2: /* stxsd with LSB of DS field = 0 */ 2178 case 6: /* stxsd with LSB of DS field = 1 */ 2179 op->ea = dsform_ea(instr, regs); 2180 op->reg = rd + 32; 2181 op->type = MKOP(STORE_VSX, 0, 8); 2182 op->element_size = 8; 2183 op->vsx_flags = VSX_CHECK_VEC; 2184 break; 2185 2186 case 3: /* stxssp with LSB of DS field = 0 */ 2187 case 7: /* stxssp with LSB of DS field = 1 */ 2188 op->ea = dsform_ea(instr, regs); 2189 op->reg = rd + 32; 2190 op->type = MKOP(STORE_VSX, 0, 4); 2191 op->element_size = 8; 2192 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2193 break; 2194 2195 case 5: /* stxv */ 2196 op->ea = dqform_ea(instr, regs); 2197 if (instr & 8) 2198 op->reg = rd + 32; 2199 op->type = MKOP(STORE_VSX, 0, 16); 2200 op->element_size = 16; 2201 op->vsx_flags = VSX_CHECK_VEC; 2202 break; 2203 } 2204 break; 2205 #endif /* CONFIG_VSX */ 2206 2207 #ifdef __powerpc64__ 2208 case 62: /* std[u] */ 2209 op->ea = dsform_ea(instr, regs); 2210 switch (instr & 3) { 2211 case 0: /* std */ 2212 op->type = MKOP(STORE, 0, 8); 2213 break; 2214 case 1: /* stdu */ 2215 op->type = MKOP(STORE, UPDATE, 8); 2216 break; 2217 case 2: /* stq */ 2218 if (!(rd & 1)) 2219 op->type = MKOP(STORE, 0, 16); 2220 break; 2221 } 2222 break; 2223 #endif /* __powerpc64__ */ 2224 2225 } 2226 return 0; 2227 2228 logical_done: 2229 if (instr & 1) 2230 set_cr0(regs, op, ra); 2231 logical_done_nocc: 2232 op->reg = ra; 2233 op->type |= SETREG; 2234 return 1; 2235 2236 arith_done: 2237 if (instr & 1) 2238 set_cr0(regs, op, rd); 2239 compute_done: 2240 op->reg = rd; 2241 op->type |= SETREG; 2242 return 1; 2243 2244 priv: 2245 op->type = INTERRUPT | 0x700; 2246 op->val = SRR1_PROGPRIV; 2247 return 0; 2248 2249 trap: 2250 op->type = INTERRUPT | 0x700; 2251 op->val = SRR1_PROGTRAP; 2252 return 0; 2253 } 2254 EXPORT_SYMBOL_GPL(analyse_instr); 2255 NOKPROBE_SYMBOL(analyse_instr); 2256 2257 /* 2258 * For PPC32 we always use stwu with r1 to change the stack pointer. 2259 * So this emulated store may corrupt the exception frame, now we 2260 * have to provide the exception frame trampoline, which is pushed 2261 * below the kprobed function stack. So we only update gpr[1] but 2262 * don't emulate the real store operation. We will do real store 2263 * operation safely in exception return code by checking this flag. 2264 */ 2265 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) 2266 { 2267 #ifdef CONFIG_PPC32 2268 /* 2269 * Check if we will touch kernel stack overflow 2270 */ 2271 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { 2272 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); 2273 return -EINVAL; 2274 } 2275 #endif /* CONFIG_PPC32 */ 2276 /* 2277 * Check if we already set since that means we'll 2278 * lose the previous value. 2279 */ 2280 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); 2281 set_thread_flag(TIF_EMULATE_STACK_STORE); 2282 return 0; 2283 } 2284 2285 static nokprobe_inline void do_signext(unsigned long *valp, int size) 2286 { 2287 switch (size) { 2288 case 2: 2289 *valp = (signed short) *valp; 2290 break; 2291 case 4: 2292 *valp = (signed int) *valp; 2293 break; 2294 } 2295 } 2296 2297 static nokprobe_inline void do_byterev(unsigned long *valp, int size) 2298 { 2299 switch (size) { 2300 case 2: 2301 *valp = byterev_2(*valp); 2302 break; 2303 case 4: 2304 *valp = byterev_4(*valp); 2305 break; 2306 #ifdef __powerpc64__ 2307 case 8: 2308 *valp = byterev_8(*valp); 2309 break; 2310 #endif 2311 } 2312 } 2313 2314 /* 2315 * Emulate an instruction that can be executed just by updating 2316 * fields in *regs. 2317 */ 2318 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) 2319 { 2320 unsigned long next_pc; 2321 2322 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); 2323 switch (op->type & INSTR_TYPE_MASK) { 2324 case COMPUTE: 2325 if (op->type & SETREG) 2326 regs->gpr[op->reg] = op->val; 2327 if (op->type & SETCC) 2328 regs->ccr = op->ccval; 2329 if (op->type & SETXER) 2330 regs->xer = op->xerval; 2331 break; 2332 2333 case BRANCH: 2334 if (op->type & SETLK) 2335 regs->link = next_pc; 2336 if (op->type & BRTAKEN) 2337 next_pc = op->val; 2338 if (op->type & DECCTR) 2339 --regs->ctr; 2340 break; 2341 2342 case BARRIER: 2343 switch (op->type & BARRIER_MASK) { 2344 case BARRIER_SYNC: 2345 mb(); 2346 break; 2347 case BARRIER_ISYNC: 2348 isync(); 2349 break; 2350 case BARRIER_EIEIO: 2351 eieio(); 2352 break; 2353 case BARRIER_LWSYNC: 2354 asm volatile("lwsync" : : : "memory"); 2355 break; 2356 case BARRIER_PTESYNC: 2357 asm volatile("ptesync" : : : "memory"); 2358 break; 2359 } 2360 break; 2361 2362 case MFSPR: 2363 switch (op->spr) { 2364 case SPRN_XER: 2365 regs->gpr[op->reg] = regs->xer & 0xffffffffUL; 2366 break; 2367 case SPRN_LR: 2368 regs->gpr[op->reg] = regs->link; 2369 break; 2370 case SPRN_CTR: 2371 regs->gpr[op->reg] = regs->ctr; 2372 break; 2373 default: 2374 WARN_ON_ONCE(1); 2375 } 2376 break; 2377 2378 case MTSPR: 2379 switch (op->spr) { 2380 case SPRN_XER: 2381 regs->xer = op->val & 0xffffffffUL; 2382 break; 2383 case SPRN_LR: 2384 regs->link = op->val; 2385 break; 2386 case SPRN_CTR: 2387 regs->ctr = op->val; 2388 break; 2389 default: 2390 WARN_ON_ONCE(1); 2391 } 2392 break; 2393 2394 default: 2395 WARN_ON_ONCE(1); 2396 } 2397 regs->nip = next_pc; 2398 } 2399 2400 /* 2401 * Emulate instructions that cause a transfer of control, 2402 * loads and stores, and a few other instructions. 2403 * Returns 1 if the step was emulated, 0 if not, 2404 * or -1 if the instruction is one that should not be stepped, 2405 * such as an rfid, or a mtmsrd that would clear MSR_RI. 2406 */ 2407 int emulate_step(struct pt_regs *regs, unsigned int instr) 2408 { 2409 struct instruction_op op; 2410 int r, err, size; 2411 unsigned long val; 2412 unsigned int cr; 2413 int i, rd, nb; 2414 2415 r = analyse_instr(&op, regs, instr); 2416 if (r < 0) 2417 return r; 2418 if (r > 0) { 2419 emulate_update_regs(regs, &op); 2420 return 1; 2421 } 2422 2423 err = 0; 2424 size = GETSIZE(op.type); 2425 switch (op.type & INSTR_TYPE_MASK) { 2426 case CACHEOP: 2427 if (!address_ok(regs, op.ea, 8)) 2428 return 0; 2429 switch (op.type & CACHEOP_MASK) { 2430 case DCBST: 2431 __cacheop_user_asmx(op.ea, err, "dcbst"); 2432 break; 2433 case DCBF: 2434 __cacheop_user_asmx(op.ea, err, "dcbf"); 2435 break; 2436 case DCBTST: 2437 if (op.reg == 0) 2438 prefetchw((void *) op.ea); 2439 break; 2440 case DCBT: 2441 if (op.reg == 0) 2442 prefetch((void *) op.ea); 2443 break; 2444 case ICBI: 2445 __cacheop_user_asmx(op.ea, err, "icbi"); 2446 break; 2447 } 2448 if (err) 2449 return 0; 2450 goto instr_done; 2451 2452 case LARX: 2453 if (op.ea & (size - 1)) 2454 break; /* can't handle misaligned */ 2455 if (!address_ok(regs, op.ea, size)) 2456 return 0; 2457 err = 0; 2458 switch (size) { 2459 #ifdef __powerpc64__ 2460 case 1: 2461 __get_user_asmx(val, op.ea, err, "lbarx"); 2462 break; 2463 case 2: 2464 __get_user_asmx(val, op.ea, err, "lharx"); 2465 break; 2466 #endif 2467 case 4: 2468 __get_user_asmx(val, op.ea, err, "lwarx"); 2469 break; 2470 #ifdef __powerpc64__ 2471 case 8: 2472 __get_user_asmx(val, op.ea, err, "ldarx"); 2473 break; 2474 case 16: 2475 err = do_lqarx(op.ea, ®s->gpr[op.reg]); 2476 goto ldst_done; 2477 #endif 2478 default: 2479 return 0; 2480 } 2481 if (!err) 2482 regs->gpr[op.reg] = val; 2483 goto ldst_done; 2484 2485 case STCX: 2486 if (op.ea & (size - 1)) 2487 break; /* can't handle misaligned */ 2488 if (!address_ok(regs, op.ea, size)) 2489 return 0; 2490 err = 0; 2491 switch (size) { 2492 #ifdef __powerpc64__ 2493 case 1: 2494 __put_user_asmx(op.val, op.ea, err, "stbcx.", cr); 2495 break; 2496 case 2: 2497 __put_user_asmx(op.val, op.ea, err, "stbcx.", cr); 2498 break; 2499 #endif 2500 case 4: 2501 __put_user_asmx(op.val, op.ea, err, "stwcx.", cr); 2502 break; 2503 #ifdef __powerpc64__ 2504 case 8: 2505 __put_user_asmx(op.val, op.ea, err, "stdcx.", cr); 2506 break; 2507 case 16: 2508 err = do_stqcx(op.ea, regs->gpr[op.reg], 2509 regs->gpr[op.reg + 1], &cr); 2510 break; 2511 #endif 2512 default: 2513 return 0; 2514 } 2515 if (!err) 2516 regs->ccr = (regs->ccr & 0x0fffffff) | 2517 (cr & 0xe0000000) | 2518 ((regs->xer >> 3) & 0x10000000); 2519 goto ldst_done; 2520 2521 case LOAD: 2522 #ifdef __powerpc64__ 2523 if (size == 16) { 2524 err = emulate_lq(regs, op.ea, op.reg); 2525 goto ldst_done; 2526 } 2527 #endif 2528 err = read_mem(®s->gpr[op.reg], op.ea, size, regs); 2529 if (!err) { 2530 if (op.type & SIGNEXT) 2531 do_signext(®s->gpr[op.reg], size); 2532 if (op.type & BYTEREV) 2533 do_byterev(®s->gpr[op.reg], size); 2534 } 2535 goto ldst_done; 2536 2537 #ifdef CONFIG_PPC_FPU 2538 case LOAD_FP: 2539 if (!(regs->msr & MSR_FP)) 2540 return 0; 2541 if (size == 4) 2542 err = do_fp_load(op.reg, do_lfs, op.ea, size, regs); 2543 else 2544 err = do_fp_load(op.reg, do_lfd, op.ea, size, regs); 2545 goto ldst_done; 2546 #endif 2547 #ifdef CONFIG_ALTIVEC 2548 case LOAD_VMX: 2549 if (!(regs->msr & MSR_VEC)) 2550 return 0; 2551 err = do_vec_load(op.reg, do_lvx, op.ea, regs); 2552 goto ldst_done; 2553 #endif 2554 #ifdef CONFIG_VSX 2555 case LOAD_VSX: { 2556 char mem[16]; 2557 union vsx_reg buf; 2558 unsigned long msrbit = MSR_VSX; 2559 2560 /* 2561 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 2562 * when the target of the instruction is a vector register. 2563 */ 2564 if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC)) 2565 msrbit = MSR_VEC; 2566 if (!(regs->msr & msrbit)) 2567 return 0; 2568 if (!address_ok(regs, op.ea, size) || 2569 __copy_from_user(mem, (void __user *)op.ea, size)) 2570 return 0; 2571 2572 emulate_vsx_load(&op, &buf, mem); 2573 load_vsrn(op.reg, &buf); 2574 goto ldst_done; 2575 } 2576 #endif 2577 case LOAD_MULTI: 2578 if (regs->msr & MSR_LE) 2579 return 0; 2580 rd = op.reg; 2581 for (i = 0; i < size; i += 4) { 2582 nb = size - i; 2583 if (nb > 4) 2584 nb = 4; 2585 err = read_mem(®s->gpr[rd], op.ea, nb, regs); 2586 if (err) 2587 return 0; 2588 if (nb < 4) /* left-justify last bytes */ 2589 regs->gpr[rd] <<= 32 - 8 * nb; 2590 op.ea += 4; 2591 ++rd; 2592 } 2593 goto instr_done; 2594 2595 case STORE: 2596 #ifdef __powerpc64__ 2597 if (size == 16) { 2598 err = emulate_stq(regs, op.ea, op.reg); 2599 goto ldst_done; 2600 } 2601 #endif 2602 if ((op.type & UPDATE) && size == sizeof(long) && 2603 op.reg == 1 && op.update_reg == 1 && 2604 !(regs->msr & MSR_PR) && 2605 op.ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { 2606 err = handle_stack_update(op.ea, regs); 2607 goto ldst_done; 2608 } 2609 err = write_mem(op.val, op.ea, size, regs); 2610 goto ldst_done; 2611 2612 #ifdef CONFIG_PPC_FPU 2613 case STORE_FP: 2614 if (!(regs->msr & MSR_FP)) 2615 return 0; 2616 if (size == 4) 2617 err = do_fp_store(op.reg, do_stfs, op.ea, size, regs); 2618 else 2619 err = do_fp_store(op.reg, do_stfd, op.ea, size, regs); 2620 goto ldst_done; 2621 #endif 2622 #ifdef CONFIG_ALTIVEC 2623 case STORE_VMX: 2624 if (!(regs->msr & MSR_VEC)) 2625 return 0; 2626 err = do_vec_store(op.reg, do_stvx, op.ea, regs); 2627 goto ldst_done; 2628 #endif 2629 #ifdef CONFIG_VSX 2630 case STORE_VSX: { 2631 char mem[16]; 2632 union vsx_reg buf; 2633 unsigned long msrbit = MSR_VSX; 2634 2635 /* 2636 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 2637 * when the target of the instruction is a vector register. 2638 */ 2639 if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC)) 2640 msrbit = MSR_VEC; 2641 if (!(regs->msr & msrbit)) 2642 return 0; 2643 if (!address_ok(regs, op.ea, size)) 2644 return 0; 2645 2646 store_vsrn(op.reg, &buf); 2647 emulate_vsx_store(&op, &buf, mem); 2648 if (__copy_to_user((void __user *)op.ea, mem, size)) 2649 return 0; 2650 goto ldst_done; 2651 } 2652 #endif 2653 case STORE_MULTI: 2654 if (regs->msr & MSR_LE) 2655 return 0; 2656 rd = op.reg; 2657 for (i = 0; i < size; i += 4) { 2658 val = regs->gpr[rd]; 2659 nb = size - i; 2660 if (nb > 4) 2661 nb = 4; 2662 else 2663 val >>= 32 - 8 * nb; 2664 err = write_mem(val, op.ea, nb, regs); 2665 if (err) 2666 return 0; 2667 op.ea += 4; 2668 ++rd; 2669 } 2670 goto instr_done; 2671 2672 case MFMSR: 2673 regs->gpr[op.reg] = regs->msr & MSR_MASK; 2674 goto instr_done; 2675 2676 case MTMSR: 2677 val = regs->gpr[op.reg]; 2678 if ((val & MSR_RI) == 0) 2679 /* can't step mtmsr[d] that would clear MSR_RI */ 2680 return -1; 2681 /* here op.val is the mask of bits to change */ 2682 regs->msr = (regs->msr & ~op.val) | (val & op.val); 2683 goto instr_done; 2684 2685 #ifdef CONFIG_PPC64 2686 case SYSCALL: /* sc */ 2687 /* 2688 * N.B. this uses knowledge about how the syscall 2689 * entry code works. If that is changed, this will 2690 * need to be changed also. 2691 */ 2692 if (regs->gpr[0] == 0x1ebe && 2693 cpu_has_feature(CPU_FTR_REAL_LE)) { 2694 regs->msr ^= MSR_LE; 2695 goto instr_done; 2696 } 2697 regs->gpr[9] = regs->gpr[13]; 2698 regs->gpr[10] = MSR_KERNEL; 2699 regs->gpr[11] = regs->nip + 4; 2700 regs->gpr[12] = regs->msr & MSR_MASK; 2701 regs->gpr[13] = (unsigned long) get_paca(); 2702 regs->nip = (unsigned long) &system_call_common; 2703 regs->msr = MSR_KERNEL; 2704 return 1; 2705 2706 case RFI: 2707 return -1; 2708 #endif 2709 } 2710 return 0; 2711 2712 ldst_done: 2713 if (err) 2714 return 0; 2715 if (op.type & UPDATE) 2716 regs->gpr[op.update_reg] = op.ea; 2717 2718 instr_done: 2719 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); 2720 return 1; 2721 } 2722 NOKPROBE_SYMBOL(emulate_step); 2723