1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * Copyright 2011 Freescale Semiconductor, Inc. 17 * 18 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 19 */ 20 21 #include <linux/jiffies.h> 22 #include <linux/hrtimer.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/kvm_host.h> 26 #include <linux/clockchips.h> 27 28 #include <asm/reg.h> 29 #include <asm/time.h> 30 #include <asm/byteorder.h> 31 #include <asm/kvm_ppc.h> 32 #include <asm/disassemble.h> 33 #include "timing.h" 34 #include "trace.h" 35 36 #define OP_TRAP 3 37 #define OP_TRAP_64 2 38 39 #define OP_31_XOP_TRAP 4 40 #define OP_31_XOP_LWZX 23 41 #define OP_31_XOP_DCBST 54 42 #define OP_31_XOP_TRAP_64 68 43 #define OP_31_XOP_DCBF 86 44 #define OP_31_XOP_LBZX 87 45 #define OP_31_XOP_STWX 151 46 #define OP_31_XOP_STBX 215 47 #define OP_31_XOP_LBZUX 119 48 #define OP_31_XOP_STBUX 247 49 #define OP_31_XOP_LHZX 279 50 #define OP_31_XOP_LHZUX 311 51 #define OP_31_XOP_MFSPR 339 52 #define OP_31_XOP_LHAX 343 53 #define OP_31_XOP_STHX 407 54 #define OP_31_XOP_STHUX 439 55 #define OP_31_XOP_MTSPR 467 56 #define OP_31_XOP_DCBI 470 57 #define OP_31_XOP_LWBRX 534 58 #define OP_31_XOP_TLBSYNC 566 59 #define OP_31_XOP_STWBRX 662 60 #define OP_31_XOP_LHBRX 790 61 #define OP_31_XOP_STHBRX 918 62 63 #define OP_LWZ 32 64 #define OP_LD 58 65 #define OP_LWZU 33 66 #define OP_LBZ 34 67 #define OP_LBZU 35 68 #define OP_STW 36 69 #define OP_STWU 37 70 #define OP_STD 62 71 #define OP_STB 38 72 #define OP_STBU 39 73 #define OP_LHZ 40 74 #define OP_LHZU 41 75 #define OP_LHA 42 76 #define OP_LHAU 43 77 #define OP_STH 44 78 #define OP_STHU 45 79 80 void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) 81 { 82 unsigned long dec_nsec; 83 unsigned long long dec_time; 84 85 pr_debug("mtDEC: %x\n", vcpu->arch.dec); 86 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 87 88 #ifdef CONFIG_PPC_BOOK3S 89 /* mtdec lowers the interrupt line when positive. */ 90 kvmppc_core_dequeue_dec(vcpu); 91 92 /* POWER4+ triggers a dec interrupt if the value is < 0 */ 93 if (vcpu->arch.dec & 0x80000000) { 94 kvmppc_core_queue_dec(vcpu); 95 return; 96 } 97 #endif 98 99 #ifdef CONFIG_BOOKE 100 /* On BOOKE, DEC = 0 is as good as decrementer not enabled */ 101 if (vcpu->arch.dec == 0) 102 return; 103 #endif 104 105 /* 106 * The decrementer ticks at the same rate as the timebase, so 107 * that's how we convert the guest DEC value to the number of 108 * host ticks. 109 */ 110 111 dec_time = vcpu->arch.dec; 112 /* 113 * Guest timebase ticks at the same frequency as host decrementer. 114 * So use the host decrementer calculations for decrementer emulation. 115 */ 116 dec_time = dec_time << decrementer_clockevent.shift; 117 do_div(dec_time, decrementer_clockevent.mult); 118 dec_nsec = do_div(dec_time, NSEC_PER_SEC); 119 hrtimer_start(&vcpu->arch.dec_timer, 120 ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL); 121 vcpu->arch.dec_jiffies = get_tb(); 122 } 123 124 u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb) 125 { 126 u64 jd = tb - vcpu->arch.dec_jiffies; 127 128 #ifdef CONFIG_BOOKE 129 if (vcpu->arch.dec < jd) 130 return 0; 131 #endif 132 133 return vcpu->arch.dec - jd; 134 } 135 136 static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) 137 { 138 enum emulation_result emulated = EMULATE_DONE; 139 ulong spr_val = kvmppc_get_gpr(vcpu, rs); 140 141 switch (sprn) { 142 case SPRN_SRR0: 143 vcpu->arch.shared->srr0 = spr_val; 144 break; 145 case SPRN_SRR1: 146 vcpu->arch.shared->srr1 = spr_val; 147 break; 148 149 /* XXX We need to context-switch the timebase for 150 * watchdog and FIT. */ 151 case SPRN_TBWL: break; 152 case SPRN_TBWU: break; 153 154 case SPRN_DEC: 155 vcpu->arch.dec = spr_val; 156 kvmppc_emulate_dec(vcpu); 157 break; 158 159 case SPRN_SPRG0: 160 vcpu->arch.shared->sprg0 = spr_val; 161 break; 162 case SPRN_SPRG1: 163 vcpu->arch.shared->sprg1 = spr_val; 164 break; 165 case SPRN_SPRG2: 166 vcpu->arch.shared->sprg2 = spr_val; 167 break; 168 case SPRN_SPRG3: 169 vcpu->arch.shared->sprg3 = spr_val; 170 break; 171 172 /* PIR can legally be written, but we ignore it */ 173 case SPRN_PIR: break; 174 175 default: 176 emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, 177 spr_val); 178 if (emulated == EMULATE_FAIL) 179 printk(KERN_INFO "mtspr: unknown spr " 180 "0x%x\n", sprn); 181 break; 182 } 183 184 kvmppc_set_exit_type(vcpu, EMULATED_MTSPR_EXITS); 185 186 return emulated; 187 } 188 189 static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) 190 { 191 enum emulation_result emulated = EMULATE_DONE; 192 ulong spr_val = 0; 193 194 switch (sprn) { 195 case SPRN_SRR0: 196 spr_val = vcpu->arch.shared->srr0; 197 break; 198 case SPRN_SRR1: 199 spr_val = vcpu->arch.shared->srr1; 200 break; 201 case SPRN_PVR: 202 spr_val = vcpu->arch.pvr; 203 break; 204 case SPRN_PIR: 205 spr_val = vcpu->vcpu_id; 206 break; 207 208 /* Note: mftb and TBRL/TBWL are user-accessible, so 209 * the guest can always access the real TB anyways. 210 * In fact, we probably will never see these traps. */ 211 case SPRN_TBWL: 212 spr_val = get_tb() >> 32; 213 break; 214 case SPRN_TBWU: 215 spr_val = get_tb(); 216 break; 217 218 case SPRN_SPRG0: 219 spr_val = vcpu->arch.shared->sprg0; 220 break; 221 case SPRN_SPRG1: 222 spr_val = vcpu->arch.shared->sprg1; 223 break; 224 case SPRN_SPRG2: 225 spr_val = vcpu->arch.shared->sprg2; 226 break; 227 case SPRN_SPRG3: 228 spr_val = vcpu->arch.shared->sprg3; 229 break; 230 /* Note: SPRG4-7 are user-readable, so we don't get 231 * a trap. */ 232 233 case SPRN_DEC: 234 spr_val = kvmppc_get_dec(vcpu, get_tb()); 235 break; 236 default: 237 emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, 238 &spr_val); 239 if (unlikely(emulated == EMULATE_FAIL)) { 240 printk(KERN_INFO "mfspr: unknown spr " 241 "0x%x\n", sprn); 242 } 243 break; 244 } 245 246 if (emulated == EMULATE_DONE) 247 kvmppc_set_gpr(vcpu, rt, spr_val); 248 kvmppc_set_exit_type(vcpu, EMULATED_MFSPR_EXITS); 249 250 return emulated; 251 } 252 253 /* XXX to do: 254 * lhax 255 * lhaux 256 * lswx 257 * lswi 258 * stswx 259 * stswi 260 * lha 261 * lhau 262 * lmw 263 * stmw 264 * 265 * XXX is_bigendian should depend on MMU mapping or MSR[LE] 266 */ 267 /* XXX Should probably auto-generate instruction decoding for a particular core 268 * from opcode tables in the future. */ 269 int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) 270 { 271 u32 inst = kvmppc_get_last_inst(vcpu); 272 int ra = get_ra(inst); 273 int rs = get_rs(inst); 274 int rt = get_rt(inst); 275 int sprn = get_sprn(inst); 276 enum emulation_result emulated = EMULATE_DONE; 277 int advance = 1; 278 279 /* this default type might be overwritten by subcategories */ 280 kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS); 281 282 pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); 283 284 switch (get_op(inst)) { 285 case OP_TRAP: 286 #ifdef CONFIG_PPC_BOOK3S 287 case OP_TRAP_64: 288 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 289 #else 290 kvmppc_core_queue_program(vcpu, 291 vcpu->arch.shared->esr | ESR_PTR); 292 #endif 293 advance = 0; 294 break; 295 296 case 31: 297 switch (get_xop(inst)) { 298 299 case OP_31_XOP_TRAP: 300 #ifdef CONFIG_64BIT 301 case OP_31_XOP_TRAP_64: 302 #endif 303 #ifdef CONFIG_PPC_BOOK3S 304 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 305 #else 306 kvmppc_core_queue_program(vcpu, 307 vcpu->arch.shared->esr | ESR_PTR); 308 #endif 309 advance = 0; 310 break; 311 case OP_31_XOP_LWZX: 312 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 313 break; 314 315 case OP_31_XOP_LBZX: 316 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 317 break; 318 319 case OP_31_XOP_LBZUX: 320 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 321 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 322 break; 323 324 case OP_31_XOP_STWX: 325 emulated = kvmppc_handle_store(run, vcpu, 326 kvmppc_get_gpr(vcpu, rs), 327 4, 1); 328 break; 329 330 case OP_31_XOP_STBX: 331 emulated = kvmppc_handle_store(run, vcpu, 332 kvmppc_get_gpr(vcpu, rs), 333 1, 1); 334 break; 335 336 case OP_31_XOP_STBUX: 337 emulated = kvmppc_handle_store(run, vcpu, 338 kvmppc_get_gpr(vcpu, rs), 339 1, 1); 340 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 341 break; 342 343 case OP_31_XOP_LHAX: 344 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 345 break; 346 347 case OP_31_XOP_LHZX: 348 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 349 break; 350 351 case OP_31_XOP_LHZUX: 352 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 353 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 354 break; 355 356 case OP_31_XOP_MFSPR: 357 emulated = kvmppc_emulate_mfspr(vcpu, sprn, rt); 358 break; 359 360 case OP_31_XOP_STHX: 361 emulated = kvmppc_handle_store(run, vcpu, 362 kvmppc_get_gpr(vcpu, rs), 363 2, 1); 364 break; 365 366 case OP_31_XOP_STHUX: 367 emulated = kvmppc_handle_store(run, vcpu, 368 kvmppc_get_gpr(vcpu, rs), 369 2, 1); 370 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 371 break; 372 373 case OP_31_XOP_MTSPR: 374 emulated = kvmppc_emulate_mtspr(vcpu, sprn, rs); 375 break; 376 377 case OP_31_XOP_DCBST: 378 case OP_31_XOP_DCBF: 379 case OP_31_XOP_DCBI: 380 /* Do nothing. The guest is performing dcbi because 381 * hardware DMA is not snooped by the dcache, but 382 * emulated DMA either goes through the dcache as 383 * normal writes, or the host kernel has handled dcache 384 * coherence. */ 385 break; 386 387 case OP_31_XOP_LWBRX: 388 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0); 389 break; 390 391 case OP_31_XOP_TLBSYNC: 392 break; 393 394 case OP_31_XOP_STWBRX: 395 emulated = kvmppc_handle_store(run, vcpu, 396 kvmppc_get_gpr(vcpu, rs), 397 4, 0); 398 break; 399 400 case OP_31_XOP_LHBRX: 401 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0); 402 break; 403 404 case OP_31_XOP_STHBRX: 405 emulated = kvmppc_handle_store(run, vcpu, 406 kvmppc_get_gpr(vcpu, rs), 407 2, 0); 408 break; 409 410 default: 411 /* Attempt core-specific emulation below. */ 412 emulated = EMULATE_FAIL; 413 } 414 break; 415 416 case OP_LWZ: 417 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 418 break; 419 420 /* TBD: Add support for other 64 bit load variants like ldu, ldux, ldx etc. */ 421 case OP_LD: 422 rt = get_rt(inst); 423 emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1); 424 break; 425 426 case OP_LWZU: 427 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 428 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 429 break; 430 431 case OP_LBZ: 432 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 433 break; 434 435 case OP_LBZU: 436 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 437 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 438 break; 439 440 case OP_STW: 441 emulated = kvmppc_handle_store(run, vcpu, 442 kvmppc_get_gpr(vcpu, rs), 443 4, 1); 444 break; 445 446 /* TBD: Add support for other 64 bit store variants like stdu, stdux, stdx etc. */ 447 case OP_STD: 448 rs = get_rs(inst); 449 emulated = kvmppc_handle_store(run, vcpu, 450 kvmppc_get_gpr(vcpu, rs), 451 8, 1); 452 break; 453 454 case OP_STWU: 455 emulated = kvmppc_handle_store(run, vcpu, 456 kvmppc_get_gpr(vcpu, rs), 457 4, 1); 458 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 459 break; 460 461 case OP_STB: 462 emulated = kvmppc_handle_store(run, vcpu, 463 kvmppc_get_gpr(vcpu, rs), 464 1, 1); 465 break; 466 467 case OP_STBU: 468 emulated = kvmppc_handle_store(run, vcpu, 469 kvmppc_get_gpr(vcpu, rs), 470 1, 1); 471 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 472 break; 473 474 case OP_LHZ: 475 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 476 break; 477 478 case OP_LHZU: 479 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 480 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 481 break; 482 483 case OP_LHA: 484 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 485 break; 486 487 case OP_LHAU: 488 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 489 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 490 break; 491 492 case OP_STH: 493 emulated = kvmppc_handle_store(run, vcpu, 494 kvmppc_get_gpr(vcpu, rs), 495 2, 1); 496 break; 497 498 case OP_STHU: 499 emulated = kvmppc_handle_store(run, vcpu, 500 kvmppc_get_gpr(vcpu, rs), 501 2, 1); 502 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 503 break; 504 505 default: 506 emulated = EMULATE_FAIL; 507 } 508 509 if (emulated == EMULATE_FAIL) { 510 emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance); 511 if (emulated == EMULATE_AGAIN) { 512 advance = 0; 513 } else if (emulated == EMULATE_FAIL) { 514 advance = 0; 515 printk(KERN_ERR "Couldn't emulate instruction 0x%08x " 516 "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); 517 kvmppc_core_queue_program(vcpu, 0); 518 } 519 } 520 521 trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); 522 523 /* Advance past emulated instruction. */ 524 if (advance) 525 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); 526 527 return emulated; 528 } 529