1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Author: Yu Liu, yu.liu@freescale.com 6 * Scott Wood, scottwood@freescale.com 7 * Ashish Kalra, ashish.kalra@freescale.com 8 * Varun Sethi, varun.sethi@freescale.com 9 * Alexander Graf, agraf@suse.de 10 * 11 * Description: 12 * This file is based on arch/powerpc/kvm/44x_tlb.c, 13 * by Hollis Blanchard <hollisb@us.ibm.com>. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/kvm.h> 21 #include <linux/kvm_host.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/uaccess.h> 25 #include <linux/sched/mm.h> 26 #include <linux/rwsem.h> 27 #include <linux/vmalloc.h> 28 #include <linux/hugetlb.h> 29 #include <asm/kvm_ppc.h> 30 #include <asm/pte-walk.h> 31 32 #include "e500.h" 33 #include "timing.h" 34 #include "e500_mmu_host.h" 35 36 #include "trace_booke.h" 37 38 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1) 39 40 static struct kvmppc_e500_tlb_params host_tlb_params[E500_TLB_NUM]; 41 42 static inline unsigned int tlb1_max_shadow_size(void) 43 { 44 /* reserve one entry for magic page */ 45 return host_tlb_params[1].entries - tlbcam_index - 1; 46 } 47 48 static inline u32 e500_shadow_mas3_attrib(u32 mas3, bool writable, int usermode) 49 { 50 /* Mask off reserved bits. */ 51 mas3 &= MAS3_ATTRIB_MASK; 52 53 if (!writable) 54 mas3 &= ~(MAS3_UW|MAS3_SW); 55 56 #ifndef CONFIG_KVM_BOOKE_HV 57 if (!usermode) { 58 /* Guest is in supervisor mode, 59 * so we need to translate guest 60 * supervisor permissions into user permissions. */ 61 mas3 &= ~E500_TLB_USER_PERM_MASK; 62 mas3 |= (mas3 & E500_TLB_SUPER_PERM_MASK) << 1; 63 } 64 mas3 |= E500_TLB_SUPER_PERM_MASK; 65 #endif 66 return mas3; 67 } 68 69 /* 70 * writing shadow tlb entry to host TLB 71 */ 72 static inline void __write_host_tlbe(struct kvm_book3e_206_tlb_entry *stlbe, 73 uint32_t mas0, 74 uint32_t lpid) 75 { 76 unsigned long flags; 77 78 local_irq_save(flags); 79 mtspr(SPRN_MAS0, mas0); 80 mtspr(SPRN_MAS1, stlbe->mas1); 81 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); 82 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); 83 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); 84 #ifdef CONFIG_KVM_BOOKE_HV 85 mtspr(SPRN_MAS8, MAS8_TGS | get_thread_specific_lpid(lpid)); 86 #endif 87 asm volatile("isync; tlbwe" : : : "memory"); 88 89 #ifdef CONFIG_KVM_BOOKE_HV 90 /* Must clear mas8 for other host tlbwe's */ 91 mtspr(SPRN_MAS8, 0); 92 isync(); 93 #endif 94 local_irq_restore(flags); 95 96 trace_kvm_booke206_stlb_write(mas0, stlbe->mas8, stlbe->mas1, 97 stlbe->mas2, stlbe->mas7_3); 98 } 99 100 /* 101 * Acquire a mas0 with victim hint, as if we just took a TLB miss. 102 * 103 * We don't care about the address we're searching for, other than that it's 104 * in the right set and is not present in the TLB. Using a zero PID and a 105 * userspace address means we don't have to set and then restore MAS5, or 106 * calculate a proper MAS6 value. 107 */ 108 static u32 get_host_mas0(unsigned long eaddr) 109 { 110 unsigned long flags; 111 u32 mas0; 112 u32 mas4; 113 114 local_irq_save(flags); 115 mtspr(SPRN_MAS6, 0); 116 mas4 = mfspr(SPRN_MAS4); 117 mtspr(SPRN_MAS4, mas4 & ~MAS4_TLBSEL_MASK); 118 asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET)); 119 mas0 = mfspr(SPRN_MAS0); 120 mtspr(SPRN_MAS4, mas4); 121 local_irq_restore(flags); 122 123 return mas0; 124 } 125 126 /* sesel is for tlb1 only */ 127 static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500, 128 int tlbsel, int sesel, struct kvm_book3e_206_tlb_entry *stlbe) 129 { 130 u32 mas0; 131 132 if (tlbsel == 0) { 133 mas0 = get_host_mas0(stlbe->mas2); 134 __write_host_tlbe(stlbe, mas0, vcpu_e500->vcpu.kvm->arch.lpid); 135 } else { 136 __write_host_tlbe(stlbe, 137 MAS0_TLBSEL(1) | 138 MAS0_ESEL(to_htlb1_esel(sesel)), 139 vcpu_e500->vcpu.kvm->arch.lpid); 140 } 141 } 142 143 /* sesel is for tlb1 only */ 144 static void write_stlbe(struct kvmppc_vcpu_e500 *vcpu_e500, 145 struct kvm_book3e_206_tlb_entry *gtlbe, 146 struct kvm_book3e_206_tlb_entry *stlbe, 147 int stlbsel, int sesel) 148 { 149 int stid; 150 151 preempt_disable(); 152 stid = kvmppc_e500_get_tlb_stid(&vcpu_e500->vcpu, gtlbe); 153 154 stlbe->mas1 |= MAS1_TID(stid); 155 write_host_tlbe(vcpu_e500, stlbsel, sesel, stlbe); 156 preempt_enable(); 157 } 158 159 #ifdef CONFIG_KVM_E500V2 160 /* XXX should be a hook in the gva2hpa translation */ 161 void kvmppc_map_magic(struct kvm_vcpu *vcpu) 162 { 163 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); 164 struct kvm_book3e_206_tlb_entry magic; 165 ulong shared_page = ((ulong)vcpu->arch.shared) & PAGE_MASK; 166 unsigned int stid; 167 kvm_pfn_t pfn; 168 169 pfn = (kvm_pfn_t)virt_to_phys((void *)shared_page) >> PAGE_SHIFT; 170 get_page(pfn_to_page(pfn)); 171 172 preempt_disable(); 173 stid = kvmppc_e500_get_sid(vcpu_e500, 0, 0, 0, 0); 174 175 magic.mas1 = MAS1_VALID | MAS1_TS | MAS1_TID(stid) | 176 MAS1_TSIZE(BOOK3E_PAGESZ_4K); 177 magic.mas2 = vcpu->arch.magic_page_ea | MAS2_M; 178 magic.mas7_3 = ((u64)pfn << PAGE_SHIFT) | 179 MAS3_SW | MAS3_SR | MAS3_UW | MAS3_UR; 180 magic.mas8 = 0; 181 182 __write_host_tlbe(&magic, MAS0_TLBSEL(1) | MAS0_ESEL(tlbcam_index), 0); 183 preempt_enable(); 184 } 185 #endif 186 187 void inval_gtlbe_on_host(struct kvmppc_vcpu_e500 *vcpu_e500, int tlbsel, 188 int esel) 189 { 190 struct kvm_book3e_206_tlb_entry *gtlbe = 191 get_entry(vcpu_e500, tlbsel, esel); 192 struct tlbe_priv *tlbe = &vcpu_e500->gtlb_priv[tlbsel][esel]; 193 194 /* Don't bother with unmapped entries */ 195 if (!(tlbe->flags & E500_TLB_VALID)) { 196 WARN(tlbe->flags & (E500_TLB_BITMAP | E500_TLB_TLB0), 197 "%s: flags %x\n", __func__, tlbe->flags); 198 WARN_ON(tlbsel == 1 && vcpu_e500->g2h_tlb1_map[esel]); 199 } 200 201 if (tlbsel == 1 && tlbe->flags & E500_TLB_BITMAP) { 202 u64 tmp = vcpu_e500->g2h_tlb1_map[esel]; 203 int hw_tlb_indx; 204 unsigned long flags; 205 206 local_irq_save(flags); 207 while (tmp) { 208 hw_tlb_indx = __ilog2_u64(tmp & -tmp); 209 mtspr(SPRN_MAS0, 210 MAS0_TLBSEL(1) | 211 MAS0_ESEL(to_htlb1_esel(hw_tlb_indx))); 212 mtspr(SPRN_MAS1, 0); 213 asm volatile("tlbwe"); 214 vcpu_e500->h2g_tlb1_rmap[hw_tlb_indx] = 0; 215 tmp &= tmp - 1; 216 } 217 mb(); 218 vcpu_e500->g2h_tlb1_map[esel] = 0; 219 tlbe->flags &= ~(E500_TLB_BITMAP | E500_TLB_VALID); 220 local_irq_restore(flags); 221 } 222 223 if (tlbsel == 1 && tlbe->flags & E500_TLB_TLB0) { 224 /* 225 * TLB1 entry is backed by 4k pages. This should happen 226 * rarely and is not worth optimizing. Invalidate everything. 227 */ 228 kvmppc_e500_tlbil_all(vcpu_e500); 229 tlbe->flags &= ~(E500_TLB_TLB0 | E500_TLB_VALID); 230 } 231 232 /* 233 * If TLB entry is still valid then it's a TLB0 entry, and thus 234 * backed by at most one host tlbe per shadow pid 235 */ 236 if (tlbe->flags & E500_TLB_VALID) 237 kvmppc_e500_tlbil_one(vcpu_e500, gtlbe); 238 239 /* Mark the TLB as not backed by the host anymore */ 240 tlbe->flags = 0; 241 } 242 243 static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe) 244 { 245 return tlbe->mas7_3 & (MAS3_SW|MAS3_UW); 246 } 247 248 static inline void kvmppc_e500_tlbe_setup(struct tlbe_priv *tlbe, 249 struct kvm_book3e_206_tlb_entry *gtlbe, 250 kvm_pfn_t pfn, unsigned int wimg, 251 bool writable) 252 { 253 tlbe->pfn = pfn; 254 tlbe->flags = E500_TLB_VALID; 255 if (writable) 256 tlbe->flags |= E500_TLB_WRITABLE; 257 258 /* Use guest supplied MAS2_G and MAS2_E */ 259 tlbe->flags |= (gtlbe->mas2 & MAS2_ATTRIB_MASK) | wimg; 260 } 261 262 static inline void kvmppc_e500_tlbe_release(struct tlbe_priv *tlbe) 263 { 264 if (tlbe->flags & E500_TLB_VALID) { 265 /* FIXME: don't log bogus pfn for TLB1 */ 266 trace_kvm_booke206_ref_release(tlbe->pfn, tlbe->flags); 267 tlbe->flags = 0; 268 } 269 } 270 271 static void clear_tlb1_bitmap(struct kvmppc_vcpu_e500 *vcpu_e500) 272 { 273 if (vcpu_e500->g2h_tlb1_map) 274 memset(vcpu_e500->g2h_tlb1_map, 0, 275 sizeof(u64) * vcpu_e500->gtlb_params[1].entries); 276 if (vcpu_e500->h2g_tlb1_rmap) 277 memset(vcpu_e500->h2g_tlb1_rmap, 0, 278 sizeof(unsigned int) * host_tlb_params[1].entries); 279 } 280 281 static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500) 282 { 283 int tlbsel; 284 int i; 285 286 for (tlbsel = 0; tlbsel <= 1; tlbsel++) { 287 for (i = 0; i < vcpu_e500->gtlb_params[tlbsel].entries; i++) 288 kvmppc_e500_tlbe_release(&vcpu_e500->gtlb_priv[tlbsel][i]); 289 } 290 } 291 292 void kvmppc_core_flush_tlb(struct kvm_vcpu *vcpu) 293 { 294 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); 295 kvmppc_e500_tlbil_all(vcpu_e500); 296 clear_tlb_privs(vcpu_e500); 297 clear_tlb1_bitmap(vcpu_e500); 298 } 299 300 /* TID must be supplied by the caller */ 301 static void kvmppc_e500_setup_stlbe( 302 struct kvm_vcpu *vcpu, 303 struct kvm_book3e_206_tlb_entry *gtlbe, 304 int tsize, struct tlbe_priv *tlbe, u64 gvaddr, 305 struct kvm_book3e_206_tlb_entry *stlbe) 306 { 307 kvm_pfn_t pfn = tlbe->pfn; 308 u32 pr = vcpu->arch.shared->msr & MSR_PR; 309 bool writable = !!(tlbe->flags & E500_TLB_WRITABLE); 310 311 BUG_ON(!(tlbe->flags & E500_TLB_VALID)); 312 313 /* Force IPROT=0 for all guest mappings. */ 314 stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID; 315 stlbe->mas2 = (gvaddr & MAS2_EPN) | (tlbe->flags & E500_TLB_MAS2_ATTR); 316 stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) | 317 e500_shadow_mas3_attrib(gtlbe->mas7_3, writable, pr); 318 } 319 320 static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500, 321 u64 gvaddr, gfn_t gfn, struct kvm_book3e_206_tlb_entry *gtlbe, 322 int tlbsel, struct kvm_book3e_206_tlb_entry *stlbe, 323 struct tlbe_priv *tlbe) 324 { 325 struct kvm_memory_slot *slot; 326 unsigned int psize; 327 unsigned long pfn; 328 struct page *page = NULL; 329 unsigned long hva; 330 int tsize = BOOK3E_PAGESZ_4K; 331 int ret = 0; 332 unsigned long mmu_seq; 333 struct kvm *kvm = vcpu_e500->vcpu.kvm; 334 pte_t *ptep; 335 unsigned int wimg = 0; 336 pgd_t *pgdir; 337 unsigned long flags; 338 bool writable = false; 339 340 /* used to check for invalidations in progress */ 341 mmu_seq = kvm->mmu_invalidate_seq; 342 smp_rmb(); 343 344 /* 345 * Translate guest physical to true physical, acquiring 346 * a page reference if it is normal, non-reserved memory. 347 * 348 * gfn_to_memslot() must succeed because otherwise we wouldn't 349 * have gotten this far. Eventually we should just pass the slot 350 * pointer through from the first lookup. 351 */ 352 slot = gfn_to_memslot(vcpu_e500->vcpu.kvm, gfn); 353 hva = gfn_to_hva_memslot(slot, gfn); 354 355 pfn = __kvm_faultin_pfn(slot, gfn, FOLL_WRITE, &writable, &page); 356 if (is_error_noslot_pfn(pfn)) { 357 if (printk_ratelimit()) 358 pr_err("%s: real page not found for gfn %lx\n", 359 __func__, (long)gfn); 360 return -EINVAL; 361 } 362 363 spin_lock(&kvm->mmu_lock); 364 if (mmu_invalidate_retry(kvm, mmu_seq)) { 365 ret = -EAGAIN; 366 goto out; 367 } 368 369 370 pgdir = vcpu_e500->vcpu.arch.pgdir; 371 /* 372 * We are just looking at the wimg bits, so we don't 373 * care much about the trans splitting bit. 374 * We are holding kvm->mmu_lock so a notifier invalidate 375 * can't run hence pfn won't change. 376 */ 377 local_irq_save(flags); 378 ptep = find_linux_pte(pgdir, hva, NULL, &psize); 379 if (ptep) { 380 pte_t pte = READ_ONCE(*ptep); 381 382 if (pte_present(pte)) { 383 wimg = (pte_val(pte) >> PTE_WIMGE_SHIFT) & 384 MAS2_WIMGE_MASK; 385 } else { 386 local_irq_restore(flags); 387 pr_err_ratelimited("%s: pte not present: gfn %lx,pfn %lx\n", 388 __func__, (long)gfn, pfn); 389 ret = -EINVAL; 390 goto out; 391 } 392 } 393 local_irq_restore(flags); 394 395 if (psize && tlbsel == 1) { 396 unsigned long psize_pages, tsize_pages; 397 unsigned long start, end; 398 unsigned long slot_start, slot_end; 399 400 psize_pages = 1UL << (psize - PAGE_SHIFT); 401 start = pfn & ~(psize_pages - 1); 402 end = start + psize_pages; 403 404 slot_start = pfn - (gfn - slot->base_gfn); 405 slot_end = slot_start + slot->npages; 406 407 if (start < slot_start) 408 start = slot_start; 409 if (end > slot_end) 410 end = slot_end; 411 412 tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >> 413 MAS1_TSIZE_SHIFT; 414 415 /* 416 * Any page size that doesn't satisfy the host mapping 417 * will fail the start and end tests. 418 */ 419 tsize = min(psize - PAGE_SHIFT + BOOK3E_PAGESZ_4K, tsize); 420 421 /* 422 * e500 doesn't implement the lowest tsize bit, 423 * or 1K pages. 424 */ 425 tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1); 426 427 /* 428 * Now find the largest tsize (up to what the guest 429 * requested) that will cover gfn, stay within the 430 * range, and for which gfn and pfn are mutually 431 * aligned. 432 */ 433 434 for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) { 435 unsigned long gfn_start, gfn_end; 436 tsize_pages = 1UL << (tsize - 2); 437 438 gfn_start = gfn & ~(tsize_pages - 1); 439 gfn_end = gfn_start + tsize_pages; 440 441 if (gfn_start + pfn - gfn < start) 442 continue; 443 if (gfn_end + pfn - gfn > end) 444 continue; 445 if ((gfn & (tsize_pages - 1)) != 446 (pfn & (tsize_pages - 1))) 447 continue; 448 449 gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1); 450 pfn &= ~(tsize_pages - 1); 451 break; 452 } 453 } 454 455 kvmppc_e500_tlbe_setup(tlbe, gtlbe, pfn, wimg, writable); 456 kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize, 457 tlbe, gvaddr, stlbe); 458 writable = tlbe_is_writable(stlbe); 459 460 /* Clear i-cache for new pages */ 461 kvmppc_mmu_flush_icache(pfn); 462 463 out: 464 kvm_release_faultin_page(kvm, page, !!ret, writable); 465 spin_unlock(&kvm->mmu_lock); 466 return ret; 467 } 468 469 /* XXX only map the one-one case, for now use TLB0 */ 470 static int kvmppc_e500_tlb0_map(struct kvmppc_vcpu_e500 *vcpu_e500, int esel, 471 struct kvm_book3e_206_tlb_entry *stlbe) 472 { 473 struct kvm_book3e_206_tlb_entry *gtlbe; 474 struct tlbe_priv *tlbe; 475 int stlbsel = 0; 476 int sesel = 0; 477 int r; 478 479 gtlbe = get_entry(vcpu_e500, 0, esel); 480 tlbe = &vcpu_e500->gtlb_priv[0][esel]; 481 482 r = kvmppc_e500_shadow_map(vcpu_e500, get_tlb_eaddr(gtlbe), 483 get_tlb_raddr(gtlbe) >> PAGE_SHIFT, 484 gtlbe, 0, stlbe, tlbe); 485 if (r) 486 return r; 487 488 write_stlbe(vcpu_e500, gtlbe, stlbe, stlbsel, sesel); 489 490 return 0; 491 } 492 493 static int kvmppc_e500_tlb1_map_tlb1(struct kvmppc_vcpu_e500 *vcpu_e500, 494 struct tlbe_priv *tlbe, 495 int esel) 496 { 497 unsigned int sesel = vcpu_e500->host_tlb1_nv++; 498 499 if (unlikely(vcpu_e500->host_tlb1_nv >= tlb1_max_shadow_size())) 500 vcpu_e500->host_tlb1_nv = 0; 501 502 if (vcpu_e500->h2g_tlb1_rmap[sesel]) { 503 unsigned int idx = vcpu_e500->h2g_tlb1_rmap[sesel] - 1; 504 vcpu_e500->g2h_tlb1_map[idx] &= ~(1ULL << sesel); 505 } 506 507 vcpu_e500->gtlb_priv[1][esel].flags |= E500_TLB_BITMAP; 508 vcpu_e500->g2h_tlb1_map[esel] |= (u64)1 << sesel; 509 vcpu_e500->h2g_tlb1_rmap[sesel] = esel + 1; 510 WARN_ON(!(tlbe->flags & E500_TLB_VALID)); 511 512 return sesel; 513 } 514 515 /* Caller must ensure that the specified guest TLB entry is safe to insert into 516 * the shadow TLB. */ 517 /* For both one-one and one-to-many */ 518 static int kvmppc_e500_tlb1_map(struct kvmppc_vcpu_e500 *vcpu_e500, 519 u64 gvaddr, gfn_t gfn, struct kvm_book3e_206_tlb_entry *gtlbe, 520 struct kvm_book3e_206_tlb_entry *stlbe, int esel) 521 { 522 struct tlbe_priv *tlbe = &vcpu_e500->gtlb_priv[1][esel]; 523 int sesel; 524 int r; 525 526 r = kvmppc_e500_shadow_map(vcpu_e500, gvaddr, gfn, gtlbe, 1, stlbe, 527 tlbe); 528 if (r) 529 return r; 530 531 /* Use TLB0 when we can only map a page with 4k */ 532 if (get_tlb_tsize(stlbe) == BOOK3E_PAGESZ_4K) { 533 vcpu_e500->gtlb_priv[1][esel].flags |= E500_TLB_TLB0; 534 write_stlbe(vcpu_e500, gtlbe, stlbe, 0, 0); 535 return 0; 536 } 537 538 /* Otherwise map into TLB1 */ 539 sesel = kvmppc_e500_tlb1_map_tlb1(vcpu_e500, tlbe, esel); 540 write_stlbe(vcpu_e500, gtlbe, stlbe, 1, sesel); 541 542 return 0; 543 } 544 545 void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 eaddr, gpa_t gpaddr, 546 unsigned int index) 547 { 548 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); 549 struct tlbe_priv *priv; 550 struct kvm_book3e_206_tlb_entry *gtlbe, stlbe; 551 int tlbsel = tlbsel_of(index); 552 int esel = esel_of(index); 553 554 gtlbe = get_entry(vcpu_e500, tlbsel, esel); 555 556 switch (tlbsel) { 557 case 0: 558 priv = &vcpu_e500->gtlb_priv[tlbsel][esel]; 559 560 /* Triggers after clear_tlb_privs or on initial mapping */ 561 if (!(priv->flags & E500_TLB_VALID)) { 562 kvmppc_e500_tlb0_map(vcpu_e500, esel, &stlbe); 563 } else { 564 kvmppc_e500_setup_stlbe(vcpu, gtlbe, BOOK3E_PAGESZ_4K, 565 priv, eaddr, &stlbe); 566 write_stlbe(vcpu_e500, gtlbe, &stlbe, 0, 0); 567 } 568 break; 569 570 case 1: { 571 gfn_t gfn = gpaddr >> PAGE_SHIFT; 572 kvmppc_e500_tlb1_map(vcpu_e500, eaddr, gfn, gtlbe, &stlbe, 573 esel); 574 break; 575 } 576 577 default: 578 BUG(); 579 break; 580 } 581 } 582 583 #ifdef CONFIG_KVM_BOOKE_HV 584 int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, 585 enum instruction_fetch_type type, unsigned long *instr) 586 { 587 gva_t geaddr; 588 hpa_t addr; 589 hfn_t pfn; 590 hva_t eaddr; 591 u32 mas1, mas2, mas3; 592 u64 mas7_mas3; 593 struct page *page; 594 unsigned int addr_space, psize_shift; 595 bool pr; 596 unsigned long flags; 597 598 /* Search TLB for guest pc to get the real address */ 599 geaddr = kvmppc_get_pc(vcpu); 600 601 addr_space = (vcpu->arch.shared->msr & MSR_IS) >> MSR_IR_LG; 602 603 local_irq_save(flags); 604 mtspr(SPRN_MAS6, (vcpu->arch.pid << MAS6_SPID_SHIFT) | addr_space); 605 mtspr(SPRN_MAS5, MAS5_SGS | get_lpid(vcpu)); 606 asm volatile("tlbsx 0, %[geaddr]\n" : : 607 [geaddr] "r" (geaddr)); 608 mtspr(SPRN_MAS5, 0); 609 mtspr(SPRN_MAS8, 0); 610 mas1 = mfspr(SPRN_MAS1); 611 mas2 = mfspr(SPRN_MAS2); 612 mas3 = mfspr(SPRN_MAS3); 613 #ifdef CONFIG_64BIT 614 mas7_mas3 = mfspr(SPRN_MAS7_MAS3); 615 #else 616 mas7_mas3 = ((u64)mfspr(SPRN_MAS7) << 32) | mas3; 617 #endif 618 local_irq_restore(flags); 619 620 /* 621 * If the TLB entry for guest pc was evicted, return to the guest. 622 * There are high chances to find a valid TLB entry next time. 623 */ 624 if (!(mas1 & MAS1_VALID)) 625 return EMULATE_AGAIN; 626 627 /* 628 * Another thread may rewrite the TLB entry in parallel, don't 629 * execute from the address if the execute permission is not set 630 */ 631 pr = vcpu->arch.shared->msr & MSR_PR; 632 if (unlikely((pr && !(mas3 & MAS3_UX)) || 633 (!pr && !(mas3 & MAS3_SX)))) { 634 pr_err_ratelimited( 635 "%s: Instruction emulation from guest address %08lx without execute permission\n", 636 __func__, geaddr); 637 return EMULATE_AGAIN; 638 } 639 640 /* 641 * The real address will be mapped by a cacheable, memory coherent, 642 * write-back page. Check for mismatches when LRAT is used. 643 */ 644 if (has_feature(vcpu, VCPU_FTR_MMU_V2) && 645 unlikely((mas2 & MAS2_I) || (mas2 & MAS2_W) || !(mas2 & MAS2_M))) { 646 pr_err_ratelimited( 647 "%s: Instruction emulation from guest address %08lx mismatches storage attributes\n", 648 __func__, geaddr); 649 return EMULATE_AGAIN; 650 } 651 652 /* Get pfn */ 653 psize_shift = MAS1_GET_TSIZE(mas1) + 10; 654 addr = (mas7_mas3 & (~0ULL << psize_shift)) | 655 (geaddr & ((1ULL << psize_shift) - 1ULL)); 656 pfn = addr >> PAGE_SHIFT; 657 658 /* Guard against emulation from devices area */ 659 if (unlikely(!page_is_ram(pfn))) { 660 pr_err_ratelimited("%s: Instruction emulation from non-RAM host address %08llx is not supported\n", 661 __func__, addr); 662 return EMULATE_AGAIN; 663 } 664 665 /* Map a page and get guest's instruction */ 666 page = pfn_to_page(pfn); 667 eaddr = (unsigned long)kmap_atomic(page); 668 *instr = *(u32 *)(eaddr | (unsigned long)(addr & ~PAGE_MASK)); 669 kunmap_atomic((u32 *)eaddr); 670 671 return EMULATE_DONE; 672 } 673 #else 674 int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, 675 enum instruction_fetch_type type, unsigned long *instr) 676 { 677 return EMULATE_AGAIN; 678 } 679 #endif 680 681 /************* MMU Notifiers *************/ 682 683 static bool kvm_e500_mmu_unmap_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 684 { 685 /* 686 * Flush all shadow tlb entries everywhere. This is slow, but 687 * we are 100% sure that we catch the to be unmapped page 688 */ 689 return true; 690 } 691 692 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) 693 { 694 return kvm_e500_mmu_unmap_gfn(kvm, range); 695 } 696 697 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 698 { 699 /* XXX could be more clever ;) */ 700 return false; 701 } 702 703 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 704 { 705 /* XXX could be more clever ;) */ 706 return false; 707 } 708 709 /*****************************************/ 710 711 int e500_mmu_host_init(struct kvmppc_vcpu_e500 *vcpu_e500) 712 { 713 host_tlb_params[0].entries = mfspr(SPRN_TLB0CFG) & TLBnCFG_N_ENTRY; 714 host_tlb_params[1].entries = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY; 715 716 /* 717 * This should never happen on real e500 hardware, but is 718 * architecturally possible -- e.g. in some weird nested 719 * virtualization case. 720 */ 721 if (host_tlb_params[0].entries == 0 || 722 host_tlb_params[1].entries == 0) { 723 pr_err("%s: need to know host tlb size\n", __func__); 724 return -ENODEV; 725 } 726 727 host_tlb_params[0].ways = (mfspr(SPRN_TLB0CFG) & TLBnCFG_ASSOC) >> 728 TLBnCFG_ASSOC_SHIFT; 729 host_tlb_params[1].ways = host_tlb_params[1].entries; 730 731 if (!is_power_of_2(host_tlb_params[0].entries) || 732 !is_power_of_2(host_tlb_params[0].ways) || 733 host_tlb_params[0].entries < host_tlb_params[0].ways || 734 host_tlb_params[0].ways == 0) { 735 pr_err("%s: bad tlb0 host config: %u entries %u ways\n", 736 __func__, host_tlb_params[0].entries, 737 host_tlb_params[0].ways); 738 return -ENODEV; 739 } 740 741 host_tlb_params[0].sets = 742 host_tlb_params[0].entries / host_tlb_params[0].ways; 743 host_tlb_params[1].sets = 1; 744 vcpu_e500->h2g_tlb1_rmap = kcalloc(host_tlb_params[1].entries, 745 sizeof(*vcpu_e500->h2g_tlb1_rmap), 746 GFP_KERNEL); 747 if (!vcpu_e500->h2g_tlb1_rmap) 748 return -EINVAL; 749 750 return 0; 751 } 752 753 void e500_mmu_host_uninit(struct kvmppc_vcpu_e500 *vcpu_e500) 754 { 755 kfree(vcpu_e500->h2g_tlb1_rmap); 756 } 757