1 /* 2 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: Yu Liu, yu.liu@freescale.com 5 * Scott Wood, scottwood@freescale.com 6 * Ashish Kalra, ashish.kalra@freescale.com 7 * Varun Sethi, varun.sethi@freescale.com 8 * Alexander Graf, agraf@suse.de 9 * 10 * Description: 11 * This file is based on arch/powerpc/kvm/44x_tlb.c, 12 * by Hollis Blanchard <hollisb@us.ibm.com>. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License, version 2, as 16 * published by the Free Software Foundation. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/types.h> 21 #include <linux/slab.h> 22 #include <linux/string.h> 23 #include <linux/kvm.h> 24 #include <linux/kvm_host.h> 25 #include <linux/highmem.h> 26 #include <linux/log2.h> 27 #include <linux/uaccess.h> 28 #include <linux/sched.h> 29 #include <linux/rwsem.h> 30 #include <linux/vmalloc.h> 31 #include <linux/hugetlb.h> 32 #include <asm/kvm_ppc.h> 33 34 #include "e500.h" 35 #include "timing.h" 36 #include "e500_mmu_host.h" 37 38 #include "trace_booke.h" 39 40 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1) 41 42 static struct kvmppc_e500_tlb_params host_tlb_params[E500_TLB_NUM]; 43 44 static inline unsigned int tlb1_max_shadow_size(void) 45 { 46 /* reserve one entry for magic page */ 47 return host_tlb_params[1].entries - tlbcam_index - 1; 48 } 49 50 static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode) 51 { 52 /* Mask off reserved bits. */ 53 mas3 &= MAS3_ATTRIB_MASK; 54 55 #ifndef CONFIG_KVM_BOOKE_HV 56 if (!usermode) { 57 /* Guest is in supervisor mode, 58 * so we need to translate guest 59 * supervisor permissions into user permissions. */ 60 mas3 &= ~E500_TLB_USER_PERM_MASK; 61 mas3 |= (mas3 & E500_TLB_SUPER_PERM_MASK) << 1; 62 } 63 mas3 |= E500_TLB_SUPER_PERM_MASK; 64 #endif 65 return mas3; 66 } 67 68 /* 69 * writing shadow tlb entry to host TLB 70 */ 71 static inline void __write_host_tlbe(struct kvm_book3e_206_tlb_entry *stlbe, 72 uint32_t mas0) 73 { 74 unsigned long flags; 75 76 local_irq_save(flags); 77 mtspr(SPRN_MAS0, mas0); 78 mtspr(SPRN_MAS1, stlbe->mas1); 79 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); 80 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); 81 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); 82 #ifdef CONFIG_KVM_BOOKE_HV 83 mtspr(SPRN_MAS8, stlbe->mas8); 84 #endif 85 asm volatile("isync; tlbwe" : : : "memory"); 86 87 #ifdef CONFIG_KVM_BOOKE_HV 88 /* Must clear mas8 for other host tlbwe's */ 89 mtspr(SPRN_MAS8, 0); 90 isync(); 91 #endif 92 local_irq_restore(flags); 93 94 trace_kvm_booke206_stlb_write(mas0, stlbe->mas8, stlbe->mas1, 95 stlbe->mas2, stlbe->mas7_3); 96 } 97 98 /* 99 * Acquire a mas0 with victim hint, as if we just took a TLB miss. 100 * 101 * We don't care about the address we're searching for, other than that it's 102 * in the right set and is not present in the TLB. Using a zero PID and a 103 * userspace address means we don't have to set and then restore MAS5, or 104 * calculate a proper MAS6 value. 105 */ 106 static u32 get_host_mas0(unsigned long eaddr) 107 { 108 unsigned long flags; 109 u32 mas0; 110 u32 mas4; 111 112 local_irq_save(flags); 113 mtspr(SPRN_MAS6, 0); 114 mas4 = mfspr(SPRN_MAS4); 115 mtspr(SPRN_MAS4, mas4 & ~MAS4_TLBSEL_MASK); 116 asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET)); 117 mas0 = mfspr(SPRN_MAS0); 118 mtspr(SPRN_MAS4, mas4); 119 local_irq_restore(flags); 120 121 return mas0; 122 } 123 124 /* sesel is for tlb1 only */ 125 static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500, 126 int tlbsel, int sesel, struct kvm_book3e_206_tlb_entry *stlbe) 127 { 128 u32 mas0; 129 130 if (tlbsel == 0) { 131 mas0 = get_host_mas0(stlbe->mas2); 132 __write_host_tlbe(stlbe, mas0); 133 } else { 134 __write_host_tlbe(stlbe, 135 MAS0_TLBSEL(1) | 136 MAS0_ESEL(to_htlb1_esel(sesel))); 137 } 138 } 139 140 /* sesel is for tlb1 only */ 141 static void write_stlbe(struct kvmppc_vcpu_e500 *vcpu_e500, 142 struct kvm_book3e_206_tlb_entry *gtlbe, 143 struct kvm_book3e_206_tlb_entry *stlbe, 144 int stlbsel, int sesel) 145 { 146 int stid; 147 148 preempt_disable(); 149 stid = kvmppc_e500_get_tlb_stid(&vcpu_e500->vcpu, gtlbe); 150 151 stlbe->mas1 |= MAS1_TID(stid); 152 write_host_tlbe(vcpu_e500, stlbsel, sesel, stlbe); 153 preempt_enable(); 154 } 155 156 #ifdef CONFIG_KVM_E500V2 157 /* XXX should be a hook in the gva2hpa translation */ 158 void kvmppc_map_magic(struct kvm_vcpu *vcpu) 159 { 160 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); 161 struct kvm_book3e_206_tlb_entry magic; 162 ulong shared_page = ((ulong)vcpu->arch.shared) & PAGE_MASK; 163 unsigned int stid; 164 pfn_t pfn; 165 166 pfn = (pfn_t)virt_to_phys((void *)shared_page) >> PAGE_SHIFT; 167 get_page(pfn_to_page(pfn)); 168 169 preempt_disable(); 170 stid = kvmppc_e500_get_sid(vcpu_e500, 0, 0, 0, 0); 171 172 magic.mas1 = MAS1_VALID | MAS1_TS | MAS1_TID(stid) | 173 MAS1_TSIZE(BOOK3E_PAGESZ_4K); 174 magic.mas2 = vcpu->arch.magic_page_ea | MAS2_M; 175 magic.mas7_3 = ((u64)pfn << PAGE_SHIFT) | 176 MAS3_SW | MAS3_SR | MAS3_UW | MAS3_UR; 177 magic.mas8 = 0; 178 179 __write_host_tlbe(&magic, MAS0_TLBSEL(1) | MAS0_ESEL(tlbcam_index)); 180 preempt_enable(); 181 } 182 #endif 183 184 void inval_gtlbe_on_host(struct kvmppc_vcpu_e500 *vcpu_e500, int tlbsel, 185 int esel) 186 { 187 struct kvm_book3e_206_tlb_entry *gtlbe = 188 get_entry(vcpu_e500, tlbsel, esel); 189 struct tlbe_ref *ref = &vcpu_e500->gtlb_priv[tlbsel][esel].ref; 190 191 /* Don't bother with unmapped entries */ 192 if (!(ref->flags & E500_TLB_VALID)) { 193 WARN(ref->flags & (E500_TLB_BITMAP | E500_TLB_TLB0), 194 "%s: flags %x\n", __func__, ref->flags); 195 WARN_ON(tlbsel == 1 && vcpu_e500->g2h_tlb1_map[esel]); 196 } 197 198 if (tlbsel == 1 && ref->flags & E500_TLB_BITMAP) { 199 u64 tmp = vcpu_e500->g2h_tlb1_map[esel]; 200 int hw_tlb_indx; 201 unsigned long flags; 202 203 local_irq_save(flags); 204 while (tmp) { 205 hw_tlb_indx = __ilog2_u64(tmp & -tmp); 206 mtspr(SPRN_MAS0, 207 MAS0_TLBSEL(1) | 208 MAS0_ESEL(to_htlb1_esel(hw_tlb_indx))); 209 mtspr(SPRN_MAS1, 0); 210 asm volatile("tlbwe"); 211 vcpu_e500->h2g_tlb1_rmap[hw_tlb_indx] = 0; 212 tmp &= tmp - 1; 213 } 214 mb(); 215 vcpu_e500->g2h_tlb1_map[esel] = 0; 216 ref->flags &= ~(E500_TLB_BITMAP | E500_TLB_VALID); 217 local_irq_restore(flags); 218 } 219 220 if (tlbsel == 1 && ref->flags & E500_TLB_TLB0) { 221 /* 222 * TLB1 entry is backed by 4k pages. This should happen 223 * rarely and is not worth optimizing. Invalidate everything. 224 */ 225 kvmppc_e500_tlbil_all(vcpu_e500); 226 ref->flags &= ~(E500_TLB_TLB0 | E500_TLB_VALID); 227 } 228 229 /* 230 * If TLB entry is still valid then it's a TLB0 entry, and thus 231 * backed by at most one host tlbe per shadow pid 232 */ 233 if (ref->flags & E500_TLB_VALID) 234 kvmppc_e500_tlbil_one(vcpu_e500, gtlbe); 235 236 /* Mark the TLB as not backed by the host anymore */ 237 ref->flags = 0; 238 } 239 240 static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe) 241 { 242 return tlbe->mas7_3 & (MAS3_SW|MAS3_UW); 243 } 244 245 static inline void kvmppc_e500_ref_setup(struct tlbe_ref *ref, 246 struct kvm_book3e_206_tlb_entry *gtlbe, 247 pfn_t pfn, unsigned int wimg) 248 { 249 ref->pfn = pfn; 250 ref->flags = E500_TLB_VALID; 251 252 /* Use guest supplied MAS2_G and MAS2_E */ 253 ref->flags |= (gtlbe->mas2 & MAS2_ATTRIB_MASK) | wimg; 254 255 /* Mark the page accessed */ 256 kvm_set_pfn_accessed(pfn); 257 258 if (tlbe_is_writable(gtlbe)) 259 kvm_set_pfn_dirty(pfn); 260 } 261 262 static inline void kvmppc_e500_ref_release(struct tlbe_ref *ref) 263 { 264 if (ref->flags & E500_TLB_VALID) { 265 /* FIXME: don't log bogus pfn for TLB1 */ 266 trace_kvm_booke206_ref_release(ref->pfn, ref->flags); 267 ref->flags = 0; 268 } 269 } 270 271 static void clear_tlb1_bitmap(struct kvmppc_vcpu_e500 *vcpu_e500) 272 { 273 if (vcpu_e500->g2h_tlb1_map) 274 memset(vcpu_e500->g2h_tlb1_map, 0, 275 sizeof(u64) * vcpu_e500->gtlb_params[1].entries); 276 if (vcpu_e500->h2g_tlb1_rmap) 277 memset(vcpu_e500->h2g_tlb1_rmap, 0, 278 sizeof(unsigned int) * host_tlb_params[1].entries); 279 } 280 281 static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500) 282 { 283 int tlbsel; 284 int i; 285 286 for (tlbsel = 0; tlbsel <= 1; tlbsel++) { 287 for (i = 0; i < vcpu_e500->gtlb_params[tlbsel].entries; i++) { 288 struct tlbe_ref *ref = 289 &vcpu_e500->gtlb_priv[tlbsel][i].ref; 290 kvmppc_e500_ref_release(ref); 291 } 292 } 293 } 294 295 void kvmppc_core_flush_tlb(struct kvm_vcpu *vcpu) 296 { 297 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); 298 kvmppc_e500_tlbil_all(vcpu_e500); 299 clear_tlb_privs(vcpu_e500); 300 clear_tlb1_bitmap(vcpu_e500); 301 } 302 303 /* TID must be supplied by the caller */ 304 static void kvmppc_e500_setup_stlbe( 305 struct kvm_vcpu *vcpu, 306 struct kvm_book3e_206_tlb_entry *gtlbe, 307 int tsize, struct tlbe_ref *ref, u64 gvaddr, 308 struct kvm_book3e_206_tlb_entry *stlbe) 309 { 310 pfn_t pfn = ref->pfn; 311 u32 pr = vcpu->arch.shared->msr & MSR_PR; 312 313 BUG_ON(!(ref->flags & E500_TLB_VALID)); 314 315 /* Force IPROT=0 for all guest mappings. */ 316 stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID; 317 stlbe->mas2 = (gvaddr & MAS2_EPN) | (ref->flags & E500_TLB_MAS2_ATTR); 318 stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) | 319 e500_shadow_mas3_attrib(gtlbe->mas7_3, pr); 320 321 #ifdef CONFIG_KVM_BOOKE_HV 322 stlbe->mas8 = MAS8_TGS | vcpu->kvm->arch.lpid; 323 #endif 324 } 325 326 static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500, 327 u64 gvaddr, gfn_t gfn, struct kvm_book3e_206_tlb_entry *gtlbe, 328 int tlbsel, struct kvm_book3e_206_tlb_entry *stlbe, 329 struct tlbe_ref *ref) 330 { 331 struct kvm_memory_slot *slot; 332 unsigned long pfn = 0; /* silence GCC warning */ 333 unsigned long hva; 334 int pfnmap = 0; 335 int tsize = BOOK3E_PAGESZ_4K; 336 int ret = 0; 337 unsigned long mmu_seq; 338 struct kvm *kvm = vcpu_e500->vcpu.kvm; 339 unsigned long tsize_pages = 0; 340 pte_t *ptep; 341 unsigned int wimg = 0; 342 pgd_t *pgdir; 343 344 /* used to check for invalidations in progress */ 345 mmu_seq = kvm->mmu_notifier_seq; 346 smp_rmb(); 347 348 /* 349 * Translate guest physical to true physical, acquiring 350 * a page reference if it is normal, non-reserved memory. 351 * 352 * gfn_to_memslot() must succeed because otherwise we wouldn't 353 * have gotten this far. Eventually we should just pass the slot 354 * pointer through from the first lookup. 355 */ 356 slot = gfn_to_memslot(vcpu_e500->vcpu.kvm, gfn); 357 hva = gfn_to_hva_memslot(slot, gfn); 358 359 if (tlbsel == 1) { 360 struct vm_area_struct *vma; 361 down_read(¤t->mm->mmap_sem); 362 363 vma = find_vma(current->mm, hva); 364 if (vma && hva >= vma->vm_start && 365 (vma->vm_flags & VM_PFNMAP)) { 366 /* 367 * This VMA is a physically contiguous region (e.g. 368 * /dev/mem) that bypasses normal Linux page 369 * management. Find the overlap between the 370 * vma and the memslot. 371 */ 372 373 unsigned long start, end; 374 unsigned long slot_start, slot_end; 375 376 pfnmap = 1; 377 378 start = vma->vm_pgoff; 379 end = start + 380 ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT); 381 382 pfn = start + ((hva - vma->vm_start) >> PAGE_SHIFT); 383 384 slot_start = pfn - (gfn - slot->base_gfn); 385 slot_end = slot_start + slot->npages; 386 387 if (start < slot_start) 388 start = slot_start; 389 if (end > slot_end) 390 end = slot_end; 391 392 tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >> 393 MAS1_TSIZE_SHIFT; 394 395 /* 396 * e500 doesn't implement the lowest tsize bit, 397 * or 1K pages. 398 */ 399 tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1); 400 401 /* 402 * Now find the largest tsize (up to what the guest 403 * requested) that will cover gfn, stay within the 404 * range, and for which gfn and pfn are mutually 405 * aligned. 406 */ 407 408 for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) { 409 unsigned long gfn_start, gfn_end; 410 tsize_pages = 1 << (tsize - 2); 411 412 gfn_start = gfn & ~(tsize_pages - 1); 413 gfn_end = gfn_start + tsize_pages; 414 415 if (gfn_start + pfn - gfn < start) 416 continue; 417 if (gfn_end + pfn - gfn > end) 418 continue; 419 if ((gfn & (tsize_pages - 1)) != 420 (pfn & (tsize_pages - 1))) 421 continue; 422 423 gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1); 424 pfn &= ~(tsize_pages - 1); 425 break; 426 } 427 } else if (vma && hva >= vma->vm_start && 428 (vma->vm_flags & VM_HUGETLB)) { 429 unsigned long psize = vma_kernel_pagesize(vma); 430 431 tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >> 432 MAS1_TSIZE_SHIFT; 433 434 /* 435 * Take the largest page size that satisfies both host 436 * and guest mapping 437 */ 438 tsize = min(__ilog2(psize) - 10, tsize); 439 440 /* 441 * e500 doesn't implement the lowest tsize bit, 442 * or 1K pages. 443 */ 444 tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1); 445 } 446 447 up_read(¤t->mm->mmap_sem); 448 } 449 450 if (likely(!pfnmap)) { 451 tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT); 452 pfn = gfn_to_pfn_memslot(slot, gfn); 453 if (is_error_noslot_pfn(pfn)) { 454 if (printk_ratelimit()) 455 pr_err("%s: real page not found for gfn %lx\n", 456 __func__, (long)gfn); 457 return -EINVAL; 458 } 459 460 /* Align guest and physical address to page map boundaries */ 461 pfn &= ~(tsize_pages - 1); 462 gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1); 463 } 464 465 spin_lock(&kvm->mmu_lock); 466 if (mmu_notifier_retry(kvm, mmu_seq)) { 467 ret = -EAGAIN; 468 goto out; 469 } 470 471 472 pgdir = vcpu_e500->vcpu.arch.pgdir; 473 ptep = lookup_linux_ptep(pgdir, hva, &tsize_pages); 474 if (pte_present(*ptep)) 475 wimg = (*ptep >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK; 476 else { 477 if (printk_ratelimit()) 478 pr_err("%s: pte not present: gfn %lx, pfn %lx\n", 479 __func__, (long)gfn, pfn); 480 ret = -EINVAL; 481 goto out; 482 } 483 kvmppc_e500_ref_setup(ref, gtlbe, pfn, wimg); 484 485 kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize, 486 ref, gvaddr, stlbe); 487 488 /* Clear i-cache for new pages */ 489 kvmppc_mmu_flush_icache(pfn); 490 491 out: 492 spin_unlock(&kvm->mmu_lock); 493 494 /* Drop refcount on page, so that mmu notifiers can clear it */ 495 kvm_release_pfn_clean(pfn); 496 497 return ret; 498 } 499 500 /* XXX only map the one-one case, for now use TLB0 */ 501 static int kvmppc_e500_tlb0_map(struct kvmppc_vcpu_e500 *vcpu_e500, int esel, 502 struct kvm_book3e_206_tlb_entry *stlbe) 503 { 504 struct kvm_book3e_206_tlb_entry *gtlbe; 505 struct tlbe_ref *ref; 506 int stlbsel = 0; 507 int sesel = 0; 508 int r; 509 510 gtlbe = get_entry(vcpu_e500, 0, esel); 511 ref = &vcpu_e500->gtlb_priv[0][esel].ref; 512 513 r = kvmppc_e500_shadow_map(vcpu_e500, get_tlb_eaddr(gtlbe), 514 get_tlb_raddr(gtlbe) >> PAGE_SHIFT, 515 gtlbe, 0, stlbe, ref); 516 if (r) 517 return r; 518 519 write_stlbe(vcpu_e500, gtlbe, stlbe, stlbsel, sesel); 520 521 return 0; 522 } 523 524 static int kvmppc_e500_tlb1_map_tlb1(struct kvmppc_vcpu_e500 *vcpu_e500, 525 struct tlbe_ref *ref, 526 int esel) 527 { 528 unsigned int sesel = vcpu_e500->host_tlb1_nv++; 529 530 if (unlikely(vcpu_e500->host_tlb1_nv >= tlb1_max_shadow_size())) 531 vcpu_e500->host_tlb1_nv = 0; 532 533 if (vcpu_e500->h2g_tlb1_rmap[sesel]) { 534 unsigned int idx = vcpu_e500->h2g_tlb1_rmap[sesel] - 1; 535 vcpu_e500->g2h_tlb1_map[idx] &= ~(1ULL << sesel); 536 } 537 538 vcpu_e500->gtlb_priv[1][esel].ref.flags |= E500_TLB_BITMAP; 539 vcpu_e500->g2h_tlb1_map[esel] |= (u64)1 << sesel; 540 vcpu_e500->h2g_tlb1_rmap[sesel] = esel + 1; 541 WARN_ON(!(ref->flags & E500_TLB_VALID)); 542 543 return sesel; 544 } 545 546 /* Caller must ensure that the specified guest TLB entry is safe to insert into 547 * the shadow TLB. */ 548 /* For both one-one and one-to-many */ 549 static int kvmppc_e500_tlb1_map(struct kvmppc_vcpu_e500 *vcpu_e500, 550 u64 gvaddr, gfn_t gfn, struct kvm_book3e_206_tlb_entry *gtlbe, 551 struct kvm_book3e_206_tlb_entry *stlbe, int esel) 552 { 553 struct tlbe_ref *ref = &vcpu_e500->gtlb_priv[1][esel].ref; 554 int sesel; 555 int r; 556 557 r = kvmppc_e500_shadow_map(vcpu_e500, gvaddr, gfn, gtlbe, 1, stlbe, 558 ref); 559 if (r) 560 return r; 561 562 /* Use TLB0 when we can only map a page with 4k */ 563 if (get_tlb_tsize(stlbe) == BOOK3E_PAGESZ_4K) { 564 vcpu_e500->gtlb_priv[1][esel].ref.flags |= E500_TLB_TLB0; 565 write_stlbe(vcpu_e500, gtlbe, stlbe, 0, 0); 566 return 0; 567 } 568 569 /* Otherwise map into TLB1 */ 570 sesel = kvmppc_e500_tlb1_map_tlb1(vcpu_e500, ref, esel); 571 write_stlbe(vcpu_e500, gtlbe, stlbe, 1, sesel); 572 573 return 0; 574 } 575 576 void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 eaddr, gpa_t gpaddr, 577 unsigned int index) 578 { 579 struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); 580 struct tlbe_priv *priv; 581 struct kvm_book3e_206_tlb_entry *gtlbe, stlbe; 582 int tlbsel = tlbsel_of(index); 583 int esel = esel_of(index); 584 585 gtlbe = get_entry(vcpu_e500, tlbsel, esel); 586 587 switch (tlbsel) { 588 case 0: 589 priv = &vcpu_e500->gtlb_priv[tlbsel][esel]; 590 591 /* Triggers after clear_tlb_privs or on initial mapping */ 592 if (!(priv->ref.flags & E500_TLB_VALID)) { 593 kvmppc_e500_tlb0_map(vcpu_e500, esel, &stlbe); 594 } else { 595 kvmppc_e500_setup_stlbe(vcpu, gtlbe, BOOK3E_PAGESZ_4K, 596 &priv->ref, eaddr, &stlbe); 597 write_stlbe(vcpu_e500, gtlbe, &stlbe, 0, 0); 598 } 599 break; 600 601 case 1: { 602 gfn_t gfn = gpaddr >> PAGE_SHIFT; 603 kvmppc_e500_tlb1_map(vcpu_e500, eaddr, gfn, gtlbe, &stlbe, 604 esel); 605 break; 606 } 607 608 default: 609 BUG(); 610 break; 611 } 612 } 613 614 #ifdef CONFIG_KVM_BOOKE_HV 615 int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, enum instruction_type type, 616 u32 *instr) 617 { 618 gva_t geaddr; 619 hpa_t addr; 620 hfn_t pfn; 621 hva_t eaddr; 622 u32 mas1, mas2, mas3; 623 u64 mas7_mas3; 624 struct page *page; 625 unsigned int addr_space, psize_shift; 626 bool pr; 627 unsigned long flags; 628 629 /* Search TLB for guest pc to get the real address */ 630 geaddr = kvmppc_get_pc(vcpu); 631 632 addr_space = (vcpu->arch.shared->msr & MSR_IS) >> MSR_IR_LG; 633 634 local_irq_save(flags); 635 mtspr(SPRN_MAS6, (vcpu->arch.pid << MAS6_SPID_SHIFT) | addr_space); 636 mtspr(SPRN_MAS5, MAS5_SGS | vcpu->kvm->arch.lpid); 637 asm volatile("tlbsx 0, %[geaddr]\n" : : 638 [geaddr] "r" (geaddr)); 639 mtspr(SPRN_MAS5, 0); 640 mtspr(SPRN_MAS8, 0); 641 mas1 = mfspr(SPRN_MAS1); 642 mas2 = mfspr(SPRN_MAS2); 643 mas3 = mfspr(SPRN_MAS3); 644 #ifdef CONFIG_64BIT 645 mas7_mas3 = mfspr(SPRN_MAS7_MAS3); 646 #else 647 mas7_mas3 = ((u64)mfspr(SPRN_MAS7) << 32) | mas3; 648 #endif 649 local_irq_restore(flags); 650 651 /* 652 * If the TLB entry for guest pc was evicted, return to the guest. 653 * There are high chances to find a valid TLB entry next time. 654 */ 655 if (!(mas1 & MAS1_VALID)) 656 return EMULATE_AGAIN; 657 658 /* 659 * Another thread may rewrite the TLB entry in parallel, don't 660 * execute from the address if the execute permission is not set 661 */ 662 pr = vcpu->arch.shared->msr & MSR_PR; 663 if (unlikely((pr && !(mas3 & MAS3_UX)) || 664 (!pr && !(mas3 & MAS3_SX)))) { 665 pr_err_ratelimited( 666 "%s: Instuction emulation from guest addres %08lx without execute permission\n", 667 __func__, geaddr); 668 return EMULATE_AGAIN; 669 } 670 671 /* 672 * The real address will be mapped by a cacheable, memory coherent, 673 * write-back page. Check for mismatches when LRAT is used. 674 */ 675 if (has_feature(vcpu, VCPU_FTR_MMU_V2) && 676 unlikely((mas2 & MAS2_I) || (mas2 & MAS2_W) || !(mas2 & MAS2_M))) { 677 pr_err_ratelimited( 678 "%s: Instuction emulation from guest addres %08lx mismatches storage attributes\n", 679 __func__, geaddr); 680 return EMULATE_AGAIN; 681 } 682 683 /* Get pfn */ 684 psize_shift = MAS1_GET_TSIZE(mas1) + 10; 685 addr = (mas7_mas3 & (~0ULL << psize_shift)) | 686 (geaddr & ((1ULL << psize_shift) - 1ULL)); 687 pfn = addr >> PAGE_SHIFT; 688 689 /* Guard against emulation from devices area */ 690 if (unlikely(!page_is_ram(pfn))) { 691 pr_err_ratelimited("%s: Instruction emulation from non-RAM host addres %08llx is not supported\n", 692 __func__, addr); 693 return EMULATE_AGAIN; 694 } 695 696 /* Map a page and get guest's instruction */ 697 page = pfn_to_page(pfn); 698 eaddr = (unsigned long)kmap_atomic(page); 699 *instr = *(u32 *)(eaddr | (unsigned long)(addr & ~PAGE_MASK)); 700 kunmap_atomic((u32 *)eaddr); 701 702 return EMULATE_DONE; 703 } 704 #else 705 int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, enum instruction_type type, 706 u32 *instr) 707 { 708 return EMULATE_AGAIN; 709 } 710 #endif 711 712 /************* MMU Notifiers *************/ 713 714 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) 715 { 716 trace_kvm_unmap_hva(hva); 717 718 /* 719 * Flush all shadow tlb entries everywhere. This is slow, but 720 * we are 100% sure that we catch the to be unmapped page 721 */ 722 kvm_flush_remote_tlbs(kvm); 723 724 return 0; 725 } 726 727 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) 728 { 729 /* kvm_unmap_hva flushes everything anyways */ 730 kvm_unmap_hva(kvm, start); 731 732 return 0; 733 } 734 735 int kvm_age_hva(struct kvm *kvm, unsigned long hva) 736 { 737 /* XXX could be more clever ;) */ 738 return 0; 739 } 740 741 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) 742 { 743 /* XXX could be more clever ;) */ 744 return 0; 745 } 746 747 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) 748 { 749 /* The page will get remapped properly on its next fault */ 750 kvm_unmap_hva(kvm, hva); 751 } 752 753 /*****************************************/ 754 755 int e500_mmu_host_init(struct kvmppc_vcpu_e500 *vcpu_e500) 756 { 757 host_tlb_params[0].entries = mfspr(SPRN_TLB0CFG) & TLBnCFG_N_ENTRY; 758 host_tlb_params[1].entries = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY; 759 760 /* 761 * This should never happen on real e500 hardware, but is 762 * architecturally possible -- e.g. in some weird nested 763 * virtualization case. 764 */ 765 if (host_tlb_params[0].entries == 0 || 766 host_tlb_params[1].entries == 0) { 767 pr_err("%s: need to know host tlb size\n", __func__); 768 return -ENODEV; 769 } 770 771 host_tlb_params[0].ways = (mfspr(SPRN_TLB0CFG) & TLBnCFG_ASSOC) >> 772 TLBnCFG_ASSOC_SHIFT; 773 host_tlb_params[1].ways = host_tlb_params[1].entries; 774 775 if (!is_power_of_2(host_tlb_params[0].entries) || 776 !is_power_of_2(host_tlb_params[0].ways) || 777 host_tlb_params[0].entries < host_tlb_params[0].ways || 778 host_tlb_params[0].ways == 0) { 779 pr_err("%s: bad tlb0 host config: %u entries %u ways\n", 780 __func__, host_tlb_params[0].entries, 781 host_tlb_params[0].ways); 782 return -ENODEV; 783 } 784 785 host_tlb_params[0].sets = 786 host_tlb_params[0].entries / host_tlb_params[0].ways; 787 host_tlb_params[1].sets = 1; 788 789 vcpu_e500->h2g_tlb1_rmap = kzalloc(sizeof(unsigned int) * 790 host_tlb_params[1].entries, 791 GFP_KERNEL); 792 if (!vcpu_e500->h2g_tlb1_rmap) 793 return -EINVAL; 794 795 return 0; 796 } 797 798 void e500_mmu_host_uninit(struct kvmppc_vcpu_e500 *vcpu_e500) 799 { 800 kfree(vcpu_e500->h2g_tlb1_rmap); 801 } 802