1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright SUSE Linux Products GmbH 2009 16 * 17 * Authors: Alexander Graf <agraf@suse.de> 18 */ 19 20#include <asm/ppc_asm.h> 21#include <asm/kvm_asm.h> 22#include <asm/reg.h> 23#include <asm/mmu.h> 24#include <asm/page.h> 25#include <asm/asm-offsets.h> 26 27#ifdef CONFIG_PPC_BOOK3S_64 28#include <asm/exception-64s.h> 29#endif 30 31/***************************************************************************** 32 * * 33 * Real Mode handlers that need to be in low physical memory * 34 * * 35 ****************************************************************************/ 36 37#if defined(CONFIG_PPC_BOOK3S_64) 38 39#define FUNC(name) GLUE(.,name) 40 41 .globl kvmppc_skip_interrupt 42kvmppc_skip_interrupt: 43 /* 44 * Here all GPRs are unchanged from when the interrupt happened 45 * except for r13, which is saved in SPRG_SCRATCH0. 46 */ 47 mfspr r13, SPRN_SRR0 48 addi r13, r13, 4 49 mtspr SPRN_SRR0, r13 50 GET_SCRATCH0(r13) 51 rfid 52 b . 53 54 .globl kvmppc_skip_Hinterrupt 55kvmppc_skip_Hinterrupt: 56 /* 57 * Here all GPRs are unchanged from when the interrupt happened 58 * except for r13, which is saved in SPRG_SCRATCH0. 59 */ 60 mfspr r13, SPRN_HSRR0 61 addi r13, r13, 4 62 mtspr SPRN_HSRR0, r13 63 GET_SCRATCH0(r13) 64 hrfid 65 b . 66 67#elif defined(CONFIG_PPC_BOOK3S_32) 68 69#define FUNC(name) name 70 71.macro INTERRUPT_TRAMPOLINE intno 72 73.global kvmppc_trampoline_\intno 74kvmppc_trampoline_\intno: 75 76 mtspr SPRN_SPRG_SCRATCH0, r13 /* Save r13 */ 77 78 /* 79 * First thing to do is to find out if we're coming 80 * from a KVM guest or a Linux process. 81 * 82 * To distinguish, we check a magic byte in the PACA/current 83 */ 84 mfspr r13, SPRN_SPRG_THREAD 85 lwz r13, THREAD_KVM_SVCPU(r13) 86 /* PPC32 can have a NULL pointer - let's check for that */ 87 mtspr SPRN_SPRG_SCRATCH1, r12 /* Save r12 */ 88 mfcr r12 89 cmpwi r13, 0 90 bne 1f 912: mtcr r12 92 mfspr r12, SPRN_SPRG_SCRATCH1 93 mfspr r13, SPRN_SPRG_SCRATCH0 /* r13 = original r13 */ 94 b kvmppc_resume_\intno /* Get back original handler */ 95 961: tophys(r13, r13) 97 stw r12, HSTATE_SCRATCH1(r13) 98 mfspr r12, SPRN_SPRG_SCRATCH1 99 stw r12, HSTATE_SCRATCH0(r13) 100 lbz r12, HSTATE_IN_GUEST(r13) 101 cmpwi r12, KVM_GUEST_MODE_NONE 102 bne ..kvmppc_handler_hasmagic_\intno 103 /* No KVM guest? Then jump back to the Linux handler! */ 104 lwz r12, HSTATE_SCRATCH1(r13) 105 b 2b 106 107 /* Now we know we're handling a KVM guest */ 108..kvmppc_handler_hasmagic_\intno: 109 110 /* Should we just skip the faulting instruction? */ 111 cmpwi r12, KVM_GUEST_MODE_SKIP 112 beq kvmppc_handler_skip_ins 113 114 /* Let's store which interrupt we're handling */ 115 li r12, \intno 116 117 /* Jump into the SLB exit code that goes to the highmem handler */ 118 b kvmppc_handler_trampoline_exit 119 120.endm 121 122INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSTEM_RESET 123INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_MACHINE_CHECK 124INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_STORAGE 125INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_STORAGE 126INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_EXTERNAL 127INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALIGNMENT 128INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PROGRAM 129INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_FP_UNAVAIL 130INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DECREMENTER 131INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSCALL 132INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_TRACE 133INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PERFMON 134INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALTIVEC 135 136/* 137 * Bring us back to the faulting code, but skip the 138 * faulting instruction. 139 * 140 * This is a generic exit path from the interrupt 141 * trampolines above. 142 * 143 * Input Registers: 144 * 145 * R12 = free 146 * R13 = Shadow VCPU (PACA) 147 * HSTATE.SCRATCH0 = guest R12 148 * HSTATE.SCRATCH1 = guest CR 149 * SPRG_SCRATCH0 = guest R13 150 * 151 */ 152kvmppc_handler_skip_ins: 153 154 /* Patch the IP to the next instruction */ 155 mfsrr0 r12 156 addi r12, r12, 4 157 mtsrr0 r12 158 159 /* Clean up all state */ 160 lwz r12, HSTATE_SCRATCH1(r13) 161 mtcr r12 162 PPC_LL r12, HSTATE_SCRATCH0(r13) 163 GET_SCRATCH0(r13) 164 165 /* And get back into the code */ 166 RFI 167#endif 168 169/* 170 * Call kvmppc_handler_trampoline_enter in real mode 171 * 172 * On entry, r4 contains the guest shadow MSR 173 */ 174_GLOBAL(kvmppc_entry_trampoline) 175 mfmsr r5 176 LOAD_REG_ADDR(r7, kvmppc_handler_trampoline_enter) 177 toreal(r7) 178 179 li r9, MSR_RI 180 ori r9, r9, MSR_EE 181 andc r9, r5, r9 /* Clear EE and RI in MSR value */ 182 li r6, MSR_IR | MSR_DR 183 ori r6, r6, MSR_EE 184 andc r6, r5, r6 /* Clear EE, DR and IR in MSR value */ 185 MTMSR_EERI(r9) /* Clear EE and RI in MSR */ 186 mtsrr0 r7 /* before we set srr0/1 */ 187 mtsrr1 r6 188 RFI 189 190#if defined(CONFIG_PPC_BOOK3S_32) 191#define STACK_LR INT_FRAME_SIZE+4 192 193/* load_up_xxx have to run with MSR_DR=0 on Book3S_32 */ 194#define MSR_EXT_START \ 195 PPC_STL r20, _NIP(r1); \ 196 mfmsr r20; \ 197 LOAD_REG_IMMEDIATE(r3, MSR_DR|MSR_EE); \ 198 andc r3,r20,r3; /* Disable DR,EE */ \ 199 mtmsr r3; \ 200 sync 201 202#define MSR_EXT_END \ 203 mtmsr r20; /* Enable DR,EE */ \ 204 sync; \ 205 PPC_LL r20, _NIP(r1) 206 207#elif defined(CONFIG_PPC_BOOK3S_64) 208#define STACK_LR _LINK 209#define MSR_EXT_START 210#define MSR_EXT_END 211#endif 212 213/* 214 * Activate current's external feature (FPU/Altivec/VSX) 215 */ 216#define define_load_up(what) \ 217 \ 218_GLOBAL(kvmppc_load_up_ ## what); \ 219 PPC_STLU r1, -INT_FRAME_SIZE(r1); \ 220 mflr r3; \ 221 PPC_STL r3, STACK_LR(r1); \ 222 MSR_EXT_START; \ 223 \ 224 bl FUNC(load_up_ ## what); \ 225 \ 226 MSR_EXT_END; \ 227 PPC_LL r3, STACK_LR(r1); \ 228 mtlr r3; \ 229 addi r1, r1, INT_FRAME_SIZE; \ 230 blr 231 232define_load_up(fpu) 233#ifdef CONFIG_ALTIVEC 234define_load_up(altivec) 235#endif 236#ifdef CONFIG_VSX 237define_load_up(vsx) 238#endif 239 240#include "book3s_segment.S" 241