1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/string.h> 11 #include <linux/kvm.h> 12 #include <linux/kvm_host.h> 13 #include <linux/hugetlb.h> 14 #include <linux/module.h> 15 #include <linux/log2.h> 16 17 #include <asm/tlbflush.h> 18 #include <asm/kvm_ppc.h> 19 #include <asm/kvm_book3s.h> 20 #include <asm/book3s/64/mmu-hash.h> 21 #include <asm/hvcall.h> 22 #include <asm/synch.h> 23 #include <asm/ppc-opcode.h> 24 25 /* Translate address of a vmalloc'd thing to a linear map address */ 26 static void *real_vmalloc_addr(void *x) 27 { 28 unsigned long addr = (unsigned long) x; 29 pte_t *p; 30 /* 31 * assume we don't have huge pages in vmalloc space... 32 * So don't worry about THP collapse/split. Called 33 * Only in realmode, hence won't need irq_save/restore. 34 */ 35 p = __find_linux_pte_or_hugepte(swapper_pg_dir, addr, NULL, NULL); 36 if (!p || !pte_present(*p)) 37 return NULL; 38 addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK); 39 return __va(addr); 40 } 41 42 /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */ 43 static int global_invalidates(struct kvm *kvm, unsigned long flags) 44 { 45 int global; 46 int cpu; 47 48 /* 49 * If there is only one vcore, and it's currently running, 50 * as indicated by local_paca->kvm_hstate.kvm_vcpu being set, 51 * we can use tlbiel as long as we mark all other physical 52 * cores as potentially having stale TLB entries for this lpid. 53 * Otherwise, don't use tlbiel. 54 */ 55 if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcpu) 56 global = 0; 57 else 58 global = 1; 59 60 if (!global) { 61 /* any other core might now have stale TLB entries... */ 62 smp_wmb(); 63 cpumask_setall(&kvm->arch.need_tlb_flush); 64 cpu = local_paca->kvm_hstate.kvm_vcore->pcpu; 65 /* 66 * On POWER9, threads are independent but the TLB is shared, 67 * so use the bit for the first thread to represent the core. 68 */ 69 if (cpu_has_feature(CPU_FTR_ARCH_300)) 70 cpu = cpu_first_thread_sibling(cpu); 71 cpumask_clear_cpu(cpu, &kvm->arch.need_tlb_flush); 72 } 73 74 return global; 75 } 76 77 /* 78 * Add this HPTE into the chain for the real page. 79 * Must be called with the chain locked; it unlocks the chain. 80 */ 81 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev, 82 unsigned long *rmap, long pte_index, int realmode) 83 { 84 struct revmap_entry *head, *tail; 85 unsigned long i; 86 87 if (*rmap & KVMPPC_RMAP_PRESENT) { 88 i = *rmap & KVMPPC_RMAP_INDEX; 89 head = &kvm->arch.hpt.rev[i]; 90 if (realmode) 91 head = real_vmalloc_addr(head); 92 tail = &kvm->arch.hpt.rev[head->back]; 93 if (realmode) 94 tail = real_vmalloc_addr(tail); 95 rev->forw = i; 96 rev->back = head->back; 97 tail->forw = pte_index; 98 head->back = pte_index; 99 } else { 100 rev->forw = rev->back = pte_index; 101 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | 102 pte_index | KVMPPC_RMAP_PRESENT; 103 } 104 unlock_rmap(rmap); 105 } 106 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain); 107 108 /* Update the changed page order field of an rmap entry */ 109 void kvmppc_update_rmap_change(unsigned long *rmap, unsigned long psize) 110 { 111 unsigned long order; 112 113 if (!psize) 114 return; 115 order = ilog2(psize); 116 order <<= KVMPPC_RMAP_CHG_SHIFT; 117 if (order > (*rmap & KVMPPC_RMAP_CHG_ORDER)) 118 *rmap = (*rmap & ~KVMPPC_RMAP_CHG_ORDER) | order; 119 } 120 EXPORT_SYMBOL_GPL(kvmppc_update_rmap_change); 121 122 /* Returns a pointer to the revmap entry for the page mapped by a HPTE */ 123 static unsigned long *revmap_for_hpte(struct kvm *kvm, unsigned long hpte_v, 124 unsigned long hpte_gr) 125 { 126 struct kvm_memory_slot *memslot; 127 unsigned long *rmap; 128 unsigned long gfn; 129 130 gfn = hpte_rpn(hpte_gr, hpte_page_size(hpte_v, hpte_gr)); 131 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn); 132 if (!memslot) 133 return NULL; 134 135 rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]); 136 return rmap; 137 } 138 139 /* Remove this HPTE from the chain for a real page */ 140 static void remove_revmap_chain(struct kvm *kvm, long pte_index, 141 struct revmap_entry *rev, 142 unsigned long hpte_v, unsigned long hpte_r) 143 { 144 struct revmap_entry *next, *prev; 145 unsigned long ptel, head; 146 unsigned long *rmap; 147 unsigned long rcbits; 148 149 rcbits = hpte_r & (HPTE_R_R | HPTE_R_C); 150 ptel = rev->guest_rpte |= rcbits; 151 rmap = revmap_for_hpte(kvm, hpte_v, ptel); 152 if (!rmap) 153 return; 154 lock_rmap(rmap); 155 156 head = *rmap & KVMPPC_RMAP_INDEX; 157 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]); 158 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]); 159 next->back = rev->back; 160 prev->forw = rev->forw; 161 if (head == pte_index) { 162 head = rev->forw; 163 if (head == pte_index) 164 *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX); 165 else 166 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head; 167 } 168 *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT; 169 if (rcbits & HPTE_R_C) 170 kvmppc_update_rmap_change(rmap, hpte_page_size(hpte_v, hpte_r)); 171 unlock_rmap(rmap); 172 } 173 174 long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags, 175 long pte_index, unsigned long pteh, unsigned long ptel, 176 pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret) 177 { 178 unsigned long i, pa, gpa, gfn, psize; 179 unsigned long slot_fn, hva; 180 __be64 *hpte; 181 struct revmap_entry *rev; 182 unsigned long g_ptel; 183 struct kvm_memory_slot *memslot; 184 unsigned hpage_shift; 185 bool is_ci; 186 unsigned long *rmap; 187 pte_t *ptep; 188 unsigned int writing; 189 unsigned long mmu_seq; 190 unsigned long rcbits, irq_flags = 0; 191 192 if (kvm_is_radix(kvm)) 193 return H_FUNCTION; 194 psize = hpte_page_size(pteh, ptel); 195 if (!psize) 196 return H_PARAMETER; 197 writing = hpte_is_writable(ptel); 198 pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID); 199 ptel &= ~HPTE_GR_RESERVED; 200 g_ptel = ptel; 201 202 /* used later to detect if we might have been invalidated */ 203 mmu_seq = kvm->mmu_notifier_seq; 204 smp_rmb(); 205 206 /* Find the memslot (if any) for this address */ 207 gpa = (ptel & HPTE_R_RPN) & ~(psize - 1); 208 gfn = gpa >> PAGE_SHIFT; 209 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn); 210 pa = 0; 211 is_ci = false; 212 rmap = NULL; 213 if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) { 214 /* Emulated MMIO - mark this with key=31 */ 215 pteh |= HPTE_V_ABSENT; 216 ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO; 217 goto do_insert; 218 } 219 220 /* Check if the requested page fits entirely in the memslot. */ 221 if (!slot_is_aligned(memslot, psize)) 222 return H_PARAMETER; 223 slot_fn = gfn - memslot->base_gfn; 224 rmap = &memslot->arch.rmap[slot_fn]; 225 226 /* Translate to host virtual address */ 227 hva = __gfn_to_hva_memslot(memslot, gfn); 228 /* 229 * If we had a page table table change after lookup, we would 230 * retry via mmu_notifier_retry. 231 */ 232 if (realmode) 233 ptep = __find_linux_pte_or_hugepte(pgdir, hva, NULL, 234 &hpage_shift); 235 else { 236 local_irq_save(irq_flags); 237 ptep = find_linux_pte_or_hugepte(pgdir, hva, NULL, 238 &hpage_shift); 239 } 240 if (ptep) { 241 pte_t pte; 242 unsigned int host_pte_size; 243 244 if (hpage_shift) 245 host_pte_size = 1ul << hpage_shift; 246 else 247 host_pte_size = PAGE_SIZE; 248 /* 249 * We should always find the guest page size 250 * to <= host page size, if host is using hugepage 251 */ 252 if (host_pte_size < psize) { 253 if (!realmode) 254 local_irq_restore(flags); 255 return H_PARAMETER; 256 } 257 pte = kvmppc_read_update_linux_pte(ptep, writing); 258 if (pte_present(pte) && !pte_protnone(pte)) { 259 if (writing && !__pte_write(pte)) 260 /* make the actual HPTE be read-only */ 261 ptel = hpte_make_readonly(ptel); 262 is_ci = pte_ci(pte); 263 pa = pte_pfn(pte) << PAGE_SHIFT; 264 pa |= hva & (host_pte_size - 1); 265 pa |= gpa & ~PAGE_MASK; 266 } 267 } 268 if (!realmode) 269 local_irq_restore(irq_flags); 270 271 ptel &= ~(HPTE_R_PP0 - psize); 272 ptel |= pa; 273 274 if (pa) 275 pteh |= HPTE_V_VALID; 276 else { 277 pteh |= HPTE_V_ABSENT; 278 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO); 279 } 280 281 /*If we had host pte mapping then Check WIMG */ 282 if (ptep && !hpte_cache_flags_ok(ptel, is_ci)) { 283 if (is_ci) 284 return H_PARAMETER; 285 /* 286 * Allow guest to map emulated device memory as 287 * uncacheable, but actually make it cacheable. 288 */ 289 ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G); 290 ptel |= HPTE_R_M; 291 } 292 293 /* Find and lock the HPTEG slot to use */ 294 do_insert: 295 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) 296 return H_PARAMETER; 297 if (likely((flags & H_EXACT) == 0)) { 298 pte_index &= ~7UL; 299 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 300 for (i = 0; i < 8; ++i) { 301 if ((be64_to_cpu(*hpte) & HPTE_V_VALID) == 0 && 302 try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID | 303 HPTE_V_ABSENT)) 304 break; 305 hpte += 2; 306 } 307 if (i == 8) { 308 /* 309 * Since try_lock_hpte doesn't retry (not even stdcx. 310 * failures), it could be that there is a free slot 311 * but we transiently failed to lock it. Try again, 312 * actually locking each slot and checking it. 313 */ 314 hpte -= 16; 315 for (i = 0; i < 8; ++i) { 316 u64 pte; 317 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK)) 318 cpu_relax(); 319 pte = be64_to_cpu(hpte[0]); 320 if (!(pte & (HPTE_V_VALID | HPTE_V_ABSENT))) 321 break; 322 __unlock_hpte(hpte, pte); 323 hpte += 2; 324 } 325 if (i == 8) 326 return H_PTEG_FULL; 327 } 328 pte_index += i; 329 } else { 330 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 331 if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID | 332 HPTE_V_ABSENT)) { 333 /* Lock the slot and check again */ 334 u64 pte; 335 336 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK)) 337 cpu_relax(); 338 pte = be64_to_cpu(hpte[0]); 339 if (pte & (HPTE_V_VALID | HPTE_V_ABSENT)) { 340 __unlock_hpte(hpte, pte); 341 return H_PTEG_FULL; 342 } 343 } 344 } 345 346 /* Save away the guest's idea of the second HPTE dword */ 347 rev = &kvm->arch.hpt.rev[pte_index]; 348 if (realmode) 349 rev = real_vmalloc_addr(rev); 350 if (rev) { 351 rev->guest_rpte = g_ptel; 352 note_hpte_modification(kvm, rev); 353 } 354 355 /* Link HPTE into reverse-map chain */ 356 if (pteh & HPTE_V_VALID) { 357 if (realmode) 358 rmap = real_vmalloc_addr(rmap); 359 lock_rmap(rmap); 360 /* Check for pending invalidations under the rmap chain lock */ 361 if (mmu_notifier_retry(kvm, mmu_seq)) { 362 /* inval in progress, write a non-present HPTE */ 363 pteh |= HPTE_V_ABSENT; 364 pteh &= ~HPTE_V_VALID; 365 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO); 366 unlock_rmap(rmap); 367 } else { 368 kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index, 369 realmode); 370 /* Only set R/C in real HPTE if already set in *rmap */ 371 rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT; 372 ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C); 373 } 374 } 375 376 /* Convert to new format on P9 */ 377 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 378 ptel = hpte_old_to_new_r(pteh, ptel); 379 pteh = hpte_old_to_new_v(pteh); 380 } 381 hpte[1] = cpu_to_be64(ptel); 382 383 /* Write the first HPTE dword, unlocking the HPTE and making it valid */ 384 eieio(); 385 __unlock_hpte(hpte, pteh); 386 asm volatile("ptesync" : : : "memory"); 387 388 *pte_idx_ret = pte_index; 389 return H_SUCCESS; 390 } 391 EXPORT_SYMBOL_GPL(kvmppc_do_h_enter); 392 393 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags, 394 long pte_index, unsigned long pteh, unsigned long ptel) 395 { 396 return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel, 397 vcpu->arch.pgdir, true, &vcpu->arch.gpr[4]); 398 } 399 400 #ifdef __BIG_ENDIAN__ 401 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token)) 402 #else 403 #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index)) 404 #endif 405 406 static inline int is_mmio_hpte(unsigned long v, unsigned long r) 407 { 408 return ((v & HPTE_V_ABSENT) && 409 (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) == 410 (HPTE_R_KEY_HI | HPTE_R_KEY_LO)); 411 } 412 413 static inline int try_lock_tlbie(unsigned int *lock) 414 { 415 unsigned int tmp, old; 416 unsigned int token = LOCK_TOKEN; 417 418 asm volatile("1:lwarx %1,0,%2\n" 419 " cmpwi cr0,%1,0\n" 420 " bne 2f\n" 421 " stwcx. %3,0,%2\n" 422 " bne- 1b\n" 423 " isync\n" 424 "2:" 425 : "=&r" (tmp), "=&r" (old) 426 : "r" (lock), "r" (token) 427 : "cc", "memory"); 428 return old == 0; 429 } 430 431 static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues, 432 long npages, int global, bool need_sync) 433 { 434 long i; 435 436 /* 437 * We use the POWER9 5-operand versions of tlbie and tlbiel here. 438 * Since we are using RIC=0 PRS=0 R=0, and P7/P8 tlbiel ignores 439 * the RS field, this is backwards-compatible with P7 and P8. 440 */ 441 if (global) { 442 while (!try_lock_tlbie(&kvm->arch.tlbie_lock)) 443 cpu_relax(); 444 if (need_sync) 445 asm volatile("ptesync" : : : "memory"); 446 for (i = 0; i < npages; ++i) 447 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : : 448 "r" (rbvalues[i]), "r" (kvm->arch.lpid)); 449 asm volatile("eieio; tlbsync; ptesync" : : : "memory"); 450 kvm->arch.tlbie_lock = 0; 451 } else { 452 if (need_sync) 453 asm volatile("ptesync" : : : "memory"); 454 for (i = 0; i < npages; ++i) 455 asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : : 456 "r" (rbvalues[i]), "r" (0)); 457 asm volatile("ptesync" : : : "memory"); 458 } 459 } 460 461 long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags, 462 unsigned long pte_index, unsigned long avpn, 463 unsigned long *hpret) 464 { 465 __be64 *hpte; 466 unsigned long v, r, rb; 467 struct revmap_entry *rev; 468 u64 pte, orig_pte, pte_r; 469 470 if (kvm_is_radix(kvm)) 471 return H_FUNCTION; 472 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) 473 return H_PARAMETER; 474 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 475 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK)) 476 cpu_relax(); 477 pte = orig_pte = be64_to_cpu(hpte[0]); 478 pte_r = be64_to_cpu(hpte[1]); 479 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 480 pte = hpte_new_to_old_v(pte, pte_r); 481 pte_r = hpte_new_to_old_r(pte_r); 482 } 483 if ((pte & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 || 484 ((flags & H_AVPN) && (pte & ~0x7fUL) != avpn) || 485 ((flags & H_ANDCOND) && (pte & avpn) != 0)) { 486 __unlock_hpte(hpte, orig_pte); 487 return H_NOT_FOUND; 488 } 489 490 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]); 491 v = pte & ~HPTE_V_HVLOCK; 492 if (v & HPTE_V_VALID) { 493 hpte[0] &= ~cpu_to_be64(HPTE_V_VALID); 494 rb = compute_tlbie_rb(v, pte_r, pte_index); 495 do_tlbies(kvm, &rb, 1, global_invalidates(kvm, flags), true); 496 /* 497 * The reference (R) and change (C) bits in a HPT 498 * entry can be set by hardware at any time up until 499 * the HPTE is invalidated and the TLB invalidation 500 * sequence has completed. This means that when 501 * removing a HPTE, we need to re-read the HPTE after 502 * the invalidation sequence has completed in order to 503 * obtain reliable values of R and C. 504 */ 505 remove_revmap_chain(kvm, pte_index, rev, v, 506 be64_to_cpu(hpte[1])); 507 } 508 r = rev->guest_rpte & ~HPTE_GR_RESERVED; 509 note_hpte_modification(kvm, rev); 510 unlock_hpte(hpte, 0); 511 512 if (is_mmio_hpte(v, pte_r)) 513 atomic64_inc(&kvm->arch.mmio_update); 514 515 if (v & HPTE_V_ABSENT) 516 v = (v & ~HPTE_V_ABSENT) | HPTE_V_VALID; 517 hpret[0] = v; 518 hpret[1] = r; 519 return H_SUCCESS; 520 } 521 EXPORT_SYMBOL_GPL(kvmppc_do_h_remove); 522 523 long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags, 524 unsigned long pte_index, unsigned long avpn) 525 { 526 return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn, 527 &vcpu->arch.gpr[4]); 528 } 529 530 long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu) 531 { 532 struct kvm *kvm = vcpu->kvm; 533 unsigned long *args = &vcpu->arch.gpr[4]; 534 __be64 *hp, *hptes[4]; 535 unsigned long tlbrb[4]; 536 long int i, j, k, n, found, indexes[4]; 537 unsigned long flags, req, pte_index, rcbits; 538 int global; 539 long int ret = H_SUCCESS; 540 struct revmap_entry *rev, *revs[4]; 541 u64 hp0, hp1; 542 543 if (kvm_is_radix(kvm)) 544 return H_FUNCTION; 545 global = global_invalidates(kvm, 0); 546 for (i = 0; i < 4 && ret == H_SUCCESS; ) { 547 n = 0; 548 for (; i < 4; ++i) { 549 j = i * 2; 550 pte_index = args[j]; 551 flags = pte_index >> 56; 552 pte_index &= ((1ul << 56) - 1); 553 req = flags >> 6; 554 flags &= 3; 555 if (req == 3) { /* no more requests */ 556 i = 4; 557 break; 558 } 559 if (req != 1 || flags == 3 || 560 pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) { 561 /* parameter error */ 562 args[j] = ((0xa0 | flags) << 56) + pte_index; 563 ret = H_PARAMETER; 564 break; 565 } 566 hp = (__be64 *) (kvm->arch.hpt.virt + (pte_index << 4)); 567 /* to avoid deadlock, don't spin except for first */ 568 if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) { 569 if (n) 570 break; 571 while (!try_lock_hpte(hp, HPTE_V_HVLOCK)) 572 cpu_relax(); 573 } 574 found = 0; 575 hp0 = be64_to_cpu(hp[0]); 576 hp1 = be64_to_cpu(hp[1]); 577 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 578 hp0 = hpte_new_to_old_v(hp0, hp1); 579 hp1 = hpte_new_to_old_r(hp1); 580 } 581 if (hp0 & (HPTE_V_ABSENT | HPTE_V_VALID)) { 582 switch (flags & 3) { 583 case 0: /* absolute */ 584 found = 1; 585 break; 586 case 1: /* andcond */ 587 if (!(hp0 & args[j + 1])) 588 found = 1; 589 break; 590 case 2: /* AVPN */ 591 if ((hp0 & ~0x7fUL) == args[j + 1]) 592 found = 1; 593 break; 594 } 595 } 596 if (!found) { 597 hp[0] &= ~cpu_to_be64(HPTE_V_HVLOCK); 598 args[j] = ((0x90 | flags) << 56) + pte_index; 599 continue; 600 } 601 602 args[j] = ((0x80 | flags) << 56) + pte_index; 603 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]); 604 note_hpte_modification(kvm, rev); 605 606 if (!(hp0 & HPTE_V_VALID)) { 607 /* insert R and C bits from PTE */ 608 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C); 609 args[j] |= rcbits << (56 - 5); 610 hp[0] = 0; 611 if (is_mmio_hpte(hp0, hp1)) 612 atomic64_inc(&kvm->arch.mmio_update); 613 continue; 614 } 615 616 /* leave it locked */ 617 hp[0] &= ~cpu_to_be64(HPTE_V_VALID); 618 tlbrb[n] = compute_tlbie_rb(hp0, hp1, pte_index); 619 indexes[n] = j; 620 hptes[n] = hp; 621 revs[n] = rev; 622 ++n; 623 } 624 625 if (!n) 626 break; 627 628 /* Now that we've collected a batch, do the tlbies */ 629 do_tlbies(kvm, tlbrb, n, global, true); 630 631 /* Read PTE low words after tlbie to get final R/C values */ 632 for (k = 0; k < n; ++k) { 633 j = indexes[k]; 634 pte_index = args[j] & ((1ul << 56) - 1); 635 hp = hptes[k]; 636 rev = revs[k]; 637 remove_revmap_chain(kvm, pte_index, rev, 638 be64_to_cpu(hp[0]), be64_to_cpu(hp[1])); 639 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C); 640 args[j] |= rcbits << (56 - 5); 641 __unlock_hpte(hp, 0); 642 } 643 } 644 645 return ret; 646 } 647 648 long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags, 649 unsigned long pte_index, unsigned long avpn, 650 unsigned long va) 651 { 652 struct kvm *kvm = vcpu->kvm; 653 __be64 *hpte; 654 struct revmap_entry *rev; 655 unsigned long v, r, rb, mask, bits; 656 u64 pte_v, pte_r; 657 658 if (kvm_is_radix(kvm)) 659 return H_FUNCTION; 660 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) 661 return H_PARAMETER; 662 663 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 664 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK)) 665 cpu_relax(); 666 v = pte_v = be64_to_cpu(hpte[0]); 667 if (cpu_has_feature(CPU_FTR_ARCH_300)) 668 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[1])); 669 if ((v & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 || 670 ((flags & H_AVPN) && (v & ~0x7fUL) != avpn)) { 671 __unlock_hpte(hpte, pte_v); 672 return H_NOT_FOUND; 673 } 674 675 pte_r = be64_to_cpu(hpte[1]); 676 bits = (flags << 55) & HPTE_R_PP0; 677 bits |= (flags << 48) & HPTE_R_KEY_HI; 678 bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO); 679 680 /* Update guest view of 2nd HPTE dword */ 681 mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N | 682 HPTE_R_KEY_HI | HPTE_R_KEY_LO; 683 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]); 684 if (rev) { 685 r = (rev->guest_rpte & ~mask) | bits; 686 rev->guest_rpte = r; 687 note_hpte_modification(kvm, rev); 688 } 689 690 /* Update HPTE */ 691 if (v & HPTE_V_VALID) { 692 /* 693 * If the page is valid, don't let it transition from 694 * readonly to writable. If it should be writable, we'll 695 * take a trap and let the page fault code sort it out. 696 */ 697 r = (pte_r & ~mask) | bits; 698 if (hpte_is_writable(r) && !hpte_is_writable(pte_r)) 699 r = hpte_make_readonly(r); 700 /* If the PTE is changing, invalidate it first */ 701 if (r != pte_r) { 702 rb = compute_tlbie_rb(v, r, pte_index); 703 hpte[0] = cpu_to_be64((pte_v & ~HPTE_V_VALID) | 704 HPTE_V_ABSENT); 705 do_tlbies(kvm, &rb, 1, global_invalidates(kvm, flags), 706 true); 707 /* Don't lose R/C bit updates done by hardware */ 708 r |= be64_to_cpu(hpte[1]) & (HPTE_R_R | HPTE_R_C); 709 hpte[1] = cpu_to_be64(r); 710 } 711 } 712 unlock_hpte(hpte, pte_v & ~HPTE_V_HVLOCK); 713 asm volatile("ptesync" : : : "memory"); 714 if (is_mmio_hpte(v, pte_r)) 715 atomic64_inc(&kvm->arch.mmio_update); 716 717 return H_SUCCESS; 718 } 719 720 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags, 721 unsigned long pte_index) 722 { 723 struct kvm *kvm = vcpu->kvm; 724 __be64 *hpte; 725 unsigned long v, r; 726 int i, n = 1; 727 struct revmap_entry *rev = NULL; 728 729 if (kvm_is_radix(kvm)) 730 return H_FUNCTION; 731 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) 732 return H_PARAMETER; 733 if (flags & H_READ_4) { 734 pte_index &= ~3; 735 n = 4; 736 } 737 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]); 738 for (i = 0; i < n; ++i, ++pte_index) { 739 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 740 v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK; 741 r = be64_to_cpu(hpte[1]); 742 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 743 v = hpte_new_to_old_v(v, r); 744 r = hpte_new_to_old_r(r); 745 } 746 if (v & HPTE_V_ABSENT) { 747 v &= ~HPTE_V_ABSENT; 748 v |= HPTE_V_VALID; 749 } 750 if (v & HPTE_V_VALID) { 751 r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C)); 752 r &= ~HPTE_GR_RESERVED; 753 } 754 vcpu->arch.gpr[4 + i * 2] = v; 755 vcpu->arch.gpr[5 + i * 2] = r; 756 } 757 return H_SUCCESS; 758 } 759 760 long kvmppc_h_clear_ref(struct kvm_vcpu *vcpu, unsigned long flags, 761 unsigned long pte_index) 762 { 763 struct kvm *kvm = vcpu->kvm; 764 __be64 *hpte; 765 unsigned long v, r, gr; 766 struct revmap_entry *rev; 767 unsigned long *rmap; 768 long ret = H_NOT_FOUND; 769 770 if (kvm_is_radix(kvm)) 771 return H_FUNCTION; 772 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) 773 return H_PARAMETER; 774 775 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]); 776 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 777 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK)) 778 cpu_relax(); 779 v = be64_to_cpu(hpte[0]); 780 r = be64_to_cpu(hpte[1]); 781 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT))) 782 goto out; 783 784 gr = rev->guest_rpte; 785 if (rev->guest_rpte & HPTE_R_R) { 786 rev->guest_rpte &= ~HPTE_R_R; 787 note_hpte_modification(kvm, rev); 788 } 789 if (v & HPTE_V_VALID) { 790 gr |= r & (HPTE_R_R | HPTE_R_C); 791 if (r & HPTE_R_R) { 792 kvmppc_clear_ref_hpte(kvm, hpte, pte_index); 793 rmap = revmap_for_hpte(kvm, v, gr); 794 if (rmap) { 795 lock_rmap(rmap); 796 *rmap |= KVMPPC_RMAP_REFERENCED; 797 unlock_rmap(rmap); 798 } 799 } 800 } 801 vcpu->arch.gpr[4] = gr; 802 ret = H_SUCCESS; 803 out: 804 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK); 805 return ret; 806 } 807 808 long kvmppc_h_clear_mod(struct kvm_vcpu *vcpu, unsigned long flags, 809 unsigned long pte_index) 810 { 811 struct kvm *kvm = vcpu->kvm; 812 __be64 *hpte; 813 unsigned long v, r, gr; 814 struct revmap_entry *rev; 815 unsigned long *rmap; 816 long ret = H_NOT_FOUND; 817 818 if (kvm_is_radix(kvm)) 819 return H_FUNCTION; 820 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) 821 return H_PARAMETER; 822 823 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]); 824 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4)); 825 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK)) 826 cpu_relax(); 827 v = be64_to_cpu(hpte[0]); 828 r = be64_to_cpu(hpte[1]); 829 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT))) 830 goto out; 831 832 gr = rev->guest_rpte; 833 if (gr & HPTE_R_C) { 834 rev->guest_rpte &= ~HPTE_R_C; 835 note_hpte_modification(kvm, rev); 836 } 837 if (v & HPTE_V_VALID) { 838 /* need to make it temporarily absent so C is stable */ 839 hpte[0] |= cpu_to_be64(HPTE_V_ABSENT); 840 kvmppc_invalidate_hpte(kvm, hpte, pte_index); 841 r = be64_to_cpu(hpte[1]); 842 gr |= r & (HPTE_R_R | HPTE_R_C); 843 if (r & HPTE_R_C) { 844 unsigned long psize = hpte_page_size(v, r); 845 hpte[1] = cpu_to_be64(r & ~HPTE_R_C); 846 eieio(); 847 rmap = revmap_for_hpte(kvm, v, gr); 848 if (rmap) { 849 lock_rmap(rmap); 850 *rmap |= KVMPPC_RMAP_CHANGED; 851 kvmppc_update_rmap_change(rmap, psize); 852 unlock_rmap(rmap); 853 } 854 } 855 } 856 vcpu->arch.gpr[4] = gr; 857 ret = H_SUCCESS; 858 out: 859 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK); 860 return ret; 861 } 862 863 void kvmppc_invalidate_hpte(struct kvm *kvm, __be64 *hptep, 864 unsigned long pte_index) 865 { 866 unsigned long rb; 867 u64 hp0, hp1; 868 869 hptep[0] &= ~cpu_to_be64(HPTE_V_VALID); 870 hp0 = be64_to_cpu(hptep[0]); 871 hp1 = be64_to_cpu(hptep[1]); 872 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 873 hp0 = hpte_new_to_old_v(hp0, hp1); 874 hp1 = hpte_new_to_old_r(hp1); 875 } 876 rb = compute_tlbie_rb(hp0, hp1, pte_index); 877 do_tlbies(kvm, &rb, 1, 1, true); 878 } 879 EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte); 880 881 void kvmppc_clear_ref_hpte(struct kvm *kvm, __be64 *hptep, 882 unsigned long pte_index) 883 { 884 unsigned long rb; 885 unsigned char rbyte; 886 u64 hp0, hp1; 887 888 hp0 = be64_to_cpu(hptep[0]); 889 hp1 = be64_to_cpu(hptep[1]); 890 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 891 hp0 = hpte_new_to_old_v(hp0, hp1); 892 hp1 = hpte_new_to_old_r(hp1); 893 } 894 rb = compute_tlbie_rb(hp0, hp1, pte_index); 895 rbyte = (be64_to_cpu(hptep[1]) & ~HPTE_R_R) >> 8; 896 /* modify only the second-last byte, which contains the ref bit */ 897 *((char *)hptep + 14) = rbyte; 898 do_tlbies(kvm, &rb, 1, 1, false); 899 } 900 EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte); 901 902 static int slb_base_page_shift[4] = { 903 24, /* 16M */ 904 16, /* 64k */ 905 34, /* 16G */ 906 20, /* 1M, unsupported */ 907 }; 908 909 static struct mmio_hpte_cache_entry *mmio_cache_search(struct kvm_vcpu *vcpu, 910 unsigned long eaddr, unsigned long slb_v, long mmio_update) 911 { 912 struct mmio_hpte_cache_entry *entry = NULL; 913 unsigned int pshift; 914 unsigned int i; 915 916 for (i = 0; i < MMIO_HPTE_CACHE_SIZE; i++) { 917 entry = &vcpu->arch.mmio_cache.entry[i]; 918 if (entry->mmio_update == mmio_update) { 919 pshift = entry->slb_base_pshift; 920 if ((entry->eaddr >> pshift) == (eaddr >> pshift) && 921 entry->slb_v == slb_v) 922 return entry; 923 } 924 } 925 return NULL; 926 } 927 928 static struct mmio_hpte_cache_entry * 929 next_mmio_cache_entry(struct kvm_vcpu *vcpu) 930 { 931 unsigned int index = vcpu->arch.mmio_cache.index; 932 933 vcpu->arch.mmio_cache.index++; 934 if (vcpu->arch.mmio_cache.index == MMIO_HPTE_CACHE_SIZE) 935 vcpu->arch.mmio_cache.index = 0; 936 937 return &vcpu->arch.mmio_cache.entry[index]; 938 } 939 940 /* When called from virtmode, this func should be protected by 941 * preempt_disable(), otherwise, the holding of HPTE_V_HVLOCK 942 * can trigger deadlock issue. 943 */ 944 long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v, 945 unsigned long valid) 946 { 947 unsigned int i; 948 unsigned int pshift; 949 unsigned long somask; 950 unsigned long vsid, hash; 951 unsigned long avpn; 952 __be64 *hpte; 953 unsigned long mask, val; 954 unsigned long v, r, orig_v; 955 956 /* Get page shift, work out hash and AVPN etc. */ 957 mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY; 958 val = 0; 959 pshift = 12; 960 if (slb_v & SLB_VSID_L) { 961 mask |= HPTE_V_LARGE; 962 val |= HPTE_V_LARGE; 963 pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4]; 964 } 965 if (slb_v & SLB_VSID_B_1T) { 966 somask = (1UL << 40) - 1; 967 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T; 968 vsid ^= vsid << 25; 969 } else { 970 somask = (1UL << 28) - 1; 971 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT; 972 } 973 hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvmppc_hpt_mask(&kvm->arch.hpt); 974 avpn = slb_v & ~(somask >> 16); /* also includes B */ 975 avpn |= (eaddr & somask) >> 16; 976 977 if (pshift >= 24) 978 avpn &= ~((1UL << (pshift - 16)) - 1); 979 else 980 avpn &= ~0x7fUL; 981 val |= avpn; 982 983 for (;;) { 984 hpte = (__be64 *)(kvm->arch.hpt.virt + (hash << 7)); 985 986 for (i = 0; i < 16; i += 2) { 987 /* Read the PTE racily */ 988 v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK; 989 if (cpu_has_feature(CPU_FTR_ARCH_300)) 990 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[i+1])); 991 992 /* Check valid/absent, hash, segment size and AVPN */ 993 if (!(v & valid) || (v & mask) != val) 994 continue; 995 996 /* Lock the PTE and read it under the lock */ 997 while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK)) 998 cpu_relax(); 999 v = orig_v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK; 1000 r = be64_to_cpu(hpte[i+1]); 1001 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1002 v = hpte_new_to_old_v(v, r); 1003 r = hpte_new_to_old_r(r); 1004 } 1005 1006 /* 1007 * Check the HPTE again, including base page size 1008 */ 1009 if ((v & valid) && (v & mask) == val && 1010 hpte_base_page_size(v, r) == (1ul << pshift)) 1011 /* Return with the HPTE still locked */ 1012 return (hash << 3) + (i >> 1); 1013 1014 __unlock_hpte(&hpte[i], orig_v); 1015 } 1016 1017 if (val & HPTE_V_SECONDARY) 1018 break; 1019 val |= HPTE_V_SECONDARY; 1020 hash = hash ^ kvmppc_hpt_mask(&kvm->arch.hpt); 1021 } 1022 return -1; 1023 } 1024 EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte); 1025 1026 /* 1027 * Called in real mode to check whether an HPTE not found fault 1028 * is due to accessing a paged-out page or an emulated MMIO page, 1029 * or if a protection fault is due to accessing a page that the 1030 * guest wanted read/write access to but which we made read-only. 1031 * Returns a possibly modified status (DSISR) value if not 1032 * (i.e. pass the interrupt to the guest), 1033 * -1 to pass the fault up to host kernel mode code, -2 to do that 1034 * and also load the instruction word (for MMIO emulation), 1035 * or 0 if we should make the guest retry the access. 1036 */ 1037 long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr, 1038 unsigned long slb_v, unsigned int status, bool data) 1039 { 1040 struct kvm *kvm = vcpu->kvm; 1041 long int index; 1042 unsigned long v, r, gr, orig_v; 1043 __be64 *hpte; 1044 unsigned long valid; 1045 struct revmap_entry *rev; 1046 unsigned long pp, key; 1047 struct mmio_hpte_cache_entry *cache_entry = NULL; 1048 long mmio_update = 0; 1049 1050 /* For protection fault, expect to find a valid HPTE */ 1051 valid = HPTE_V_VALID; 1052 if (status & DSISR_NOHPTE) { 1053 valid |= HPTE_V_ABSENT; 1054 mmio_update = atomic64_read(&kvm->arch.mmio_update); 1055 cache_entry = mmio_cache_search(vcpu, addr, slb_v, mmio_update); 1056 } 1057 if (cache_entry) { 1058 index = cache_entry->pte_index; 1059 v = cache_entry->hpte_v; 1060 r = cache_entry->hpte_r; 1061 gr = cache_entry->rpte; 1062 } else { 1063 index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid); 1064 if (index < 0) { 1065 if (status & DSISR_NOHPTE) 1066 return status; /* there really was no HPTE */ 1067 return 0; /* for prot fault, HPTE disappeared */ 1068 } 1069 hpte = (__be64 *)(kvm->arch.hpt.virt + (index << 4)); 1070 v = orig_v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK; 1071 r = be64_to_cpu(hpte[1]); 1072 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1073 v = hpte_new_to_old_v(v, r); 1074 r = hpte_new_to_old_r(r); 1075 } 1076 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[index]); 1077 gr = rev->guest_rpte; 1078 1079 unlock_hpte(hpte, orig_v); 1080 } 1081 1082 /* For not found, if the HPTE is valid by now, retry the instruction */ 1083 if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID)) 1084 return 0; 1085 1086 /* Check access permissions to the page */ 1087 pp = gr & (HPTE_R_PP0 | HPTE_R_PP); 1088 key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS; 1089 status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */ 1090 if (!data) { 1091 if (gr & (HPTE_R_N | HPTE_R_G)) 1092 return status | SRR1_ISI_N_OR_G; 1093 if (!hpte_read_permission(pp, slb_v & key)) 1094 return status | SRR1_ISI_PROT; 1095 } else if (status & DSISR_ISSTORE) { 1096 /* check write permission */ 1097 if (!hpte_write_permission(pp, slb_v & key)) 1098 return status | DSISR_PROTFAULT; 1099 } else { 1100 if (!hpte_read_permission(pp, slb_v & key)) 1101 return status | DSISR_PROTFAULT; 1102 } 1103 1104 /* Check storage key, if applicable */ 1105 if (data && (vcpu->arch.shregs.msr & MSR_DR)) { 1106 unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr); 1107 if (status & DSISR_ISSTORE) 1108 perm >>= 1; 1109 if (perm & 1) 1110 return status | DSISR_KEYFAULT; 1111 } 1112 1113 /* Save HPTE info for virtual-mode handler */ 1114 vcpu->arch.pgfault_addr = addr; 1115 vcpu->arch.pgfault_index = index; 1116 vcpu->arch.pgfault_hpte[0] = v; 1117 vcpu->arch.pgfault_hpte[1] = r; 1118 vcpu->arch.pgfault_cache = cache_entry; 1119 1120 /* Check the storage key to see if it is possibly emulated MMIO */ 1121 if ((r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) == 1122 (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) { 1123 if (!cache_entry) { 1124 unsigned int pshift = 12; 1125 unsigned int pshift_index; 1126 1127 if (slb_v & SLB_VSID_L) { 1128 pshift_index = ((slb_v & SLB_VSID_LP) >> 4); 1129 pshift = slb_base_page_shift[pshift_index]; 1130 } 1131 cache_entry = next_mmio_cache_entry(vcpu); 1132 cache_entry->eaddr = addr; 1133 cache_entry->slb_base_pshift = pshift; 1134 cache_entry->pte_index = index; 1135 cache_entry->hpte_v = v; 1136 cache_entry->hpte_r = r; 1137 cache_entry->rpte = gr; 1138 cache_entry->slb_v = slb_v; 1139 cache_entry->mmio_update = mmio_update; 1140 } 1141 if (data && (vcpu->arch.shregs.msr & MSR_IR)) 1142 return -2; /* MMIO emulation - load instr word */ 1143 } 1144 1145 return -1; /* send fault up to host kernel mode */ 1146 } 1147