1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * Copyright 2012 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/string.h> 11 #include <linux/kvm.h> 12 #include <linux/kvm_host.h> 13 #include <linux/kernel.h> 14 #include <asm/opal.h> 15 #include <asm/mce.h> 16 #include <asm/machdep.h> 17 #include <asm/cputhreads.h> 18 #include <asm/hmi.h> 19 #include <asm/kvm_ppc.h> 20 21 /* SRR1 bits for machine check on POWER7 */ 22 #define SRR1_MC_LDSTERR (1ul << (63-42)) 23 #define SRR1_MC_IFETCH_SH (63-45) 24 #define SRR1_MC_IFETCH_MASK 0x7 25 #define SRR1_MC_IFETCH_SLBPAR 2 /* SLB parity error */ 26 #define SRR1_MC_IFETCH_SLBMULTI 3 /* SLB multi-hit */ 27 #define SRR1_MC_IFETCH_SLBPARMULTI 4 /* SLB parity + multi-hit */ 28 #define SRR1_MC_IFETCH_TLBMULTI 5 /* I-TLB multi-hit */ 29 30 /* DSISR bits for machine check on POWER7 */ 31 #define DSISR_MC_DERAT_MULTI 0x800 /* D-ERAT multi-hit */ 32 #define DSISR_MC_TLB_MULTI 0x400 /* D-TLB multi-hit */ 33 #define DSISR_MC_SLB_PARITY 0x100 /* SLB parity error */ 34 #define DSISR_MC_SLB_MULTI 0x080 /* SLB multi-hit */ 35 #define DSISR_MC_SLB_PARMULTI 0x040 /* SLB parity + multi-hit */ 36 37 /* POWER7 SLB flush and reload */ 38 static void reload_slb(struct kvm_vcpu *vcpu) 39 { 40 struct slb_shadow *slb; 41 unsigned long i, n; 42 43 /* First clear out SLB */ 44 asm volatile("slbmte %0,%0; slbia" : : "r" (0)); 45 46 /* Do they have an SLB shadow buffer registered? */ 47 slb = vcpu->arch.slb_shadow.pinned_addr; 48 if (!slb) 49 return; 50 51 /* Sanity check */ 52 n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE); 53 if ((void *) &slb->save_area[n] > vcpu->arch.slb_shadow.pinned_end) 54 return; 55 56 /* Load up the SLB from that */ 57 for (i = 0; i < n; ++i) { 58 unsigned long rb = be64_to_cpu(slb->save_area[i].esid); 59 unsigned long rs = be64_to_cpu(slb->save_area[i].vsid); 60 61 rb = (rb & ~0xFFFul) | i; /* insert entry number */ 62 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb)); 63 } 64 } 65 66 /* 67 * On POWER7, see if we can handle a machine check that occurred inside 68 * the guest in real mode, without switching to the host partition. 69 * 70 * Returns: 0 => exit guest, 1 => deliver machine check to guest 71 */ 72 static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu) 73 { 74 unsigned long srr1 = vcpu->arch.shregs.msr; 75 struct machine_check_event mce_evt; 76 long handled = 1; 77 78 if (srr1 & SRR1_MC_LDSTERR) { 79 /* error on load/store */ 80 unsigned long dsisr = vcpu->arch.shregs.dsisr; 81 82 if (dsisr & (DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI | 83 DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI)) { 84 /* flush and reload SLB; flushes D-ERAT too */ 85 reload_slb(vcpu); 86 dsisr &= ~(DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI | 87 DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI); 88 } 89 if (dsisr & DSISR_MC_TLB_MULTI) { 90 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) 91 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_LPID); 92 dsisr &= ~DSISR_MC_TLB_MULTI; 93 } 94 /* Any other errors we don't understand? */ 95 if (dsisr & 0xffffffffUL) 96 handled = 0; 97 } 98 99 switch ((srr1 >> SRR1_MC_IFETCH_SH) & SRR1_MC_IFETCH_MASK) { 100 case 0: 101 break; 102 case SRR1_MC_IFETCH_SLBPAR: 103 case SRR1_MC_IFETCH_SLBMULTI: 104 case SRR1_MC_IFETCH_SLBPARMULTI: 105 reload_slb(vcpu); 106 break; 107 case SRR1_MC_IFETCH_TLBMULTI: 108 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) 109 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_LPID); 110 break; 111 default: 112 handled = 0; 113 } 114 115 /* 116 * See if we have already handled the condition in the linux host. 117 * We assume that if the condition is recovered then linux host 118 * will have generated an error log event that we will pick 119 * up and log later. 120 * Don't release mce event now. We will queue up the event so that 121 * we can log the MCE event info on host console. 122 */ 123 if (!get_mce_event(&mce_evt, MCE_EVENT_DONTRELEASE)) 124 goto out; 125 126 if (mce_evt.version == MCE_V1 && 127 (mce_evt.severity == MCE_SEV_NO_ERROR || 128 mce_evt.disposition == MCE_DISPOSITION_RECOVERED)) 129 handled = 1; 130 131 out: 132 /* 133 * We are now going enter guest either through machine check 134 * interrupt (for unhandled errors) or will continue from 135 * current HSRR0 (for handled errors) in guest. Hence 136 * queue up the event so that we can log it from host console later. 137 */ 138 machine_check_queue_event(); 139 140 return handled; 141 } 142 143 long kvmppc_realmode_machine_check(struct kvm_vcpu *vcpu) 144 { 145 return kvmppc_realmode_mc_power7(vcpu); 146 } 147 148 /* Check if dynamic split is in force and return subcore size accordingly. */ 149 static inline int kvmppc_cur_subcore_size(void) 150 { 151 if (local_paca->kvm_hstate.kvm_split_mode) 152 return local_paca->kvm_hstate.kvm_split_mode->subcore_size; 153 154 return threads_per_subcore; 155 } 156 157 void kvmppc_subcore_enter_guest(void) 158 { 159 int thread_id, subcore_id; 160 161 thread_id = cpu_thread_in_core(local_paca->paca_index); 162 subcore_id = thread_id / kvmppc_cur_subcore_size(); 163 164 local_paca->sibling_subcore_state->in_guest[subcore_id] = 1; 165 } 166 167 void kvmppc_subcore_exit_guest(void) 168 { 169 int thread_id, subcore_id; 170 171 thread_id = cpu_thread_in_core(local_paca->paca_index); 172 subcore_id = thread_id / kvmppc_cur_subcore_size(); 173 174 local_paca->sibling_subcore_state->in_guest[subcore_id] = 0; 175 } 176 177 static bool kvmppc_tb_resync_required(void) 178 { 179 if (test_and_set_bit(CORE_TB_RESYNC_REQ_BIT, 180 &local_paca->sibling_subcore_state->flags)) 181 return false; 182 183 return true; 184 } 185 186 static void kvmppc_tb_resync_done(void) 187 { 188 clear_bit(CORE_TB_RESYNC_REQ_BIT, 189 &local_paca->sibling_subcore_state->flags); 190 } 191 192 /* 193 * kvmppc_realmode_hmi_handler() is called only by primary thread during 194 * guest exit path. 195 * 196 * There are multiple reasons why HMI could occur, one of them is 197 * Timebase (TB) error. If this HMI is due to TB error, then TB would 198 * have been in stopped state. The opal hmi handler Will fix it and 199 * restore the TB value with host timebase value. For HMI caused due 200 * to non-TB errors, opal hmi handler will not touch/restore TB register 201 * and hence there won't be any change in TB value. 202 * 203 * Since we are not sure about the cause of this HMI, we can't be sure 204 * about the content of TB register whether it holds guest or host timebase 205 * value. Hence the idea is to resync the TB on every HMI, so that we 206 * know about the exact state of the TB value. Resync TB call will 207 * restore TB to host timebase. 208 * 209 * Things to consider: 210 * - On TB error, HMI interrupt is reported on all the threads of the core 211 * that has encountered TB error irrespective of split-core mode. 212 * - The very first thread on the core that get chance to fix TB error 213 * would rsync the TB with local chipTOD value. 214 * - The resync TB is a core level action i.e. it will sync all the TBs 215 * in that core independent of split-core mode. This means if we trigger 216 * TB sync from a thread from one subcore, it would affect TB values of 217 * sibling subcores of the same core. 218 * 219 * All threads need to co-ordinate before making opal hmi handler. 220 * All threads will use sibling_subcore_state->in_guest[] (shared by all 221 * threads in the core) in paca which holds information about whether 222 * sibling subcores are in Guest mode or host mode. The in_guest[] array 223 * is of size MAX_SUBCORE_PER_CORE=4, indexed using subcore id to set/unset 224 * subcore status. Only primary threads from each subcore is responsible 225 * to set/unset its designated array element while entering/exiting the 226 * guset. 227 * 228 * After invoking opal hmi handler call, one of the thread (of entire core) 229 * will need to resync the TB. Bit 63 from subcore state bitmap flags 230 * (sibling_subcore_state->flags) will be used to co-ordinate between 231 * primary threads to decide who takes up the responsibility. 232 * 233 * This is what we do: 234 * - Primary thread from each subcore tries to set resync required bit[63] 235 * of paca->sibling_subcore_state->flags. 236 * - The first primary thread that is able to set the flag takes the 237 * responsibility of TB resync. (Let us call it as thread leader) 238 * - All other threads which are in host will call 239 * wait_for_subcore_guest_exit() and wait for in_guest[0-3] from 240 * paca->sibling_subcore_state to get cleared. 241 * - All the primary thread will clear its subcore status from subcore 242 * state in_guest[] array respectively. 243 * - Once all primary threads clear in_guest[0-3], all of them will invoke 244 * opal hmi handler. 245 * - Now all threads will wait for TB resync to complete by invoking 246 * wait_for_tb_resync() except the thread leader. 247 * - Thread leader will do a TB resync by invoking opal_resync_timebase() 248 * call and the it will clear the resync required bit. 249 * - All other threads will now come out of resync wait loop and proceed 250 * with individual execution. 251 * - On return of this function, primary thread will signal all 252 * secondary threads to proceed. 253 * - All secondary threads will eventually call opal hmi handler on 254 * their exit path. 255 */ 256 257 long kvmppc_realmode_hmi_handler(void) 258 { 259 int ptid = local_paca->kvm_hstate.ptid; 260 bool resync_req; 261 262 /* This is only called on primary thread. */ 263 BUG_ON(ptid != 0); 264 __this_cpu_inc(irq_stat.hmi_exceptions); 265 266 /* 267 * By now primary thread has already completed guest->host 268 * partition switch but haven't signaled secondaries yet. 269 * All the secondary threads on this subcore is waiting 270 * for primary thread to signal them to go ahead. 271 * 272 * For threads from subcore which isn't in guest, they all will 273 * wait until all other subcores on this core exit the guest. 274 * 275 * Now set the resync required bit. If you are the first to 276 * set this bit then kvmppc_tb_resync_required() function will 277 * return true. For rest all other subcores 278 * kvmppc_tb_resync_required() will return false. 279 * 280 * If resync_req == true, then this thread is responsible to 281 * initiate TB resync after hmi handler has completed. 282 * All other threads on this core will wait until this thread 283 * clears the resync required bit flag. 284 */ 285 resync_req = kvmppc_tb_resync_required(); 286 287 /* Reset the subcore status to indicate it has exited guest */ 288 kvmppc_subcore_exit_guest(); 289 290 /* 291 * Wait for other subcores on this core to exit the guest. 292 * All the primary threads and threads from subcore that are 293 * not in guest will wait here until all subcores are out 294 * of guest context. 295 */ 296 wait_for_subcore_guest_exit(); 297 298 /* 299 * At this point we are sure that primary threads from each 300 * subcore on this core have completed guest->host partition 301 * switch. Now it is safe to call HMI handler. 302 */ 303 if (ppc_md.hmi_exception_early) 304 ppc_md.hmi_exception_early(NULL); 305 306 /* 307 * Check if this thread is responsible to resync TB. 308 * All other threads will wait until this thread completes the 309 * TB resync. 310 */ 311 if (resync_req) { 312 opal_resync_timebase(); 313 /* Reset TB resync req bit */ 314 kvmppc_tb_resync_done(); 315 } else { 316 wait_for_tb_resync(); 317 } 318 return 0; 319 } 320