1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright SUSE Linux Products GmbH 2009 16 * 17 * Authors: Alexander Graf <agraf@suse.de> 18 */ 19 20 #include <asm/kvm_ppc.h> 21 #include <asm/disassemble.h> 22 #include <asm/kvm_book3s.h> 23 #include <asm/reg.h> 24 #include <asm/switch_to.h> 25 #include <asm/time.h> 26 27 #define OP_19_XOP_RFID 18 28 #define OP_19_XOP_RFI 50 29 30 #define OP_31_XOP_MFMSR 83 31 #define OP_31_XOP_MTMSR 146 32 #define OP_31_XOP_MTMSRD 178 33 #define OP_31_XOP_MTSR 210 34 #define OP_31_XOP_MTSRIN 242 35 #define OP_31_XOP_TLBIEL 274 36 #define OP_31_XOP_TLBIE 306 37 #define OP_31_XOP_SLBMTE 402 38 #define OP_31_XOP_SLBIE 434 39 #define OP_31_XOP_SLBIA 498 40 #define OP_31_XOP_MFSR 595 41 #define OP_31_XOP_MFSRIN 659 42 #define OP_31_XOP_DCBA 758 43 #define OP_31_XOP_SLBMFEV 851 44 #define OP_31_XOP_EIOIO 854 45 #define OP_31_XOP_SLBMFEE 915 46 47 /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ 48 #define OP_31_XOP_DCBZ 1010 49 50 #define OP_LFS 48 51 #define OP_LFD 50 52 #define OP_STFS 52 53 #define OP_STFD 54 54 55 #define SPRN_GQR0 912 56 #define SPRN_GQR1 913 57 #define SPRN_GQR2 914 58 #define SPRN_GQR3 915 59 #define SPRN_GQR4 916 60 #define SPRN_GQR5 917 61 #define SPRN_GQR6 918 62 #define SPRN_GQR7 919 63 64 /* Book3S_32 defines mfsrin(v) - but that messes up our abstract 65 * function pointers, so let's just disable the define. */ 66 #undef mfsrin 67 68 enum priv_level { 69 PRIV_PROBLEM = 0, 70 PRIV_SUPER = 1, 71 PRIV_HYPER = 2, 72 }; 73 74 static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level) 75 { 76 /* PAPR VMs only access supervisor SPRs */ 77 if (vcpu->arch.papr_enabled && (level > PRIV_SUPER)) 78 return false; 79 80 /* Limit user space to its own small SPR set */ 81 if ((vcpu->arch.shared->msr & MSR_PR) && level > PRIV_PROBLEM) 82 return false; 83 84 return true; 85 } 86 87 int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, 88 unsigned int inst, int *advance) 89 { 90 int emulated = EMULATE_DONE; 91 int rt = get_rt(inst); 92 int rs = get_rs(inst); 93 int ra = get_ra(inst); 94 int rb = get_rb(inst); 95 96 switch (get_op(inst)) { 97 case 19: 98 switch (get_xop(inst)) { 99 case OP_19_XOP_RFID: 100 case OP_19_XOP_RFI: 101 kvmppc_set_pc(vcpu, vcpu->arch.shared->srr0); 102 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1); 103 *advance = 0; 104 break; 105 106 default: 107 emulated = EMULATE_FAIL; 108 break; 109 } 110 break; 111 case 31: 112 switch (get_xop(inst)) { 113 case OP_31_XOP_MFMSR: 114 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr); 115 break; 116 case OP_31_XOP_MTMSRD: 117 { 118 ulong rs_val = kvmppc_get_gpr(vcpu, rs); 119 if (inst & 0x10000) { 120 ulong new_msr = vcpu->arch.shared->msr; 121 new_msr &= ~(MSR_RI | MSR_EE); 122 new_msr |= rs_val & (MSR_RI | MSR_EE); 123 vcpu->arch.shared->msr = new_msr; 124 } else 125 kvmppc_set_msr(vcpu, rs_val); 126 break; 127 } 128 case OP_31_XOP_MTMSR: 129 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs)); 130 break; 131 case OP_31_XOP_MFSR: 132 { 133 int srnum; 134 135 srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32); 136 if (vcpu->arch.mmu.mfsrin) { 137 u32 sr; 138 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); 139 kvmppc_set_gpr(vcpu, rt, sr); 140 } 141 break; 142 } 143 case OP_31_XOP_MFSRIN: 144 { 145 int srnum; 146 147 srnum = (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf; 148 if (vcpu->arch.mmu.mfsrin) { 149 u32 sr; 150 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); 151 kvmppc_set_gpr(vcpu, rt, sr); 152 } 153 break; 154 } 155 case OP_31_XOP_MTSR: 156 vcpu->arch.mmu.mtsrin(vcpu, 157 (inst >> 16) & 0xf, 158 kvmppc_get_gpr(vcpu, rs)); 159 break; 160 case OP_31_XOP_MTSRIN: 161 vcpu->arch.mmu.mtsrin(vcpu, 162 (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf, 163 kvmppc_get_gpr(vcpu, rs)); 164 break; 165 case OP_31_XOP_TLBIE: 166 case OP_31_XOP_TLBIEL: 167 { 168 bool large = (inst & 0x00200000) ? true : false; 169 ulong addr = kvmppc_get_gpr(vcpu, rb); 170 vcpu->arch.mmu.tlbie(vcpu, addr, large); 171 break; 172 } 173 case OP_31_XOP_EIOIO: 174 break; 175 case OP_31_XOP_SLBMTE: 176 if (!vcpu->arch.mmu.slbmte) 177 return EMULATE_FAIL; 178 179 vcpu->arch.mmu.slbmte(vcpu, 180 kvmppc_get_gpr(vcpu, rs), 181 kvmppc_get_gpr(vcpu, rb)); 182 break; 183 case OP_31_XOP_SLBIE: 184 if (!vcpu->arch.mmu.slbie) 185 return EMULATE_FAIL; 186 187 vcpu->arch.mmu.slbie(vcpu, 188 kvmppc_get_gpr(vcpu, rb)); 189 break; 190 case OP_31_XOP_SLBIA: 191 if (!vcpu->arch.mmu.slbia) 192 return EMULATE_FAIL; 193 194 vcpu->arch.mmu.slbia(vcpu); 195 break; 196 case OP_31_XOP_SLBMFEE: 197 if (!vcpu->arch.mmu.slbmfee) { 198 emulated = EMULATE_FAIL; 199 } else { 200 ulong t, rb_val; 201 202 rb_val = kvmppc_get_gpr(vcpu, rb); 203 t = vcpu->arch.mmu.slbmfee(vcpu, rb_val); 204 kvmppc_set_gpr(vcpu, rt, t); 205 } 206 break; 207 case OP_31_XOP_SLBMFEV: 208 if (!vcpu->arch.mmu.slbmfev) { 209 emulated = EMULATE_FAIL; 210 } else { 211 ulong t, rb_val; 212 213 rb_val = kvmppc_get_gpr(vcpu, rb); 214 t = vcpu->arch.mmu.slbmfev(vcpu, rb_val); 215 kvmppc_set_gpr(vcpu, rt, t); 216 } 217 break; 218 case OP_31_XOP_DCBA: 219 /* Gets treated as NOP */ 220 break; 221 case OP_31_XOP_DCBZ: 222 { 223 ulong rb_val = kvmppc_get_gpr(vcpu, rb); 224 ulong ra_val = 0; 225 ulong addr, vaddr; 226 u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 227 u32 dsisr; 228 int r; 229 230 if (ra) 231 ra_val = kvmppc_get_gpr(vcpu, ra); 232 233 addr = (ra_val + rb_val) & ~31ULL; 234 if (!(vcpu->arch.shared->msr & MSR_SF)) 235 addr &= 0xffffffff; 236 vaddr = addr; 237 238 r = kvmppc_st(vcpu, &addr, 32, zeros, true); 239 if ((r == -ENOENT) || (r == -EPERM)) { 240 struct kvmppc_book3s_shadow_vcpu *svcpu; 241 242 svcpu = svcpu_get(vcpu); 243 *advance = 0; 244 vcpu->arch.shared->dar = vaddr; 245 svcpu->fault_dar = vaddr; 246 247 dsisr = DSISR_ISSTORE; 248 if (r == -ENOENT) 249 dsisr |= DSISR_NOHPTE; 250 else if (r == -EPERM) 251 dsisr |= DSISR_PROTFAULT; 252 253 vcpu->arch.shared->dsisr = dsisr; 254 svcpu->fault_dsisr = dsisr; 255 svcpu_put(svcpu); 256 257 kvmppc_book3s_queue_irqprio(vcpu, 258 BOOK3S_INTERRUPT_DATA_STORAGE); 259 } 260 261 break; 262 } 263 default: 264 emulated = EMULATE_FAIL; 265 } 266 break; 267 default: 268 emulated = EMULATE_FAIL; 269 } 270 271 if (emulated == EMULATE_FAIL) 272 emulated = kvmppc_emulate_paired_single(run, vcpu); 273 274 return emulated; 275 } 276 277 void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper, 278 u32 val) 279 { 280 if (upper) { 281 /* Upper BAT */ 282 u32 bl = (val >> 2) & 0x7ff; 283 bat->bepi_mask = (~bl << 17); 284 bat->bepi = val & 0xfffe0000; 285 bat->vs = (val & 2) ? 1 : 0; 286 bat->vp = (val & 1) ? 1 : 0; 287 bat->raw = (bat->raw & 0xffffffff00000000ULL) | val; 288 } else { 289 /* Lower BAT */ 290 bat->brpn = val & 0xfffe0000; 291 bat->wimg = (val >> 3) & 0xf; 292 bat->pp = val & 3; 293 bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32); 294 } 295 } 296 297 static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn) 298 { 299 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); 300 struct kvmppc_bat *bat; 301 302 switch (sprn) { 303 case SPRN_IBAT0U ... SPRN_IBAT3L: 304 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2]; 305 break; 306 case SPRN_IBAT4U ... SPRN_IBAT7L: 307 bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)]; 308 break; 309 case SPRN_DBAT0U ... SPRN_DBAT3L: 310 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2]; 311 break; 312 case SPRN_DBAT4U ... SPRN_DBAT7L: 313 bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)]; 314 break; 315 default: 316 BUG(); 317 } 318 319 return bat; 320 } 321 322 int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val) 323 { 324 int emulated = EMULATE_DONE; 325 326 switch (sprn) { 327 case SPRN_SDR1: 328 if (!spr_allowed(vcpu, PRIV_HYPER)) 329 goto unprivileged; 330 to_book3s(vcpu)->sdr1 = spr_val; 331 break; 332 case SPRN_DSISR: 333 vcpu->arch.shared->dsisr = spr_val; 334 break; 335 case SPRN_DAR: 336 vcpu->arch.shared->dar = spr_val; 337 break; 338 case SPRN_HIOR: 339 to_book3s(vcpu)->hior = spr_val; 340 break; 341 case SPRN_IBAT0U ... SPRN_IBAT3L: 342 case SPRN_IBAT4U ... SPRN_IBAT7L: 343 case SPRN_DBAT0U ... SPRN_DBAT3L: 344 case SPRN_DBAT4U ... SPRN_DBAT7L: 345 { 346 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn); 347 348 kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val); 349 /* BAT writes happen so rarely that we're ok to flush 350 * everything here */ 351 kvmppc_mmu_pte_flush(vcpu, 0, 0); 352 kvmppc_mmu_flush_segments(vcpu); 353 break; 354 } 355 case SPRN_HID0: 356 to_book3s(vcpu)->hid[0] = spr_val; 357 break; 358 case SPRN_HID1: 359 to_book3s(vcpu)->hid[1] = spr_val; 360 break; 361 case SPRN_HID2: 362 to_book3s(vcpu)->hid[2] = spr_val; 363 break; 364 case SPRN_HID2_GEKKO: 365 to_book3s(vcpu)->hid[2] = spr_val; 366 /* HID2.PSE controls paired single on gekko */ 367 switch (vcpu->arch.pvr) { 368 case 0x00080200: /* lonestar 2.0 */ 369 case 0x00088202: /* lonestar 2.2 */ 370 case 0x70000100: /* gekko 1.0 */ 371 case 0x00080100: /* gekko 2.0 */ 372 case 0x00083203: /* gekko 2.3a */ 373 case 0x00083213: /* gekko 2.3b */ 374 case 0x00083204: /* gekko 2.4 */ 375 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ 376 case 0x00087200: /* broadway */ 377 if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) { 378 /* Native paired singles */ 379 } else if (spr_val & (1 << 29)) { /* HID2.PSE */ 380 vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE; 381 kvmppc_giveup_ext(vcpu, MSR_FP); 382 } else { 383 vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE; 384 } 385 break; 386 } 387 break; 388 case SPRN_HID4: 389 case SPRN_HID4_GEKKO: 390 to_book3s(vcpu)->hid[4] = spr_val; 391 break; 392 case SPRN_HID5: 393 to_book3s(vcpu)->hid[5] = spr_val; 394 /* guest HID5 set can change is_dcbz32 */ 395 if (vcpu->arch.mmu.is_dcbz32(vcpu) && 396 (mfmsr() & MSR_HV)) 397 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 398 break; 399 case SPRN_PURR: 400 to_book3s(vcpu)->purr_offset = spr_val - get_tb(); 401 break; 402 case SPRN_SPURR: 403 to_book3s(vcpu)->spurr_offset = spr_val - get_tb(); 404 break; 405 case SPRN_GQR0: 406 case SPRN_GQR1: 407 case SPRN_GQR2: 408 case SPRN_GQR3: 409 case SPRN_GQR4: 410 case SPRN_GQR5: 411 case SPRN_GQR6: 412 case SPRN_GQR7: 413 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val; 414 break; 415 case SPRN_ICTC: 416 case SPRN_THRM1: 417 case SPRN_THRM2: 418 case SPRN_THRM3: 419 case SPRN_CTRLF: 420 case SPRN_CTRLT: 421 case SPRN_L2CR: 422 case SPRN_DSCR: 423 case SPRN_MMCR0_GEKKO: 424 case SPRN_MMCR1_GEKKO: 425 case SPRN_PMC1_GEKKO: 426 case SPRN_PMC2_GEKKO: 427 case SPRN_PMC3_GEKKO: 428 case SPRN_PMC4_GEKKO: 429 case SPRN_WPAR_GEKKO: 430 break; 431 unprivileged: 432 default: 433 printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn); 434 #ifndef DEBUG_SPR 435 emulated = EMULATE_FAIL; 436 #endif 437 break; 438 } 439 440 return emulated; 441 } 442 443 int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val) 444 { 445 int emulated = EMULATE_DONE; 446 447 switch (sprn) { 448 case SPRN_IBAT0U ... SPRN_IBAT3L: 449 case SPRN_IBAT4U ... SPRN_IBAT7L: 450 case SPRN_DBAT0U ... SPRN_DBAT3L: 451 case SPRN_DBAT4U ... SPRN_DBAT7L: 452 { 453 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn); 454 455 if (sprn % 2) 456 *spr_val = bat->raw >> 32; 457 else 458 *spr_val = bat->raw; 459 460 break; 461 } 462 case SPRN_SDR1: 463 if (!spr_allowed(vcpu, PRIV_HYPER)) 464 goto unprivileged; 465 *spr_val = to_book3s(vcpu)->sdr1; 466 break; 467 case SPRN_DSISR: 468 *spr_val = vcpu->arch.shared->dsisr; 469 break; 470 case SPRN_DAR: 471 *spr_val = vcpu->arch.shared->dar; 472 break; 473 case SPRN_HIOR: 474 *spr_val = to_book3s(vcpu)->hior; 475 break; 476 case SPRN_HID0: 477 *spr_val = to_book3s(vcpu)->hid[0]; 478 break; 479 case SPRN_HID1: 480 *spr_val = to_book3s(vcpu)->hid[1]; 481 break; 482 case SPRN_HID2: 483 case SPRN_HID2_GEKKO: 484 *spr_val = to_book3s(vcpu)->hid[2]; 485 break; 486 case SPRN_HID4: 487 case SPRN_HID4_GEKKO: 488 *spr_val = to_book3s(vcpu)->hid[4]; 489 break; 490 case SPRN_HID5: 491 *spr_val = to_book3s(vcpu)->hid[5]; 492 break; 493 case SPRN_CFAR: 494 case SPRN_DSCR: 495 *spr_val = 0; 496 break; 497 case SPRN_PURR: 498 *spr_val = get_tb() + to_book3s(vcpu)->purr_offset; 499 break; 500 case SPRN_SPURR: 501 *spr_val = get_tb() + to_book3s(vcpu)->purr_offset; 502 break; 503 case SPRN_GQR0: 504 case SPRN_GQR1: 505 case SPRN_GQR2: 506 case SPRN_GQR3: 507 case SPRN_GQR4: 508 case SPRN_GQR5: 509 case SPRN_GQR6: 510 case SPRN_GQR7: 511 *spr_val = to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]; 512 break; 513 case SPRN_THRM1: 514 case SPRN_THRM2: 515 case SPRN_THRM3: 516 case SPRN_CTRLF: 517 case SPRN_CTRLT: 518 case SPRN_L2CR: 519 case SPRN_MMCR0_GEKKO: 520 case SPRN_MMCR1_GEKKO: 521 case SPRN_PMC1_GEKKO: 522 case SPRN_PMC2_GEKKO: 523 case SPRN_PMC3_GEKKO: 524 case SPRN_PMC4_GEKKO: 525 case SPRN_WPAR_GEKKO: 526 *spr_val = 0; 527 break; 528 default: 529 unprivileged: 530 printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn); 531 #ifndef DEBUG_SPR 532 emulated = EMULATE_FAIL; 533 #endif 534 break; 535 } 536 537 return emulated; 538 } 539 540 u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst) 541 { 542 u32 dsisr = 0; 543 544 /* 545 * This is what the spec says about DSISR bits (not mentioned = 0): 546 * 547 * 12:13 [DS] Set to bits 30:31 548 * 15:16 [X] Set to bits 29:30 549 * 17 [X] Set to bit 25 550 * [D/DS] Set to bit 5 551 * 18:21 [X] Set to bits 21:24 552 * [D/DS] Set to bits 1:4 553 * 22:26 Set to bits 6:10 (RT/RS/FRT/FRS) 554 * 27:31 Set to bits 11:15 (RA) 555 */ 556 557 switch (get_op(inst)) { 558 /* D-form */ 559 case OP_LFS: 560 case OP_LFD: 561 case OP_STFD: 562 case OP_STFS: 563 dsisr |= (inst >> 12) & 0x4000; /* bit 17 */ 564 dsisr |= (inst >> 17) & 0x3c00; /* bits 18:21 */ 565 break; 566 /* X-form */ 567 case 31: 568 dsisr |= (inst << 14) & 0x18000; /* bits 15:16 */ 569 dsisr |= (inst << 8) & 0x04000; /* bit 17 */ 570 dsisr |= (inst << 3) & 0x03c00; /* bits 18:21 */ 571 break; 572 default: 573 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst); 574 break; 575 } 576 577 dsisr |= (inst >> 16) & 0x03ff; /* bits 22:31 */ 578 579 return dsisr; 580 } 581 582 ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst) 583 { 584 ulong dar = 0; 585 ulong ra = get_ra(inst); 586 ulong rb = get_rb(inst); 587 588 switch (get_op(inst)) { 589 case OP_LFS: 590 case OP_LFD: 591 case OP_STFD: 592 case OP_STFS: 593 if (ra) 594 dar = kvmppc_get_gpr(vcpu, ra); 595 dar += (s32)((s16)inst); 596 break; 597 case 31: 598 if (ra) 599 dar = kvmppc_get_gpr(vcpu, ra); 600 dar += kvmppc_get_gpr(vcpu, rb); 601 break; 602 default: 603 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst); 604 break; 605 } 606 607 return dar; 608 } 609