1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright SUSE Linux Products GmbH 2009 16 * 17 * Authors: Alexander Graf <agraf@suse.de> 18 */ 19 20 #include <asm/kvm_ppc.h> 21 #include <asm/disassemble.h> 22 #include <asm/kvm_book3s.h> 23 #include <asm/reg.h> 24 #include <asm/switch_to.h> 25 #include <asm/time.h> 26 #include <asm/tm.h> 27 #include "book3s.h" 28 #include <asm/asm-prototypes.h> 29 30 #define OP_19_XOP_RFID 18 31 #define OP_19_XOP_RFI 50 32 33 #define OP_31_XOP_MFMSR 83 34 #define OP_31_XOP_MTMSR 146 35 #define OP_31_XOP_MTMSRD 178 36 #define OP_31_XOP_MTSR 210 37 #define OP_31_XOP_MTSRIN 242 38 #define OP_31_XOP_TLBIEL 274 39 /* Opcode is officially reserved, reuse it as sc 1 when sc 1 doesn't trap */ 40 #define OP_31_XOP_FAKE_SC1 308 41 #define OP_31_XOP_SLBMTE 402 42 #define OP_31_XOP_SLBIE 434 43 #define OP_31_XOP_SLBIA 498 44 #define OP_31_XOP_MFSR 595 45 #define OP_31_XOP_MFSRIN 659 46 #define OP_31_XOP_DCBA 758 47 #define OP_31_XOP_SLBMFEV 851 48 #define OP_31_XOP_EIOIO 854 49 #define OP_31_XOP_SLBMFEE 915 50 51 #define OP_31_XOP_TBEGIN 654 52 #define OP_31_XOP_TABORT 910 53 54 #define OP_31_XOP_TRECLAIM 942 55 #define OP_31_XOP_TRCHKPT 1006 56 57 /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ 58 #define OP_31_XOP_DCBZ 1010 59 60 #define OP_LFS 48 61 #define OP_LFD 50 62 #define OP_STFS 52 63 #define OP_STFD 54 64 65 #define SPRN_GQR0 912 66 #define SPRN_GQR1 913 67 #define SPRN_GQR2 914 68 #define SPRN_GQR3 915 69 #define SPRN_GQR4 916 70 #define SPRN_GQR5 917 71 #define SPRN_GQR6 918 72 #define SPRN_GQR7 919 73 74 /* Book3S_32 defines mfsrin(v) - but that messes up our abstract 75 * function pointers, so let's just disable the define. */ 76 #undef mfsrin 77 78 enum priv_level { 79 PRIV_PROBLEM = 0, 80 PRIV_SUPER = 1, 81 PRIV_HYPER = 2, 82 }; 83 84 static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level) 85 { 86 /* PAPR VMs only access supervisor SPRs */ 87 if (vcpu->arch.papr_enabled && (level > PRIV_SUPER)) 88 return false; 89 90 /* Limit user space to its own small SPR set */ 91 if ((kvmppc_get_msr(vcpu) & MSR_PR) && level > PRIV_PROBLEM) 92 return false; 93 94 return true; 95 } 96 97 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 98 static inline void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu) 99 { 100 memcpy(&vcpu->arch.gpr_tm[0], &vcpu->arch.regs.gpr[0], 101 sizeof(vcpu->arch.gpr_tm)); 102 memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp, 103 sizeof(struct thread_fp_state)); 104 memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr, 105 sizeof(struct thread_vr_state)); 106 vcpu->arch.ppr_tm = vcpu->arch.ppr; 107 vcpu->arch.dscr_tm = vcpu->arch.dscr; 108 vcpu->arch.amr_tm = vcpu->arch.amr; 109 vcpu->arch.ctr_tm = vcpu->arch.regs.ctr; 110 vcpu->arch.tar_tm = vcpu->arch.tar; 111 vcpu->arch.lr_tm = vcpu->arch.regs.link; 112 vcpu->arch.cr_tm = vcpu->arch.regs.ccr; 113 vcpu->arch.xer_tm = vcpu->arch.regs.xer; 114 vcpu->arch.vrsave_tm = vcpu->arch.vrsave; 115 } 116 117 static inline void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu) 118 { 119 memcpy(&vcpu->arch.regs.gpr[0], &vcpu->arch.gpr_tm[0], 120 sizeof(vcpu->arch.regs.gpr)); 121 memcpy(&vcpu->arch.fp, &vcpu->arch.fp_tm, 122 sizeof(struct thread_fp_state)); 123 memcpy(&vcpu->arch.vr, &vcpu->arch.vr_tm, 124 sizeof(struct thread_vr_state)); 125 vcpu->arch.ppr = vcpu->arch.ppr_tm; 126 vcpu->arch.dscr = vcpu->arch.dscr_tm; 127 vcpu->arch.amr = vcpu->arch.amr_tm; 128 vcpu->arch.regs.ctr = vcpu->arch.ctr_tm; 129 vcpu->arch.tar = vcpu->arch.tar_tm; 130 vcpu->arch.regs.link = vcpu->arch.lr_tm; 131 vcpu->arch.regs.ccr = vcpu->arch.cr_tm; 132 vcpu->arch.regs.xer = vcpu->arch.xer_tm; 133 vcpu->arch.vrsave = vcpu->arch.vrsave_tm; 134 } 135 136 static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val) 137 { 138 unsigned long guest_msr = kvmppc_get_msr(vcpu); 139 int fc_val = ra_val ? ra_val : 1; 140 uint64_t texasr; 141 142 /* CR0 = 0 | MSR[TS] | 0 */ 143 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) | 144 (((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1)) 145 << CR0_SHIFT); 146 147 preempt_disable(); 148 tm_enable(); 149 texasr = mfspr(SPRN_TEXASR); 150 kvmppc_save_tm_pr(vcpu); 151 kvmppc_copyfrom_vcpu_tm(vcpu); 152 153 /* failure recording depends on Failure Summary bit */ 154 if (!(texasr & TEXASR_FS)) { 155 texasr &= ~TEXASR_FC; 156 texasr |= ((u64)fc_val << TEXASR_FC_LG) | TEXASR_FS; 157 158 texasr &= ~(TEXASR_PR | TEXASR_HV); 159 if (kvmppc_get_msr(vcpu) & MSR_PR) 160 texasr |= TEXASR_PR; 161 162 if (kvmppc_get_msr(vcpu) & MSR_HV) 163 texasr |= TEXASR_HV; 164 165 vcpu->arch.texasr = texasr; 166 vcpu->arch.tfiar = kvmppc_get_pc(vcpu); 167 mtspr(SPRN_TEXASR, texasr); 168 mtspr(SPRN_TFIAR, vcpu->arch.tfiar); 169 } 170 tm_disable(); 171 /* 172 * treclaim need quit to non-transactional state. 173 */ 174 guest_msr &= ~(MSR_TS_MASK); 175 kvmppc_set_msr(vcpu, guest_msr); 176 preempt_enable(); 177 178 if (vcpu->arch.shadow_fscr & FSCR_TAR) 179 mtspr(SPRN_TAR, vcpu->arch.tar); 180 } 181 182 static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu) 183 { 184 unsigned long guest_msr = kvmppc_get_msr(vcpu); 185 186 preempt_disable(); 187 /* 188 * need flush FP/VEC/VSX to vcpu save area before 189 * copy. 190 */ 191 kvmppc_giveup_ext(vcpu, MSR_VSX); 192 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 193 kvmppc_copyto_vcpu_tm(vcpu); 194 kvmppc_save_tm_sprs(vcpu); 195 196 /* 197 * as a result of trecheckpoint. set TS to suspended. 198 */ 199 guest_msr &= ~(MSR_TS_MASK); 200 guest_msr |= MSR_TS_S; 201 kvmppc_set_msr(vcpu, guest_msr); 202 kvmppc_restore_tm_pr(vcpu); 203 preempt_enable(); 204 } 205 206 /* emulate tabort. at guest privilege state */ 207 void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val) 208 { 209 /* currently we only emulate tabort. but no emulation of other 210 * tabort variants since there is no kernel usage of them at 211 * present. 212 */ 213 unsigned long guest_msr = kvmppc_get_msr(vcpu); 214 uint64_t org_texasr; 215 216 preempt_disable(); 217 tm_enable(); 218 org_texasr = mfspr(SPRN_TEXASR); 219 tm_abort(ra_val); 220 221 /* CR0 = 0 | MSR[TS] | 0 */ 222 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) | 223 (((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1)) 224 << CR0_SHIFT); 225 226 vcpu->arch.texasr = mfspr(SPRN_TEXASR); 227 /* failure recording depends on Failure Summary bit, 228 * and tabort will be treated as nops in non-transactional 229 * state. 230 */ 231 if (!(org_texasr & TEXASR_FS) && 232 MSR_TM_ACTIVE(guest_msr)) { 233 vcpu->arch.texasr &= ~(TEXASR_PR | TEXASR_HV); 234 if (guest_msr & MSR_PR) 235 vcpu->arch.texasr |= TEXASR_PR; 236 237 if (guest_msr & MSR_HV) 238 vcpu->arch.texasr |= TEXASR_HV; 239 240 vcpu->arch.tfiar = kvmppc_get_pc(vcpu); 241 } 242 tm_disable(); 243 preempt_enable(); 244 } 245 246 #endif 247 248 int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, 249 unsigned int inst, int *advance) 250 { 251 int emulated = EMULATE_DONE; 252 int rt = get_rt(inst); 253 int rs = get_rs(inst); 254 int ra = get_ra(inst); 255 int rb = get_rb(inst); 256 u32 inst_sc = 0x44000002; 257 258 switch (get_op(inst)) { 259 case 0: 260 emulated = EMULATE_FAIL; 261 if ((kvmppc_get_msr(vcpu) & MSR_LE) && 262 (inst == swab32(inst_sc))) { 263 /* 264 * This is the byte reversed syscall instruction of our 265 * hypercall handler. Early versions of LE Linux didn't 266 * swap the instructions correctly and ended up in 267 * illegal instructions. 268 * Just always fail hypercalls on these broken systems. 269 */ 270 kvmppc_set_gpr(vcpu, 3, EV_UNIMPLEMENTED); 271 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); 272 emulated = EMULATE_DONE; 273 } 274 break; 275 case 19: 276 switch (get_xop(inst)) { 277 case OP_19_XOP_RFID: 278 case OP_19_XOP_RFI: { 279 unsigned long srr1 = kvmppc_get_srr1(vcpu); 280 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 281 unsigned long cur_msr = kvmppc_get_msr(vcpu); 282 283 /* 284 * add rules to fit in ISA specification regarding TM 285 * state transistion in TM disable/Suspended state, 286 * and target TM state is TM inactive(00) state. (the 287 * change should be suppressed). 288 */ 289 if (((cur_msr & MSR_TM) == 0) && 290 ((srr1 & MSR_TM) == 0) && 291 MSR_TM_SUSPENDED(cur_msr) && 292 !MSR_TM_ACTIVE(srr1)) 293 srr1 |= MSR_TS_S; 294 #endif 295 kvmppc_set_pc(vcpu, kvmppc_get_srr0(vcpu)); 296 kvmppc_set_msr(vcpu, srr1); 297 *advance = 0; 298 break; 299 } 300 301 default: 302 emulated = EMULATE_FAIL; 303 break; 304 } 305 break; 306 case 31: 307 switch (get_xop(inst)) { 308 case OP_31_XOP_MFMSR: 309 kvmppc_set_gpr(vcpu, rt, kvmppc_get_msr(vcpu)); 310 break; 311 case OP_31_XOP_MTMSRD: 312 { 313 ulong rs_val = kvmppc_get_gpr(vcpu, rs); 314 if (inst & 0x10000) { 315 ulong new_msr = kvmppc_get_msr(vcpu); 316 new_msr &= ~(MSR_RI | MSR_EE); 317 new_msr |= rs_val & (MSR_RI | MSR_EE); 318 kvmppc_set_msr_fast(vcpu, new_msr); 319 } else 320 kvmppc_set_msr(vcpu, rs_val); 321 break; 322 } 323 case OP_31_XOP_MTMSR: 324 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs)); 325 break; 326 case OP_31_XOP_MFSR: 327 { 328 int srnum; 329 330 srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32); 331 if (vcpu->arch.mmu.mfsrin) { 332 u32 sr; 333 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); 334 kvmppc_set_gpr(vcpu, rt, sr); 335 } 336 break; 337 } 338 case OP_31_XOP_MFSRIN: 339 { 340 int srnum; 341 342 srnum = (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf; 343 if (vcpu->arch.mmu.mfsrin) { 344 u32 sr; 345 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); 346 kvmppc_set_gpr(vcpu, rt, sr); 347 } 348 break; 349 } 350 case OP_31_XOP_MTSR: 351 vcpu->arch.mmu.mtsrin(vcpu, 352 (inst >> 16) & 0xf, 353 kvmppc_get_gpr(vcpu, rs)); 354 break; 355 case OP_31_XOP_MTSRIN: 356 vcpu->arch.mmu.mtsrin(vcpu, 357 (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf, 358 kvmppc_get_gpr(vcpu, rs)); 359 break; 360 case OP_31_XOP_TLBIE: 361 case OP_31_XOP_TLBIEL: 362 { 363 bool large = (inst & 0x00200000) ? true : false; 364 ulong addr = kvmppc_get_gpr(vcpu, rb); 365 vcpu->arch.mmu.tlbie(vcpu, addr, large); 366 break; 367 } 368 #ifdef CONFIG_PPC_BOOK3S_64 369 case OP_31_XOP_FAKE_SC1: 370 { 371 /* SC 1 papr hypercalls */ 372 ulong cmd = kvmppc_get_gpr(vcpu, 3); 373 int i; 374 375 if ((kvmppc_get_msr(vcpu) & MSR_PR) || 376 !vcpu->arch.papr_enabled) { 377 emulated = EMULATE_FAIL; 378 break; 379 } 380 381 if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) 382 break; 383 384 run->papr_hcall.nr = cmd; 385 for (i = 0; i < 9; ++i) { 386 ulong gpr = kvmppc_get_gpr(vcpu, 4 + i); 387 run->papr_hcall.args[i] = gpr; 388 } 389 390 run->exit_reason = KVM_EXIT_PAPR_HCALL; 391 vcpu->arch.hcall_needed = 1; 392 emulated = EMULATE_EXIT_USER; 393 break; 394 } 395 #endif 396 case OP_31_XOP_EIOIO: 397 break; 398 case OP_31_XOP_SLBMTE: 399 if (!vcpu->arch.mmu.slbmte) 400 return EMULATE_FAIL; 401 402 vcpu->arch.mmu.slbmte(vcpu, 403 kvmppc_get_gpr(vcpu, rs), 404 kvmppc_get_gpr(vcpu, rb)); 405 break; 406 case OP_31_XOP_SLBIE: 407 if (!vcpu->arch.mmu.slbie) 408 return EMULATE_FAIL; 409 410 vcpu->arch.mmu.slbie(vcpu, 411 kvmppc_get_gpr(vcpu, rb)); 412 break; 413 case OP_31_XOP_SLBIA: 414 if (!vcpu->arch.mmu.slbia) 415 return EMULATE_FAIL; 416 417 vcpu->arch.mmu.slbia(vcpu); 418 break; 419 case OP_31_XOP_SLBMFEE: 420 if (!vcpu->arch.mmu.slbmfee) { 421 emulated = EMULATE_FAIL; 422 } else { 423 ulong t, rb_val; 424 425 rb_val = kvmppc_get_gpr(vcpu, rb); 426 t = vcpu->arch.mmu.slbmfee(vcpu, rb_val); 427 kvmppc_set_gpr(vcpu, rt, t); 428 } 429 break; 430 case OP_31_XOP_SLBMFEV: 431 if (!vcpu->arch.mmu.slbmfev) { 432 emulated = EMULATE_FAIL; 433 } else { 434 ulong t, rb_val; 435 436 rb_val = kvmppc_get_gpr(vcpu, rb); 437 t = vcpu->arch.mmu.slbmfev(vcpu, rb_val); 438 kvmppc_set_gpr(vcpu, rt, t); 439 } 440 break; 441 case OP_31_XOP_DCBA: 442 /* Gets treated as NOP */ 443 break; 444 case OP_31_XOP_DCBZ: 445 { 446 ulong rb_val = kvmppc_get_gpr(vcpu, rb); 447 ulong ra_val = 0; 448 ulong addr, vaddr; 449 u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 450 u32 dsisr; 451 int r; 452 453 if (ra) 454 ra_val = kvmppc_get_gpr(vcpu, ra); 455 456 addr = (ra_val + rb_val) & ~31ULL; 457 if (!(kvmppc_get_msr(vcpu) & MSR_SF)) 458 addr &= 0xffffffff; 459 vaddr = addr; 460 461 r = kvmppc_st(vcpu, &addr, 32, zeros, true); 462 if ((r == -ENOENT) || (r == -EPERM)) { 463 *advance = 0; 464 kvmppc_set_dar(vcpu, vaddr); 465 vcpu->arch.fault_dar = vaddr; 466 467 dsisr = DSISR_ISSTORE; 468 if (r == -ENOENT) 469 dsisr |= DSISR_NOHPTE; 470 else if (r == -EPERM) 471 dsisr |= DSISR_PROTFAULT; 472 473 kvmppc_set_dsisr(vcpu, dsisr); 474 vcpu->arch.fault_dsisr = dsisr; 475 476 kvmppc_book3s_queue_irqprio(vcpu, 477 BOOK3S_INTERRUPT_DATA_STORAGE); 478 } 479 480 break; 481 } 482 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 483 case OP_31_XOP_TBEGIN: 484 { 485 if (!cpu_has_feature(CPU_FTR_TM)) 486 break; 487 488 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { 489 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); 490 emulated = EMULATE_AGAIN; 491 break; 492 } 493 494 if (!(kvmppc_get_msr(vcpu) & MSR_PR)) { 495 preempt_disable(); 496 vcpu->arch.regs.ccr = (CR0_TBEGIN_FAILURE | 497 (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT))); 498 499 vcpu->arch.texasr = (TEXASR_FS | TEXASR_EXACT | 500 (((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 501 << TEXASR_FC_LG)); 502 503 if ((inst >> 21) & 0x1) 504 vcpu->arch.texasr |= TEXASR_ROT; 505 506 if (kvmppc_get_msr(vcpu) & MSR_HV) 507 vcpu->arch.texasr |= TEXASR_HV; 508 509 vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4; 510 vcpu->arch.tfiar = kvmppc_get_pc(vcpu); 511 512 kvmppc_restore_tm_sprs(vcpu); 513 preempt_enable(); 514 } else 515 emulated = EMULATE_FAIL; 516 break; 517 } 518 case OP_31_XOP_TABORT: 519 { 520 ulong guest_msr = kvmppc_get_msr(vcpu); 521 unsigned long ra_val = 0; 522 523 if (!cpu_has_feature(CPU_FTR_TM)) 524 break; 525 526 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { 527 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); 528 emulated = EMULATE_AGAIN; 529 break; 530 } 531 532 /* only emulate for privilege guest, since problem state 533 * guest can run with TM enabled and we don't expect to 534 * trap at here for that case. 535 */ 536 WARN_ON(guest_msr & MSR_PR); 537 538 if (ra) 539 ra_val = kvmppc_get_gpr(vcpu, ra); 540 541 kvmppc_emulate_tabort(vcpu, ra_val); 542 break; 543 } 544 case OP_31_XOP_TRECLAIM: 545 { 546 ulong guest_msr = kvmppc_get_msr(vcpu); 547 unsigned long ra_val = 0; 548 549 if (!cpu_has_feature(CPU_FTR_TM)) 550 break; 551 552 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { 553 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); 554 emulated = EMULATE_AGAIN; 555 break; 556 } 557 558 /* generate interrupts based on priorities */ 559 if (guest_msr & MSR_PR) { 560 /* Privileged Instruction type Program Interrupt */ 561 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV); 562 emulated = EMULATE_AGAIN; 563 break; 564 } 565 566 if (!MSR_TM_ACTIVE(guest_msr)) { 567 /* TM bad thing interrupt */ 568 kvmppc_core_queue_program(vcpu, SRR1_PROGTM); 569 emulated = EMULATE_AGAIN; 570 break; 571 } 572 573 if (ra) 574 ra_val = kvmppc_get_gpr(vcpu, ra); 575 kvmppc_emulate_treclaim(vcpu, ra_val); 576 break; 577 } 578 case OP_31_XOP_TRCHKPT: 579 { 580 ulong guest_msr = kvmppc_get_msr(vcpu); 581 unsigned long texasr; 582 583 if (!cpu_has_feature(CPU_FTR_TM)) 584 break; 585 586 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { 587 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); 588 emulated = EMULATE_AGAIN; 589 break; 590 } 591 592 /* generate interrupt based on priorities */ 593 if (guest_msr & MSR_PR) { 594 /* Privileged Instruction type Program Intr */ 595 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV); 596 emulated = EMULATE_AGAIN; 597 break; 598 } 599 600 tm_enable(); 601 texasr = mfspr(SPRN_TEXASR); 602 tm_disable(); 603 604 if (MSR_TM_ACTIVE(guest_msr) || 605 !(texasr & (TEXASR_FS))) { 606 /* TM bad thing interrupt */ 607 kvmppc_core_queue_program(vcpu, SRR1_PROGTM); 608 emulated = EMULATE_AGAIN; 609 break; 610 } 611 612 kvmppc_emulate_trchkpt(vcpu); 613 break; 614 } 615 #endif 616 default: 617 emulated = EMULATE_FAIL; 618 } 619 break; 620 default: 621 emulated = EMULATE_FAIL; 622 } 623 624 if (emulated == EMULATE_FAIL) 625 emulated = kvmppc_emulate_paired_single(run, vcpu); 626 627 return emulated; 628 } 629 630 void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper, 631 u32 val) 632 { 633 if (upper) { 634 /* Upper BAT */ 635 u32 bl = (val >> 2) & 0x7ff; 636 bat->bepi_mask = (~bl << 17); 637 bat->bepi = val & 0xfffe0000; 638 bat->vs = (val & 2) ? 1 : 0; 639 bat->vp = (val & 1) ? 1 : 0; 640 bat->raw = (bat->raw & 0xffffffff00000000ULL) | val; 641 } else { 642 /* Lower BAT */ 643 bat->brpn = val & 0xfffe0000; 644 bat->wimg = (val >> 3) & 0xf; 645 bat->pp = val & 3; 646 bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32); 647 } 648 } 649 650 static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn) 651 { 652 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); 653 struct kvmppc_bat *bat; 654 655 switch (sprn) { 656 case SPRN_IBAT0U ... SPRN_IBAT3L: 657 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2]; 658 break; 659 case SPRN_IBAT4U ... SPRN_IBAT7L: 660 bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)]; 661 break; 662 case SPRN_DBAT0U ... SPRN_DBAT3L: 663 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2]; 664 break; 665 case SPRN_DBAT4U ... SPRN_DBAT7L: 666 bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)]; 667 break; 668 default: 669 BUG(); 670 } 671 672 return bat; 673 } 674 675 int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val) 676 { 677 int emulated = EMULATE_DONE; 678 679 switch (sprn) { 680 case SPRN_SDR1: 681 if (!spr_allowed(vcpu, PRIV_HYPER)) 682 goto unprivileged; 683 to_book3s(vcpu)->sdr1 = spr_val; 684 break; 685 case SPRN_DSISR: 686 kvmppc_set_dsisr(vcpu, spr_val); 687 break; 688 case SPRN_DAR: 689 kvmppc_set_dar(vcpu, spr_val); 690 break; 691 case SPRN_HIOR: 692 to_book3s(vcpu)->hior = spr_val; 693 break; 694 case SPRN_IBAT0U ... SPRN_IBAT3L: 695 case SPRN_IBAT4U ... SPRN_IBAT7L: 696 case SPRN_DBAT0U ... SPRN_DBAT3L: 697 case SPRN_DBAT4U ... SPRN_DBAT7L: 698 { 699 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn); 700 701 kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val); 702 /* BAT writes happen so rarely that we're ok to flush 703 * everything here */ 704 kvmppc_mmu_pte_flush(vcpu, 0, 0); 705 kvmppc_mmu_flush_segments(vcpu); 706 break; 707 } 708 case SPRN_HID0: 709 to_book3s(vcpu)->hid[0] = spr_val; 710 break; 711 case SPRN_HID1: 712 to_book3s(vcpu)->hid[1] = spr_val; 713 break; 714 case SPRN_HID2: 715 to_book3s(vcpu)->hid[2] = spr_val; 716 break; 717 case SPRN_HID2_GEKKO: 718 to_book3s(vcpu)->hid[2] = spr_val; 719 /* HID2.PSE controls paired single on gekko */ 720 switch (vcpu->arch.pvr) { 721 case 0x00080200: /* lonestar 2.0 */ 722 case 0x00088202: /* lonestar 2.2 */ 723 case 0x70000100: /* gekko 1.0 */ 724 case 0x00080100: /* gekko 2.0 */ 725 case 0x00083203: /* gekko 2.3a */ 726 case 0x00083213: /* gekko 2.3b */ 727 case 0x00083204: /* gekko 2.4 */ 728 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ 729 case 0x00087200: /* broadway */ 730 if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) { 731 /* Native paired singles */ 732 } else if (spr_val & (1 << 29)) { /* HID2.PSE */ 733 vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE; 734 kvmppc_giveup_ext(vcpu, MSR_FP); 735 } else { 736 vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE; 737 } 738 break; 739 } 740 break; 741 case SPRN_HID4: 742 case SPRN_HID4_GEKKO: 743 to_book3s(vcpu)->hid[4] = spr_val; 744 break; 745 case SPRN_HID5: 746 to_book3s(vcpu)->hid[5] = spr_val; 747 /* guest HID5 set can change is_dcbz32 */ 748 if (vcpu->arch.mmu.is_dcbz32(vcpu) && 749 (mfmsr() & MSR_HV)) 750 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 751 break; 752 case SPRN_GQR0: 753 case SPRN_GQR1: 754 case SPRN_GQR2: 755 case SPRN_GQR3: 756 case SPRN_GQR4: 757 case SPRN_GQR5: 758 case SPRN_GQR6: 759 case SPRN_GQR7: 760 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val; 761 break; 762 #ifdef CONFIG_PPC_BOOK3S_64 763 case SPRN_FSCR: 764 kvmppc_set_fscr(vcpu, spr_val); 765 break; 766 case SPRN_BESCR: 767 vcpu->arch.bescr = spr_val; 768 break; 769 case SPRN_EBBHR: 770 vcpu->arch.ebbhr = spr_val; 771 break; 772 case SPRN_EBBRR: 773 vcpu->arch.ebbrr = spr_val; 774 break; 775 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 776 case SPRN_TFHAR: 777 case SPRN_TEXASR: 778 case SPRN_TFIAR: 779 if (!cpu_has_feature(CPU_FTR_TM)) 780 break; 781 782 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { 783 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); 784 emulated = EMULATE_AGAIN; 785 break; 786 } 787 788 if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)) && 789 !((MSR_TM_SUSPENDED(kvmppc_get_msr(vcpu))) && 790 (sprn == SPRN_TFHAR))) { 791 /* it is illegal to mtspr() TM regs in 792 * other than non-transactional state, with 793 * the exception of TFHAR in suspend state. 794 */ 795 kvmppc_core_queue_program(vcpu, SRR1_PROGTM); 796 emulated = EMULATE_AGAIN; 797 break; 798 } 799 800 tm_enable(); 801 if (sprn == SPRN_TFHAR) 802 mtspr(SPRN_TFHAR, spr_val); 803 else if (sprn == SPRN_TEXASR) 804 mtspr(SPRN_TEXASR, spr_val); 805 else 806 mtspr(SPRN_TFIAR, spr_val); 807 tm_disable(); 808 809 break; 810 #endif 811 #endif 812 case SPRN_ICTC: 813 case SPRN_THRM1: 814 case SPRN_THRM2: 815 case SPRN_THRM3: 816 case SPRN_CTRLF: 817 case SPRN_CTRLT: 818 case SPRN_L2CR: 819 case SPRN_DSCR: 820 case SPRN_MMCR0_GEKKO: 821 case SPRN_MMCR1_GEKKO: 822 case SPRN_PMC1_GEKKO: 823 case SPRN_PMC2_GEKKO: 824 case SPRN_PMC3_GEKKO: 825 case SPRN_PMC4_GEKKO: 826 case SPRN_WPAR_GEKKO: 827 case SPRN_MSSSR0: 828 case SPRN_DABR: 829 #ifdef CONFIG_PPC_BOOK3S_64 830 case SPRN_MMCRS: 831 case SPRN_MMCRA: 832 case SPRN_MMCR0: 833 case SPRN_MMCR1: 834 case SPRN_MMCR2: 835 case SPRN_UMMCR2: 836 #endif 837 break; 838 unprivileged: 839 default: 840 pr_info_ratelimited("KVM: invalid SPR write: %d\n", sprn); 841 if (sprn & 0x10) { 842 if (kvmppc_get_msr(vcpu) & MSR_PR) { 843 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV); 844 emulated = EMULATE_AGAIN; 845 } 846 } else { 847 if ((kvmppc_get_msr(vcpu) & MSR_PR) || sprn == 0) { 848 kvmppc_core_queue_program(vcpu, SRR1_PROGILL); 849 emulated = EMULATE_AGAIN; 850 } 851 } 852 break; 853 } 854 855 return emulated; 856 } 857 858 int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val) 859 { 860 int emulated = EMULATE_DONE; 861 862 switch (sprn) { 863 case SPRN_IBAT0U ... SPRN_IBAT3L: 864 case SPRN_IBAT4U ... SPRN_IBAT7L: 865 case SPRN_DBAT0U ... SPRN_DBAT3L: 866 case SPRN_DBAT4U ... SPRN_DBAT7L: 867 { 868 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn); 869 870 if (sprn % 2) 871 *spr_val = bat->raw >> 32; 872 else 873 *spr_val = bat->raw; 874 875 break; 876 } 877 case SPRN_SDR1: 878 if (!spr_allowed(vcpu, PRIV_HYPER)) 879 goto unprivileged; 880 *spr_val = to_book3s(vcpu)->sdr1; 881 break; 882 case SPRN_DSISR: 883 *spr_val = kvmppc_get_dsisr(vcpu); 884 break; 885 case SPRN_DAR: 886 *spr_val = kvmppc_get_dar(vcpu); 887 break; 888 case SPRN_HIOR: 889 *spr_val = to_book3s(vcpu)->hior; 890 break; 891 case SPRN_HID0: 892 *spr_val = to_book3s(vcpu)->hid[0]; 893 break; 894 case SPRN_HID1: 895 *spr_val = to_book3s(vcpu)->hid[1]; 896 break; 897 case SPRN_HID2: 898 case SPRN_HID2_GEKKO: 899 *spr_val = to_book3s(vcpu)->hid[2]; 900 break; 901 case SPRN_HID4: 902 case SPRN_HID4_GEKKO: 903 *spr_val = to_book3s(vcpu)->hid[4]; 904 break; 905 case SPRN_HID5: 906 *spr_val = to_book3s(vcpu)->hid[5]; 907 break; 908 case SPRN_CFAR: 909 case SPRN_DSCR: 910 *spr_val = 0; 911 break; 912 case SPRN_PURR: 913 /* 914 * On exit we would have updated purr 915 */ 916 *spr_val = vcpu->arch.purr; 917 break; 918 case SPRN_SPURR: 919 /* 920 * On exit we would have updated spurr 921 */ 922 *spr_val = vcpu->arch.spurr; 923 break; 924 case SPRN_VTB: 925 *spr_val = to_book3s(vcpu)->vtb; 926 break; 927 case SPRN_IC: 928 *spr_val = vcpu->arch.ic; 929 break; 930 case SPRN_GQR0: 931 case SPRN_GQR1: 932 case SPRN_GQR2: 933 case SPRN_GQR3: 934 case SPRN_GQR4: 935 case SPRN_GQR5: 936 case SPRN_GQR6: 937 case SPRN_GQR7: 938 *spr_val = to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]; 939 break; 940 #ifdef CONFIG_PPC_BOOK3S_64 941 case SPRN_FSCR: 942 *spr_val = vcpu->arch.fscr; 943 break; 944 case SPRN_BESCR: 945 *spr_val = vcpu->arch.bescr; 946 break; 947 case SPRN_EBBHR: 948 *spr_val = vcpu->arch.ebbhr; 949 break; 950 case SPRN_EBBRR: 951 *spr_val = vcpu->arch.ebbrr; 952 break; 953 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 954 case SPRN_TFHAR: 955 case SPRN_TEXASR: 956 case SPRN_TFIAR: 957 if (!cpu_has_feature(CPU_FTR_TM)) 958 break; 959 960 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { 961 kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); 962 emulated = EMULATE_AGAIN; 963 break; 964 } 965 966 tm_enable(); 967 if (sprn == SPRN_TFHAR) 968 *spr_val = mfspr(SPRN_TFHAR); 969 else if (sprn == SPRN_TEXASR) 970 *spr_val = mfspr(SPRN_TEXASR); 971 else if (sprn == SPRN_TFIAR) 972 *spr_val = mfspr(SPRN_TFIAR); 973 tm_disable(); 974 break; 975 #endif 976 #endif 977 case SPRN_THRM1: 978 case SPRN_THRM2: 979 case SPRN_THRM3: 980 case SPRN_CTRLF: 981 case SPRN_CTRLT: 982 case SPRN_L2CR: 983 case SPRN_MMCR0_GEKKO: 984 case SPRN_MMCR1_GEKKO: 985 case SPRN_PMC1_GEKKO: 986 case SPRN_PMC2_GEKKO: 987 case SPRN_PMC3_GEKKO: 988 case SPRN_PMC4_GEKKO: 989 case SPRN_WPAR_GEKKO: 990 case SPRN_MSSSR0: 991 case SPRN_DABR: 992 #ifdef CONFIG_PPC_BOOK3S_64 993 case SPRN_MMCRS: 994 case SPRN_MMCRA: 995 case SPRN_MMCR0: 996 case SPRN_MMCR1: 997 case SPRN_MMCR2: 998 case SPRN_UMMCR2: 999 case SPRN_TIR: 1000 #endif 1001 *spr_val = 0; 1002 break; 1003 default: 1004 unprivileged: 1005 pr_info_ratelimited("KVM: invalid SPR read: %d\n", sprn); 1006 if (sprn & 0x10) { 1007 if (kvmppc_get_msr(vcpu) & MSR_PR) { 1008 kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV); 1009 emulated = EMULATE_AGAIN; 1010 } 1011 } else { 1012 if ((kvmppc_get_msr(vcpu) & MSR_PR) || sprn == 0 || 1013 sprn == 4 || sprn == 5 || sprn == 6) { 1014 kvmppc_core_queue_program(vcpu, SRR1_PROGILL); 1015 emulated = EMULATE_AGAIN; 1016 } 1017 } 1018 1019 break; 1020 } 1021 1022 return emulated; 1023 } 1024 1025 u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst) 1026 { 1027 return make_dsisr(inst); 1028 } 1029 1030 ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst) 1031 { 1032 #ifdef CONFIG_PPC_BOOK3S_64 1033 /* 1034 * Linux's fix_alignment() assumes that DAR is valid, so can we 1035 */ 1036 return vcpu->arch.fault_dar; 1037 #else 1038 ulong dar = 0; 1039 ulong ra = get_ra(inst); 1040 ulong rb = get_rb(inst); 1041 1042 switch (get_op(inst)) { 1043 case OP_LFS: 1044 case OP_LFD: 1045 case OP_STFD: 1046 case OP_STFS: 1047 if (ra) 1048 dar = kvmppc_get_gpr(vcpu, ra); 1049 dar += (s32)((s16)inst); 1050 break; 1051 case 31: 1052 if (ra) 1053 dar = kvmppc_get_gpr(vcpu, ra); 1054 dar += kvmppc_get_gpr(vcpu, rb); 1055 break; 1056 default: 1057 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst); 1058 break; 1059 } 1060 1061 return dar; 1062 #endif 1063 } 1064