1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/sched/debug.h> 21 #include <linux/kernel.h> 22 #include <linux/mm.h> 23 #include <linux/stddef.h> 24 #include <linux/unistd.h> 25 #include <linux/ptrace.h> 26 #include <linux/user.h> 27 #include <linux/interrupt.h> 28 #include <linux/init.h> 29 #include <linux/extable.h> 30 #include <linux/module.h> /* print_modules */ 31 #include <linux/prctl.h> 32 #include <linux/delay.h> 33 #include <linux/kprobes.h> 34 #include <linux/kexec.h> 35 #include <linux/backlight.h> 36 #include <linux/bug.h> 37 #include <linux/kdebug.h> 38 #include <linux/ratelimit.h> 39 #include <linux/context_tracking.h> 40 41 #include <asm/emulated_ops.h> 42 #include <asm/pgtable.h> 43 #include <linux/uaccess.h> 44 #include <asm/debugfs.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #include <asm/tm.h> 57 #endif 58 #include <asm/kexec.h> 59 #include <asm/ppc-opcode.h> 60 #include <asm/rio.h> 61 #include <asm/fadump.h> 62 #include <asm/switch_to.h> 63 #include <asm/tm.h> 64 #include <asm/debug.h> 65 #include <asm/asm-prototypes.h> 66 #include <asm/hmi.h> 67 #include <sysdev/fsl_pci.h> 68 #include <asm/kprobes.h> 69 70 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 71 int (*__debugger)(struct pt_regs *regs) __read_mostly; 72 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 73 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 78 79 EXPORT_SYMBOL(__debugger); 80 EXPORT_SYMBOL(__debugger_ipi); 81 EXPORT_SYMBOL(__debugger_bpt); 82 EXPORT_SYMBOL(__debugger_sstep); 83 EXPORT_SYMBOL(__debugger_iabr_match); 84 EXPORT_SYMBOL(__debugger_break_match); 85 EXPORT_SYMBOL(__debugger_fault_handler); 86 #endif 87 88 /* Transactional Memory trap debug */ 89 #ifdef TM_DEBUG_SW 90 #define TM_DEBUG(x...) printk(KERN_INFO x) 91 #else 92 #define TM_DEBUG(x...) do { } while(0) 93 #endif 94 95 /* 96 * Trap & Exception support 97 */ 98 99 #ifdef CONFIG_PMAC_BACKLIGHT 100 static void pmac_backlight_unblank(void) 101 { 102 mutex_lock(&pmac_backlight_mutex); 103 if (pmac_backlight) { 104 struct backlight_properties *props; 105 106 props = &pmac_backlight->props; 107 props->brightness = props->max_brightness; 108 props->power = FB_BLANK_UNBLANK; 109 backlight_update_status(pmac_backlight); 110 } 111 mutex_unlock(&pmac_backlight_mutex); 112 } 113 #else 114 static inline void pmac_backlight_unblank(void) { } 115 #endif 116 117 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 118 static int die_owner = -1; 119 static unsigned int die_nest_count; 120 static int die_counter; 121 122 static unsigned long oops_begin(struct pt_regs *regs) 123 { 124 int cpu; 125 unsigned long flags; 126 127 oops_enter(); 128 129 /* racy, but better than risking deadlock. */ 130 raw_local_irq_save(flags); 131 cpu = smp_processor_id(); 132 if (!arch_spin_trylock(&die_lock)) { 133 if (cpu == die_owner) 134 /* nested oops. should stop eventually */; 135 else 136 arch_spin_lock(&die_lock); 137 } 138 die_nest_count++; 139 die_owner = cpu; 140 console_verbose(); 141 bust_spinlocks(1); 142 if (machine_is(powermac)) 143 pmac_backlight_unblank(); 144 return flags; 145 } 146 NOKPROBE_SYMBOL(oops_begin); 147 148 static void oops_end(unsigned long flags, struct pt_regs *regs, 149 int signr) 150 { 151 bust_spinlocks(0); 152 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 153 die_nest_count--; 154 oops_exit(); 155 printk("\n"); 156 if (!die_nest_count) { 157 /* Nest count reaches zero, release the lock. */ 158 die_owner = -1; 159 arch_spin_unlock(&die_lock); 160 } 161 raw_local_irq_restore(flags); 162 163 crash_fadump(regs, "die oops"); 164 165 /* 166 * A system reset (0x100) is a request to dump, so we always send 167 * it through the crashdump code. 168 */ 169 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { 170 crash_kexec(regs); 171 172 /* 173 * We aren't the primary crash CPU. We need to send it 174 * to a holding pattern to avoid it ending up in the panic 175 * code. 176 */ 177 crash_kexec_secondary(regs); 178 } 179 180 if (!signr) 181 return; 182 183 /* 184 * While our oops output is serialised by a spinlock, output 185 * from panic() called below can race and corrupt it. If we 186 * know we are going to panic, delay for 1 second so we have a 187 * chance to get clean backtraces from all CPUs that are oopsing. 188 */ 189 if (in_interrupt() || panic_on_oops || !current->pid || 190 is_global_init(current)) { 191 mdelay(MSEC_PER_SEC); 192 } 193 194 if (in_interrupt()) 195 panic("Fatal exception in interrupt"); 196 if (panic_on_oops) 197 panic("Fatal exception"); 198 do_exit(signr); 199 } 200 NOKPROBE_SYMBOL(oops_end); 201 202 static int __die(const char *str, struct pt_regs *regs, long err) 203 { 204 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 205 #ifdef CONFIG_PREEMPT 206 printk("PREEMPT "); 207 #endif 208 #ifdef CONFIG_SMP 209 printk("SMP NR_CPUS=%d ", NR_CPUS); 210 #endif 211 if (debug_pagealloc_enabled()) 212 printk("DEBUG_PAGEALLOC "); 213 #ifdef CONFIG_NUMA 214 printk("NUMA "); 215 #endif 216 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 217 218 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 219 return 1; 220 221 print_modules(); 222 show_regs(regs); 223 224 return 0; 225 } 226 NOKPROBE_SYMBOL(__die); 227 228 void die(const char *str, struct pt_regs *regs, long err) 229 { 230 unsigned long flags; 231 232 if (debugger(regs)) 233 return; 234 235 flags = oops_begin(regs); 236 if (__die(str, regs, err)) 237 err = 0; 238 oops_end(flags, regs, err); 239 } 240 241 void user_single_step_siginfo(struct task_struct *tsk, 242 struct pt_regs *regs, siginfo_t *info) 243 { 244 memset(info, 0, sizeof(*info)); 245 info->si_signo = SIGTRAP; 246 info->si_code = TRAP_TRACE; 247 info->si_addr = (void __user *)regs->nip; 248 } 249 250 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 251 { 252 siginfo_t info; 253 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 254 "at %08lx nip %08lx lr %08lx code %x\n"; 255 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 256 "at %016lx nip %016lx lr %016lx code %x\n"; 257 258 if (!user_mode(regs)) { 259 die("Exception in kernel mode", regs, signr); 260 return; 261 } 262 263 if (show_unhandled_signals && unhandled_signal(current, signr)) { 264 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 265 current->comm, current->pid, signr, 266 addr, regs->nip, regs->link, code); 267 } 268 269 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 270 local_irq_enable(); 271 272 current->thread.trap_nr = code; 273 memset(&info, 0, sizeof(info)); 274 info.si_signo = signr; 275 info.si_code = code; 276 info.si_addr = (void __user *) addr; 277 force_sig_info(signr, &info, current); 278 } 279 280 void system_reset_exception(struct pt_regs *regs) 281 { 282 /* 283 * Avoid crashes in case of nested NMI exceptions. Recoverability 284 * is determined by RI and in_nmi 285 */ 286 bool nested = in_nmi(); 287 if (!nested) 288 nmi_enter(); 289 290 /* See if any machine dependent calls */ 291 if (ppc_md.system_reset_exception) { 292 if (ppc_md.system_reset_exception(regs)) 293 goto out; 294 } 295 296 die("System Reset", regs, SIGABRT); 297 298 out: 299 #ifdef CONFIG_PPC_BOOK3S_64 300 BUG_ON(get_paca()->in_nmi == 0); 301 if (get_paca()->in_nmi > 1) 302 panic("Unrecoverable nested System Reset"); 303 #endif 304 /* Must die if the interrupt is not recoverable */ 305 if (!(regs->msr & MSR_RI)) 306 panic("Unrecoverable System Reset"); 307 308 if (!nested) 309 nmi_exit(); 310 311 /* What should we do here? We could issue a shutdown or hard reset. */ 312 } 313 314 #ifdef CONFIG_PPC64 315 /* 316 * This function is called in real mode. Strictly no printk's please. 317 * 318 * regs->nip and regs->msr contains srr0 and ssr1. 319 */ 320 long machine_check_early(struct pt_regs *regs) 321 { 322 long handled = 0; 323 324 __this_cpu_inc(irq_stat.mce_exceptions); 325 326 if (cur_cpu_spec && cur_cpu_spec->machine_check_early) 327 handled = cur_cpu_spec->machine_check_early(regs); 328 return handled; 329 } 330 331 long hmi_exception_realmode(struct pt_regs *regs) 332 { 333 __this_cpu_inc(irq_stat.hmi_exceptions); 334 335 wait_for_subcore_guest_exit(); 336 337 if (ppc_md.hmi_exception_early) 338 ppc_md.hmi_exception_early(regs); 339 340 wait_for_tb_resync(); 341 342 return 0; 343 } 344 345 #endif 346 347 /* 348 * I/O accesses can cause machine checks on powermacs. 349 * Check if the NIP corresponds to the address of a sync 350 * instruction for which there is an entry in the exception 351 * table. 352 * Note that the 601 only takes a machine check on TEA 353 * (transfer error ack) signal assertion, and does not 354 * set any of the top 16 bits of SRR1. 355 * -- paulus. 356 */ 357 static inline int check_io_access(struct pt_regs *regs) 358 { 359 #ifdef CONFIG_PPC32 360 unsigned long msr = regs->msr; 361 const struct exception_table_entry *entry; 362 unsigned int *nip = (unsigned int *)regs->nip; 363 364 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 365 && (entry = search_exception_tables(regs->nip)) != NULL) { 366 /* 367 * Check that it's a sync instruction, or somewhere 368 * in the twi; isync; nop sequence that inb/inw/inl uses. 369 * As the address is in the exception table 370 * we should be able to read the instr there. 371 * For the debug message, we look at the preceding 372 * load or store. 373 */ 374 if (*nip == PPC_INST_NOP) 375 nip -= 2; 376 else if (*nip == PPC_INST_ISYNC) 377 --nip; 378 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 379 unsigned int rb; 380 381 --nip; 382 rb = (*nip >> 11) & 0x1f; 383 printk(KERN_DEBUG "%s bad port %lx at %p\n", 384 (*nip & 0x100)? "OUT to": "IN from", 385 regs->gpr[rb] - _IO_BASE, nip); 386 regs->msr |= MSR_RI; 387 regs->nip = extable_fixup(entry); 388 return 1; 389 } 390 } 391 #endif /* CONFIG_PPC32 */ 392 return 0; 393 } 394 395 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 396 /* On 4xx, the reason for the machine check or program exception 397 is in the ESR. */ 398 #define get_reason(regs) ((regs)->dsisr) 399 #ifndef CONFIG_FSL_BOOKE 400 #define get_mc_reason(regs) ((regs)->dsisr) 401 #else 402 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 403 #endif 404 #define REASON_FP ESR_FP 405 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 406 #define REASON_PRIVILEGED ESR_PPR 407 #define REASON_TRAP ESR_PTR 408 409 /* single-step stuff */ 410 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 411 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 412 413 #else 414 /* On non-4xx, the reason for the machine check or program 415 exception is in the MSR. */ 416 #define get_reason(regs) ((regs)->msr) 417 #define get_mc_reason(regs) ((regs)->msr) 418 #define REASON_TM 0x200000 419 #define REASON_FP 0x100000 420 #define REASON_ILLEGAL 0x80000 421 #define REASON_PRIVILEGED 0x40000 422 #define REASON_TRAP 0x20000 423 424 #define single_stepping(regs) ((regs)->msr & MSR_SE) 425 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 426 #endif 427 428 #if defined(CONFIG_4xx) 429 int machine_check_4xx(struct pt_regs *regs) 430 { 431 unsigned long reason = get_mc_reason(regs); 432 433 if (reason & ESR_IMCP) { 434 printk("Instruction"); 435 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 436 } else 437 printk("Data"); 438 printk(" machine check in kernel mode.\n"); 439 440 return 0; 441 } 442 443 int machine_check_440A(struct pt_regs *regs) 444 { 445 unsigned long reason = get_mc_reason(regs); 446 447 printk("Machine check in kernel mode.\n"); 448 if (reason & ESR_IMCP){ 449 printk("Instruction Synchronous Machine Check exception\n"); 450 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 451 } 452 else { 453 u32 mcsr = mfspr(SPRN_MCSR); 454 if (mcsr & MCSR_IB) 455 printk("Instruction Read PLB Error\n"); 456 if (mcsr & MCSR_DRB) 457 printk("Data Read PLB Error\n"); 458 if (mcsr & MCSR_DWB) 459 printk("Data Write PLB Error\n"); 460 if (mcsr & MCSR_TLBP) 461 printk("TLB Parity Error\n"); 462 if (mcsr & MCSR_ICP){ 463 flush_instruction_cache(); 464 printk("I-Cache Parity Error\n"); 465 } 466 if (mcsr & MCSR_DCSP) 467 printk("D-Cache Search Parity Error\n"); 468 if (mcsr & MCSR_DCFP) 469 printk("D-Cache Flush Parity Error\n"); 470 if (mcsr & MCSR_IMPE) 471 printk("Machine Check exception is imprecise\n"); 472 473 /* Clear MCSR */ 474 mtspr(SPRN_MCSR, mcsr); 475 } 476 return 0; 477 } 478 479 int machine_check_47x(struct pt_regs *regs) 480 { 481 unsigned long reason = get_mc_reason(regs); 482 u32 mcsr; 483 484 printk(KERN_ERR "Machine check in kernel mode.\n"); 485 if (reason & ESR_IMCP) { 486 printk(KERN_ERR 487 "Instruction Synchronous Machine Check exception\n"); 488 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 489 return 0; 490 } 491 mcsr = mfspr(SPRN_MCSR); 492 if (mcsr & MCSR_IB) 493 printk(KERN_ERR "Instruction Read PLB Error\n"); 494 if (mcsr & MCSR_DRB) 495 printk(KERN_ERR "Data Read PLB Error\n"); 496 if (mcsr & MCSR_DWB) 497 printk(KERN_ERR "Data Write PLB Error\n"); 498 if (mcsr & MCSR_TLBP) 499 printk(KERN_ERR "TLB Parity Error\n"); 500 if (mcsr & MCSR_ICP) { 501 flush_instruction_cache(); 502 printk(KERN_ERR "I-Cache Parity Error\n"); 503 } 504 if (mcsr & MCSR_DCSP) 505 printk(KERN_ERR "D-Cache Search Parity Error\n"); 506 if (mcsr & PPC47x_MCSR_GPR) 507 printk(KERN_ERR "GPR Parity Error\n"); 508 if (mcsr & PPC47x_MCSR_FPR) 509 printk(KERN_ERR "FPR Parity Error\n"); 510 if (mcsr & PPC47x_MCSR_IPR) 511 printk(KERN_ERR "Machine Check exception is imprecise\n"); 512 513 /* Clear MCSR */ 514 mtspr(SPRN_MCSR, mcsr); 515 516 return 0; 517 } 518 #elif defined(CONFIG_E500) 519 int machine_check_e500mc(struct pt_regs *regs) 520 { 521 unsigned long mcsr = mfspr(SPRN_MCSR); 522 unsigned long reason = mcsr; 523 int recoverable = 1; 524 525 if (reason & MCSR_LD) { 526 recoverable = fsl_rio_mcheck_exception(regs); 527 if (recoverable == 1) 528 goto silent_out; 529 } 530 531 printk("Machine check in kernel mode.\n"); 532 printk("Caused by (from MCSR=%lx): ", reason); 533 534 if (reason & MCSR_MCP) 535 printk("Machine Check Signal\n"); 536 537 if (reason & MCSR_ICPERR) { 538 printk("Instruction Cache Parity Error\n"); 539 540 /* 541 * This is recoverable by invalidating the i-cache. 542 */ 543 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 544 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 545 ; 546 547 /* 548 * This will generally be accompanied by an instruction 549 * fetch error report -- only treat MCSR_IF as fatal 550 * if it wasn't due to an L1 parity error. 551 */ 552 reason &= ~MCSR_IF; 553 } 554 555 if (reason & MCSR_DCPERR_MC) { 556 printk("Data Cache Parity Error\n"); 557 558 /* 559 * In write shadow mode we auto-recover from the error, but it 560 * may still get logged and cause a machine check. We should 561 * only treat the non-write shadow case as non-recoverable. 562 */ 563 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 564 recoverable = 0; 565 } 566 567 if (reason & MCSR_L2MMU_MHIT) { 568 printk("Hit on multiple TLB entries\n"); 569 recoverable = 0; 570 } 571 572 if (reason & MCSR_NMI) 573 printk("Non-maskable interrupt\n"); 574 575 if (reason & MCSR_IF) { 576 printk("Instruction Fetch Error Report\n"); 577 recoverable = 0; 578 } 579 580 if (reason & MCSR_LD) { 581 printk("Load Error Report\n"); 582 recoverable = 0; 583 } 584 585 if (reason & MCSR_ST) { 586 printk("Store Error Report\n"); 587 recoverable = 0; 588 } 589 590 if (reason & MCSR_LDG) { 591 printk("Guarded Load Error Report\n"); 592 recoverable = 0; 593 } 594 595 if (reason & MCSR_TLBSYNC) 596 printk("Simultaneous tlbsync operations\n"); 597 598 if (reason & MCSR_BSL2_ERR) { 599 printk("Level 2 Cache Error\n"); 600 recoverable = 0; 601 } 602 603 if (reason & MCSR_MAV) { 604 u64 addr; 605 606 addr = mfspr(SPRN_MCAR); 607 addr |= (u64)mfspr(SPRN_MCARU) << 32; 608 609 printk("Machine Check %s Address: %#llx\n", 610 reason & MCSR_MEA ? "Effective" : "Physical", addr); 611 } 612 613 silent_out: 614 mtspr(SPRN_MCSR, mcsr); 615 return mfspr(SPRN_MCSR) == 0 && recoverable; 616 } 617 618 int machine_check_e500(struct pt_regs *regs) 619 { 620 unsigned long reason = get_mc_reason(regs); 621 622 if (reason & MCSR_BUS_RBERR) { 623 if (fsl_rio_mcheck_exception(regs)) 624 return 1; 625 if (fsl_pci_mcheck_exception(regs)) 626 return 1; 627 } 628 629 printk("Machine check in kernel mode.\n"); 630 printk("Caused by (from MCSR=%lx): ", reason); 631 632 if (reason & MCSR_MCP) 633 printk("Machine Check Signal\n"); 634 if (reason & MCSR_ICPERR) 635 printk("Instruction Cache Parity Error\n"); 636 if (reason & MCSR_DCP_PERR) 637 printk("Data Cache Push Parity Error\n"); 638 if (reason & MCSR_DCPERR) 639 printk("Data Cache Parity Error\n"); 640 if (reason & MCSR_BUS_IAERR) 641 printk("Bus - Instruction Address Error\n"); 642 if (reason & MCSR_BUS_RAERR) 643 printk("Bus - Read Address Error\n"); 644 if (reason & MCSR_BUS_WAERR) 645 printk("Bus - Write Address Error\n"); 646 if (reason & MCSR_BUS_IBERR) 647 printk("Bus - Instruction Data Error\n"); 648 if (reason & MCSR_BUS_RBERR) 649 printk("Bus - Read Data Bus Error\n"); 650 if (reason & MCSR_BUS_WBERR) 651 printk("Bus - Write Data Bus Error\n"); 652 if (reason & MCSR_BUS_IPERR) 653 printk("Bus - Instruction Parity Error\n"); 654 if (reason & MCSR_BUS_RPERR) 655 printk("Bus - Read Parity Error\n"); 656 657 return 0; 658 } 659 660 int machine_check_generic(struct pt_regs *regs) 661 { 662 return 0; 663 } 664 #elif defined(CONFIG_E200) 665 int machine_check_e200(struct pt_regs *regs) 666 { 667 unsigned long reason = get_mc_reason(regs); 668 669 printk("Machine check in kernel mode.\n"); 670 printk("Caused by (from MCSR=%lx): ", reason); 671 672 if (reason & MCSR_MCP) 673 printk("Machine Check Signal\n"); 674 if (reason & MCSR_CP_PERR) 675 printk("Cache Push Parity Error\n"); 676 if (reason & MCSR_CPERR) 677 printk("Cache Parity Error\n"); 678 if (reason & MCSR_EXCP_ERR) 679 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 680 if (reason & MCSR_BUS_IRERR) 681 printk("Bus - Read Bus Error on instruction fetch\n"); 682 if (reason & MCSR_BUS_DRERR) 683 printk("Bus - Read Bus Error on data load\n"); 684 if (reason & MCSR_BUS_WRERR) 685 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 686 687 return 0; 688 } 689 #elif defined(CONFIG_PPC_8xx) 690 int machine_check_8xx(struct pt_regs *regs) 691 { 692 unsigned long reason = get_mc_reason(regs); 693 694 pr_err("Machine check in kernel mode.\n"); 695 pr_err("Caused by (from SRR1=%lx): ", reason); 696 if (reason & 0x40000000) 697 pr_err("Fetch error at address %lx\n", regs->nip); 698 else 699 pr_err("Data access error at address %lx\n", regs->dar); 700 701 #ifdef CONFIG_PCI 702 /* the qspan pci read routines can cause machine checks -- Cort 703 * 704 * yuck !!! that totally needs to go away ! There are better ways 705 * to deal with that than having a wart in the mcheck handler. 706 * -- BenH 707 */ 708 bad_page_fault(regs, regs->dar, SIGBUS); 709 return 1; 710 #else 711 return 0; 712 #endif 713 } 714 #else 715 int machine_check_generic(struct pt_regs *regs) 716 { 717 unsigned long reason = get_mc_reason(regs); 718 719 printk("Machine check in kernel mode.\n"); 720 printk("Caused by (from SRR1=%lx): ", reason); 721 switch (reason & 0x601F0000) { 722 case 0x80000: 723 printk("Machine check signal\n"); 724 break; 725 case 0: /* for 601 */ 726 case 0x40000: 727 case 0x140000: /* 7450 MSS error and TEA */ 728 printk("Transfer error ack signal\n"); 729 break; 730 case 0x20000: 731 printk("Data parity error signal\n"); 732 break; 733 case 0x10000: 734 printk("Address parity error signal\n"); 735 break; 736 case 0x20000000: 737 printk("L1 Data Cache error\n"); 738 break; 739 case 0x40000000: 740 printk("L1 Instruction Cache error\n"); 741 break; 742 case 0x00100000: 743 printk("L2 data cache parity error\n"); 744 break; 745 default: 746 printk("Unknown values in msr\n"); 747 } 748 return 0; 749 } 750 #endif /* everything else */ 751 752 void machine_check_exception(struct pt_regs *regs) 753 { 754 enum ctx_state prev_state = exception_enter(); 755 int recover = 0; 756 757 __this_cpu_inc(irq_stat.mce_exceptions); 758 759 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 760 761 /* See if any machine dependent calls. In theory, we would want 762 * to call the CPU first, and call the ppc_md. one if the CPU 763 * one returns a positive number. However there is existing code 764 * that assumes the board gets a first chance, so let's keep it 765 * that way for now and fix things later. --BenH. 766 */ 767 if (ppc_md.machine_check_exception) 768 recover = ppc_md.machine_check_exception(regs); 769 else if (cur_cpu_spec->machine_check) 770 recover = cur_cpu_spec->machine_check(regs); 771 772 if (recover > 0) 773 goto bail; 774 775 if (debugger_fault_handler(regs)) 776 goto bail; 777 778 if (check_io_access(regs)) 779 goto bail; 780 781 die("Machine check", regs, SIGBUS); 782 783 /* Must die if the interrupt is not recoverable */ 784 if (!(regs->msr & MSR_RI)) 785 panic("Unrecoverable Machine check"); 786 787 bail: 788 exception_exit(prev_state); 789 } 790 791 void SMIException(struct pt_regs *regs) 792 { 793 die("System Management Interrupt", regs, SIGABRT); 794 } 795 796 void handle_hmi_exception(struct pt_regs *regs) 797 { 798 struct pt_regs *old_regs; 799 800 old_regs = set_irq_regs(regs); 801 irq_enter(); 802 803 if (ppc_md.handle_hmi_exception) 804 ppc_md.handle_hmi_exception(regs); 805 806 irq_exit(); 807 set_irq_regs(old_regs); 808 } 809 810 void unknown_exception(struct pt_regs *regs) 811 { 812 enum ctx_state prev_state = exception_enter(); 813 814 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 815 regs->nip, regs->msr, regs->trap); 816 817 _exception(SIGTRAP, regs, 0, 0); 818 819 exception_exit(prev_state); 820 } 821 822 void instruction_breakpoint_exception(struct pt_regs *regs) 823 { 824 enum ctx_state prev_state = exception_enter(); 825 826 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 827 5, SIGTRAP) == NOTIFY_STOP) 828 goto bail; 829 if (debugger_iabr_match(regs)) 830 goto bail; 831 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 832 833 bail: 834 exception_exit(prev_state); 835 } 836 837 void RunModeException(struct pt_regs *regs) 838 { 839 _exception(SIGTRAP, regs, 0, 0); 840 } 841 842 void single_step_exception(struct pt_regs *regs) 843 { 844 enum ctx_state prev_state = exception_enter(); 845 846 clear_single_step(regs); 847 848 if (kprobe_post_handler(regs)) 849 return; 850 851 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 852 5, SIGTRAP) == NOTIFY_STOP) 853 goto bail; 854 if (debugger_sstep(regs)) 855 goto bail; 856 857 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 858 859 bail: 860 exception_exit(prev_state); 861 } 862 NOKPROBE_SYMBOL(single_step_exception); 863 864 /* 865 * After we have successfully emulated an instruction, we have to 866 * check if the instruction was being single-stepped, and if so, 867 * pretend we got a single-step exception. This was pointed out 868 * by Kumar Gala. -- paulus 869 */ 870 static void emulate_single_step(struct pt_regs *regs) 871 { 872 if (single_stepping(regs)) 873 single_step_exception(regs); 874 } 875 876 static inline int __parse_fpscr(unsigned long fpscr) 877 { 878 int ret = 0; 879 880 /* Invalid operation */ 881 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 882 ret = FPE_FLTINV; 883 884 /* Overflow */ 885 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 886 ret = FPE_FLTOVF; 887 888 /* Underflow */ 889 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 890 ret = FPE_FLTUND; 891 892 /* Divide by zero */ 893 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 894 ret = FPE_FLTDIV; 895 896 /* Inexact result */ 897 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 898 ret = FPE_FLTRES; 899 900 return ret; 901 } 902 903 static void parse_fpe(struct pt_regs *regs) 904 { 905 int code = 0; 906 907 flush_fp_to_thread(current); 908 909 code = __parse_fpscr(current->thread.fp_state.fpscr); 910 911 _exception(SIGFPE, regs, code, regs->nip); 912 } 913 914 /* 915 * Illegal instruction emulation support. Originally written to 916 * provide the PVR to user applications using the mfspr rd, PVR. 917 * Return non-zero if we can't emulate, or -EFAULT if the associated 918 * memory access caused an access fault. Return zero on success. 919 * 920 * There are a couple of ways to do this, either "decode" the instruction 921 * or directly match lots of bits. In this case, matching lots of 922 * bits is faster and easier. 923 * 924 */ 925 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 926 { 927 u8 rT = (instword >> 21) & 0x1f; 928 u8 rA = (instword >> 16) & 0x1f; 929 u8 NB_RB = (instword >> 11) & 0x1f; 930 u32 num_bytes; 931 unsigned long EA; 932 int pos = 0; 933 934 /* Early out if we are an invalid form of lswx */ 935 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 936 if ((rT == rA) || (rT == NB_RB)) 937 return -EINVAL; 938 939 EA = (rA == 0) ? 0 : regs->gpr[rA]; 940 941 switch (instword & PPC_INST_STRING_MASK) { 942 case PPC_INST_LSWX: 943 case PPC_INST_STSWX: 944 EA += NB_RB; 945 num_bytes = regs->xer & 0x7f; 946 break; 947 case PPC_INST_LSWI: 948 case PPC_INST_STSWI: 949 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 950 break; 951 default: 952 return -EINVAL; 953 } 954 955 while (num_bytes != 0) 956 { 957 u8 val; 958 u32 shift = 8 * (3 - (pos & 0x3)); 959 960 /* if process is 32-bit, clear upper 32 bits of EA */ 961 if ((regs->msr & MSR_64BIT) == 0) 962 EA &= 0xFFFFFFFF; 963 964 switch ((instword & PPC_INST_STRING_MASK)) { 965 case PPC_INST_LSWX: 966 case PPC_INST_LSWI: 967 if (get_user(val, (u8 __user *)EA)) 968 return -EFAULT; 969 /* first time updating this reg, 970 * zero it out */ 971 if (pos == 0) 972 regs->gpr[rT] = 0; 973 regs->gpr[rT] |= val << shift; 974 break; 975 case PPC_INST_STSWI: 976 case PPC_INST_STSWX: 977 val = regs->gpr[rT] >> shift; 978 if (put_user(val, (u8 __user *)EA)) 979 return -EFAULT; 980 break; 981 } 982 /* move EA to next address */ 983 EA += 1; 984 num_bytes--; 985 986 /* manage our position within the register */ 987 if (++pos == 4) { 988 pos = 0; 989 if (++rT == 32) 990 rT = 0; 991 } 992 } 993 994 return 0; 995 } 996 997 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 998 { 999 u32 ra,rs; 1000 unsigned long tmp; 1001 1002 ra = (instword >> 16) & 0x1f; 1003 rs = (instword >> 21) & 0x1f; 1004 1005 tmp = regs->gpr[rs]; 1006 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1007 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1008 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1009 regs->gpr[ra] = tmp; 1010 1011 return 0; 1012 } 1013 1014 static int emulate_isel(struct pt_regs *regs, u32 instword) 1015 { 1016 u8 rT = (instword >> 21) & 0x1f; 1017 u8 rA = (instword >> 16) & 0x1f; 1018 u8 rB = (instword >> 11) & 0x1f; 1019 u8 BC = (instword >> 6) & 0x1f; 1020 u8 bit; 1021 unsigned long tmp; 1022 1023 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1024 bit = (regs->ccr >> (31 - BC)) & 0x1; 1025 1026 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1027 1028 return 0; 1029 } 1030 1031 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1032 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1033 { 1034 /* If we're emulating a load/store in an active transaction, we cannot 1035 * emulate it as the kernel operates in transaction suspended context. 1036 * We need to abort the transaction. This creates a persistent TM 1037 * abort so tell the user what caused it with a new code. 1038 */ 1039 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1040 tm_enable(); 1041 tm_abort(cause); 1042 return true; 1043 } 1044 return false; 1045 } 1046 #else 1047 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1048 { 1049 return false; 1050 } 1051 #endif 1052 1053 static int emulate_instruction(struct pt_regs *regs) 1054 { 1055 u32 instword; 1056 u32 rd; 1057 1058 if (!user_mode(regs)) 1059 return -EINVAL; 1060 CHECK_FULL_REGS(regs); 1061 1062 if (get_user(instword, (u32 __user *)(regs->nip))) 1063 return -EFAULT; 1064 1065 /* Emulate the mfspr rD, PVR. */ 1066 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1067 PPC_WARN_EMULATED(mfpvr, regs); 1068 rd = (instword >> 21) & 0x1f; 1069 regs->gpr[rd] = mfspr(SPRN_PVR); 1070 return 0; 1071 } 1072 1073 /* Emulating the dcba insn is just a no-op. */ 1074 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1075 PPC_WARN_EMULATED(dcba, regs); 1076 return 0; 1077 } 1078 1079 /* Emulate the mcrxr insn. */ 1080 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1081 int shift = (instword >> 21) & 0x1c; 1082 unsigned long msk = 0xf0000000UL >> shift; 1083 1084 PPC_WARN_EMULATED(mcrxr, regs); 1085 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1086 regs->xer &= ~0xf0000000UL; 1087 return 0; 1088 } 1089 1090 /* Emulate load/store string insn. */ 1091 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1092 if (tm_abort_check(regs, 1093 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1094 return -EINVAL; 1095 PPC_WARN_EMULATED(string, regs); 1096 return emulate_string_inst(regs, instword); 1097 } 1098 1099 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1100 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1101 PPC_WARN_EMULATED(popcntb, regs); 1102 return emulate_popcntb_inst(regs, instword); 1103 } 1104 1105 /* Emulate isel (Integer Select) instruction */ 1106 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1107 PPC_WARN_EMULATED(isel, regs); 1108 return emulate_isel(regs, instword); 1109 } 1110 1111 /* Emulate sync instruction variants */ 1112 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1113 PPC_WARN_EMULATED(sync, regs); 1114 asm volatile("sync"); 1115 return 0; 1116 } 1117 1118 #ifdef CONFIG_PPC64 1119 /* Emulate the mfspr rD, DSCR. */ 1120 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1121 PPC_INST_MFSPR_DSCR_USER) || 1122 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1123 PPC_INST_MFSPR_DSCR)) && 1124 cpu_has_feature(CPU_FTR_DSCR)) { 1125 PPC_WARN_EMULATED(mfdscr, regs); 1126 rd = (instword >> 21) & 0x1f; 1127 regs->gpr[rd] = mfspr(SPRN_DSCR); 1128 return 0; 1129 } 1130 /* Emulate the mtspr DSCR, rD. */ 1131 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1132 PPC_INST_MTSPR_DSCR_USER) || 1133 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1134 PPC_INST_MTSPR_DSCR)) && 1135 cpu_has_feature(CPU_FTR_DSCR)) { 1136 PPC_WARN_EMULATED(mtdscr, regs); 1137 rd = (instword >> 21) & 0x1f; 1138 current->thread.dscr = regs->gpr[rd]; 1139 current->thread.dscr_inherit = 1; 1140 mtspr(SPRN_DSCR, current->thread.dscr); 1141 return 0; 1142 } 1143 #endif 1144 1145 return -EINVAL; 1146 } 1147 1148 int is_valid_bugaddr(unsigned long addr) 1149 { 1150 return is_kernel_addr(addr); 1151 } 1152 1153 #ifdef CONFIG_MATH_EMULATION 1154 static int emulate_math(struct pt_regs *regs) 1155 { 1156 int ret; 1157 extern int do_mathemu(struct pt_regs *regs); 1158 1159 ret = do_mathemu(regs); 1160 if (ret >= 0) 1161 PPC_WARN_EMULATED(math, regs); 1162 1163 switch (ret) { 1164 case 0: 1165 emulate_single_step(regs); 1166 return 0; 1167 case 1: { 1168 int code = 0; 1169 code = __parse_fpscr(current->thread.fp_state.fpscr); 1170 _exception(SIGFPE, regs, code, regs->nip); 1171 return 0; 1172 } 1173 case -EFAULT: 1174 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1175 return 0; 1176 } 1177 1178 return -1; 1179 } 1180 #else 1181 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1182 #endif 1183 1184 void program_check_exception(struct pt_regs *regs) 1185 { 1186 enum ctx_state prev_state = exception_enter(); 1187 unsigned int reason = get_reason(regs); 1188 1189 /* We can now get here via a FP Unavailable exception if the core 1190 * has no FPU, in that case the reason flags will be 0 */ 1191 1192 if (reason & REASON_FP) { 1193 /* IEEE FP exception */ 1194 parse_fpe(regs); 1195 goto bail; 1196 } 1197 if (reason & REASON_TRAP) { 1198 unsigned long bugaddr; 1199 /* Debugger is first in line to stop recursive faults in 1200 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1201 if (debugger_bpt(regs)) 1202 goto bail; 1203 1204 if (kprobe_handler(regs)) 1205 goto bail; 1206 1207 /* trap exception */ 1208 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1209 == NOTIFY_STOP) 1210 goto bail; 1211 1212 bugaddr = regs->nip; 1213 /* 1214 * Fixup bugaddr for BUG_ON() in real mode 1215 */ 1216 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1217 bugaddr += PAGE_OFFSET; 1218 1219 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1220 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1221 regs->nip += 4; 1222 goto bail; 1223 } 1224 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1225 goto bail; 1226 } 1227 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1228 if (reason & REASON_TM) { 1229 /* This is a TM "Bad Thing Exception" program check. 1230 * This occurs when: 1231 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1232 * transition in TM states. 1233 * - A trechkpt is attempted when transactional. 1234 * - A treclaim is attempted when non transactional. 1235 * - A tend is illegally attempted. 1236 * - writing a TM SPR when transactional. 1237 */ 1238 if (!user_mode(regs) && 1239 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1240 regs->nip += 4; 1241 goto bail; 1242 } 1243 /* If usermode caused this, it's done something illegal and 1244 * gets a SIGILL slap on the wrist. We call it an illegal 1245 * operand to distinguish from the instruction just being bad 1246 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1247 * illegal /placement/ of a valid instruction. 1248 */ 1249 if (user_mode(regs)) { 1250 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1251 goto bail; 1252 } else { 1253 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1254 "at %lx (msr 0x%x)\n", regs->nip, reason); 1255 die("Unrecoverable exception", regs, SIGABRT); 1256 } 1257 } 1258 #endif 1259 1260 /* 1261 * If we took the program check in the kernel skip down to sending a 1262 * SIGILL. The subsequent cases all relate to emulating instructions 1263 * which we should only do for userspace. We also do not want to enable 1264 * interrupts for kernel faults because that might lead to further 1265 * faults, and loose the context of the original exception. 1266 */ 1267 if (!user_mode(regs)) 1268 goto sigill; 1269 1270 /* We restore the interrupt state now */ 1271 if (!arch_irq_disabled_regs(regs)) 1272 local_irq_enable(); 1273 1274 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1275 * but there seems to be a hardware bug on the 405GP (RevD) 1276 * that means ESR is sometimes set incorrectly - either to 1277 * ESR_DST (!?) or 0. In the process of chasing this with the 1278 * hardware people - not sure if it can happen on any illegal 1279 * instruction or only on FP instructions, whether there is a 1280 * pattern to occurrences etc. -dgibson 31/Mar/2003 1281 */ 1282 if (!emulate_math(regs)) 1283 goto bail; 1284 1285 /* Try to emulate it if we should. */ 1286 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1287 switch (emulate_instruction(regs)) { 1288 case 0: 1289 regs->nip += 4; 1290 emulate_single_step(regs); 1291 goto bail; 1292 case -EFAULT: 1293 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1294 goto bail; 1295 } 1296 } 1297 1298 sigill: 1299 if (reason & REASON_PRIVILEGED) 1300 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1301 else 1302 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1303 1304 bail: 1305 exception_exit(prev_state); 1306 } 1307 NOKPROBE_SYMBOL(program_check_exception); 1308 1309 /* 1310 * This occurs when running in hypervisor mode on POWER6 or later 1311 * and an illegal instruction is encountered. 1312 */ 1313 void emulation_assist_interrupt(struct pt_regs *regs) 1314 { 1315 regs->msr |= REASON_ILLEGAL; 1316 program_check_exception(regs); 1317 } 1318 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1319 1320 void alignment_exception(struct pt_regs *regs) 1321 { 1322 enum ctx_state prev_state = exception_enter(); 1323 int sig, code, fixed = 0; 1324 1325 /* We restore the interrupt state now */ 1326 if (!arch_irq_disabled_regs(regs)) 1327 local_irq_enable(); 1328 1329 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1330 goto bail; 1331 1332 /* we don't implement logging of alignment exceptions */ 1333 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1334 fixed = fix_alignment(regs); 1335 1336 if (fixed == 1) { 1337 regs->nip += 4; /* skip over emulated instruction */ 1338 emulate_single_step(regs); 1339 goto bail; 1340 } 1341 1342 /* Operand address was bad */ 1343 if (fixed == -EFAULT) { 1344 sig = SIGSEGV; 1345 code = SEGV_ACCERR; 1346 } else { 1347 sig = SIGBUS; 1348 code = BUS_ADRALN; 1349 } 1350 if (user_mode(regs)) 1351 _exception(sig, regs, code, regs->dar); 1352 else 1353 bad_page_fault(regs, regs->dar, sig); 1354 1355 bail: 1356 exception_exit(prev_state); 1357 } 1358 1359 void slb_miss_bad_addr(struct pt_regs *regs) 1360 { 1361 enum ctx_state prev_state = exception_enter(); 1362 1363 if (user_mode(regs)) 1364 _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); 1365 else 1366 bad_page_fault(regs, regs->dar, SIGSEGV); 1367 1368 exception_exit(prev_state); 1369 } 1370 1371 void StackOverflow(struct pt_regs *regs) 1372 { 1373 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1374 current, regs->gpr[1]); 1375 debugger(regs); 1376 show_regs(regs); 1377 panic("kernel stack overflow"); 1378 } 1379 1380 void nonrecoverable_exception(struct pt_regs *regs) 1381 { 1382 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1383 regs->nip, regs->msr); 1384 debugger(regs); 1385 die("nonrecoverable exception", regs, SIGKILL); 1386 } 1387 1388 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1389 { 1390 enum ctx_state prev_state = exception_enter(); 1391 1392 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1393 "%lx at %lx\n", regs->trap, regs->nip); 1394 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1395 1396 exception_exit(prev_state); 1397 } 1398 1399 void altivec_unavailable_exception(struct pt_regs *regs) 1400 { 1401 enum ctx_state prev_state = exception_enter(); 1402 1403 if (user_mode(regs)) { 1404 /* A user program has executed an altivec instruction, 1405 but this kernel doesn't support altivec. */ 1406 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1407 goto bail; 1408 } 1409 1410 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1411 "%lx at %lx\n", regs->trap, regs->nip); 1412 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1413 1414 bail: 1415 exception_exit(prev_state); 1416 } 1417 1418 void vsx_unavailable_exception(struct pt_regs *regs) 1419 { 1420 if (user_mode(regs)) { 1421 /* A user program has executed an vsx instruction, 1422 but this kernel doesn't support vsx. */ 1423 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1424 return; 1425 } 1426 1427 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1428 "%lx at %lx\n", regs->trap, regs->nip); 1429 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1430 } 1431 1432 #ifdef CONFIG_PPC64 1433 static void tm_unavailable(struct pt_regs *regs) 1434 { 1435 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1436 if (user_mode(regs)) { 1437 current->thread.load_tm++; 1438 regs->msr |= MSR_TM; 1439 tm_enable(); 1440 tm_restore_sprs(¤t->thread); 1441 return; 1442 } 1443 #endif 1444 pr_emerg("Unrecoverable TM Unavailable Exception " 1445 "%lx at %lx\n", regs->trap, regs->nip); 1446 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1447 } 1448 1449 void facility_unavailable_exception(struct pt_regs *regs) 1450 { 1451 static char *facility_strings[] = { 1452 [FSCR_FP_LG] = "FPU", 1453 [FSCR_VECVSX_LG] = "VMX/VSX", 1454 [FSCR_DSCR_LG] = "DSCR", 1455 [FSCR_PM_LG] = "PMU SPRs", 1456 [FSCR_BHRB_LG] = "BHRB", 1457 [FSCR_TM_LG] = "TM", 1458 [FSCR_EBB_LG] = "EBB", 1459 [FSCR_TAR_LG] = "TAR", 1460 [FSCR_MSGP_LG] = "MSGP", 1461 [FSCR_SCV_LG] = "SCV", 1462 }; 1463 char *facility = "unknown"; 1464 u64 value; 1465 u32 instword, rd; 1466 u8 status; 1467 bool hv; 1468 1469 hv = (regs->trap == 0xf80); 1470 if (hv) 1471 value = mfspr(SPRN_HFSCR); 1472 else 1473 value = mfspr(SPRN_FSCR); 1474 1475 status = value >> 56; 1476 if (status == FSCR_DSCR_LG) { 1477 /* 1478 * User is accessing the DSCR register using the problem 1479 * state only SPR number (0x03) either through a mfspr or 1480 * a mtspr instruction. If it is a write attempt through 1481 * a mtspr, then we set the inherit bit. This also allows 1482 * the user to write or read the register directly in the 1483 * future by setting via the FSCR DSCR bit. But in case it 1484 * is a read DSCR attempt through a mfspr instruction, we 1485 * just emulate the instruction instead. This code path will 1486 * always emulate all the mfspr instructions till the user 1487 * has attempted at least one mtspr instruction. This way it 1488 * preserves the same behaviour when the user is accessing 1489 * the DSCR through privilege level only SPR number (0x11) 1490 * which is emulated through illegal instruction exception. 1491 * We always leave HFSCR DSCR set. 1492 */ 1493 if (get_user(instword, (u32 __user *)(regs->nip))) { 1494 pr_err("Failed to fetch the user instruction\n"); 1495 return; 1496 } 1497 1498 /* Write into DSCR (mtspr 0x03, RS) */ 1499 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1500 == PPC_INST_MTSPR_DSCR_USER) { 1501 rd = (instword >> 21) & 0x1f; 1502 current->thread.dscr = regs->gpr[rd]; 1503 current->thread.dscr_inherit = 1; 1504 current->thread.fscr |= FSCR_DSCR; 1505 mtspr(SPRN_FSCR, current->thread.fscr); 1506 } 1507 1508 /* Read from DSCR (mfspr RT, 0x03) */ 1509 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1510 == PPC_INST_MFSPR_DSCR_USER) { 1511 if (emulate_instruction(regs)) { 1512 pr_err("DSCR based mfspr emulation failed\n"); 1513 return; 1514 } 1515 regs->nip += 4; 1516 emulate_single_step(regs); 1517 } 1518 return; 1519 } 1520 1521 if (status == FSCR_TM_LG) { 1522 /* 1523 * If we're here then the hardware is TM aware because it 1524 * generated an exception with FSRM_TM set. 1525 * 1526 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1527 * told us not to do TM, or the kernel is not built with TM 1528 * support. 1529 * 1530 * If both of those things are true, then userspace can spam the 1531 * console by triggering the printk() below just by continually 1532 * doing tbegin (or any TM instruction). So in that case just 1533 * send the process a SIGILL immediately. 1534 */ 1535 if (!cpu_has_feature(CPU_FTR_TM)) 1536 goto out; 1537 1538 tm_unavailable(regs); 1539 return; 1540 } 1541 1542 if ((hv || status >= 2) && 1543 (status < ARRAY_SIZE(facility_strings)) && 1544 facility_strings[status]) 1545 facility = facility_strings[status]; 1546 1547 /* We restore the interrupt state now */ 1548 if (!arch_irq_disabled_regs(regs)) 1549 local_irq_enable(); 1550 1551 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1552 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1553 1554 out: 1555 if (user_mode(regs)) { 1556 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1557 return; 1558 } 1559 1560 die("Unexpected facility unavailable exception", regs, SIGABRT); 1561 } 1562 #endif 1563 1564 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1565 1566 void fp_unavailable_tm(struct pt_regs *regs) 1567 { 1568 /* Note: This does not handle any kind of FP laziness. */ 1569 1570 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1571 regs->nip, regs->msr); 1572 1573 /* We can only have got here if the task started using FP after 1574 * beginning the transaction. So, the transactional regs are just a 1575 * copy of the checkpointed ones. But, we still need to recheckpoint 1576 * as we're enabling FP for the process; it will return, abort the 1577 * transaction, and probably retry but now with FP enabled. So the 1578 * checkpointed FP registers need to be loaded. 1579 */ 1580 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1581 /* Reclaim didn't save out any FPRs to transact_fprs. */ 1582 1583 /* Enable FP for the task: */ 1584 regs->msr |= (MSR_FP | current->thread.fpexc_mode); 1585 1586 /* This loads and recheckpoints the FP registers from 1587 * thread.fpr[]. They will remain in registers after the 1588 * checkpoint so we don't need to reload them after. 1589 * If VMX is in use, the VRs now hold checkpointed values, 1590 * so we don't want to load the VRs from the thread_struct. 1591 */ 1592 tm_recheckpoint(¤t->thread, MSR_FP); 1593 1594 /* If VMX is in use, get the transactional values back */ 1595 if (regs->msr & MSR_VEC) { 1596 msr_check_and_set(MSR_VEC); 1597 load_vr_state(¤t->thread.vr_state); 1598 /* At this point all the VSX state is loaded, so enable it */ 1599 regs->msr |= MSR_VSX; 1600 } 1601 } 1602 1603 void altivec_unavailable_tm(struct pt_regs *regs) 1604 { 1605 /* See the comments in fp_unavailable_tm(). This function operates 1606 * the same way. 1607 */ 1608 1609 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1610 "MSR=%lx\n", 1611 regs->nip, regs->msr); 1612 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1613 regs->msr |= MSR_VEC; 1614 tm_recheckpoint(¤t->thread, MSR_VEC); 1615 current->thread.used_vr = 1; 1616 1617 if (regs->msr & MSR_FP) { 1618 msr_check_and_set(MSR_FP); 1619 load_fp_state(¤t->thread.fp_state); 1620 regs->msr |= MSR_VSX; 1621 } 1622 } 1623 1624 void vsx_unavailable_tm(struct pt_regs *regs) 1625 { 1626 unsigned long orig_msr = regs->msr; 1627 1628 /* See the comments in fp_unavailable_tm(). This works similarly, 1629 * though we're loading both FP and VEC registers in here. 1630 * 1631 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1632 * regs. Either way, set MSR_VSX. 1633 */ 1634 1635 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1636 "MSR=%lx\n", 1637 regs->nip, regs->msr); 1638 1639 current->thread.used_vsr = 1; 1640 1641 /* If FP and VMX are already loaded, we have all the state we need */ 1642 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) { 1643 regs->msr |= MSR_VSX; 1644 return; 1645 } 1646 1647 /* This reclaims FP and/or VR regs if they're already enabled */ 1648 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1649 1650 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | 1651 MSR_VSX; 1652 1653 /* This loads & recheckpoints FP and VRs; but we have 1654 * to be sure not to overwrite previously-valid state. 1655 */ 1656 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr); 1657 1658 msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC)); 1659 1660 if (orig_msr & MSR_FP) 1661 load_fp_state(¤t->thread.fp_state); 1662 if (orig_msr & MSR_VEC) 1663 load_vr_state(¤t->thread.vr_state); 1664 } 1665 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1666 1667 void performance_monitor_exception(struct pt_regs *regs) 1668 { 1669 __this_cpu_inc(irq_stat.pmu_irqs); 1670 1671 perf_irq(regs); 1672 } 1673 1674 #ifdef CONFIG_8xx 1675 void SoftwareEmulation(struct pt_regs *regs) 1676 { 1677 CHECK_FULL_REGS(regs); 1678 1679 if (!user_mode(regs)) { 1680 debugger(regs); 1681 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation", 1682 regs, SIGFPE); 1683 } 1684 1685 if (!emulate_math(regs)) 1686 return; 1687 1688 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1689 } 1690 #endif /* CONFIG_8xx */ 1691 1692 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1693 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1694 { 1695 int changed = 0; 1696 /* 1697 * Determine the cause of the debug event, clear the 1698 * event flags and send a trap to the handler. Torez 1699 */ 1700 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1701 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1702 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1703 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1704 #endif 1705 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1706 5); 1707 changed |= 0x01; 1708 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1709 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1710 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1711 6); 1712 changed |= 0x01; 1713 } else if (debug_status & DBSR_IAC1) { 1714 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1715 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1716 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1717 1); 1718 changed |= 0x01; 1719 } else if (debug_status & DBSR_IAC2) { 1720 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1721 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1722 2); 1723 changed |= 0x01; 1724 } else if (debug_status & DBSR_IAC3) { 1725 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1726 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1727 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1728 3); 1729 changed |= 0x01; 1730 } else if (debug_status & DBSR_IAC4) { 1731 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1732 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1733 4); 1734 changed |= 0x01; 1735 } 1736 /* 1737 * At the point this routine was called, the MSR(DE) was turned off. 1738 * Check all other debug flags and see if that bit needs to be turned 1739 * back on or not. 1740 */ 1741 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1742 current->thread.debug.dbcr1)) 1743 regs->msr |= MSR_DE; 1744 else 1745 /* Make sure the IDM flag is off */ 1746 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1747 1748 if (changed & 0x01) 1749 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1750 } 1751 1752 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1753 { 1754 current->thread.debug.dbsr = debug_status; 1755 1756 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1757 * on server, it stops on the target of the branch. In order to simulate 1758 * the server behaviour, we thus restart right away with a single step 1759 * instead of stopping here when hitting a BT 1760 */ 1761 if (debug_status & DBSR_BT) { 1762 regs->msr &= ~MSR_DE; 1763 1764 /* Disable BT */ 1765 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1766 /* Clear the BT event */ 1767 mtspr(SPRN_DBSR, DBSR_BT); 1768 1769 /* Do the single step trick only when coming from userspace */ 1770 if (user_mode(regs)) { 1771 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1772 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1773 regs->msr |= MSR_DE; 1774 return; 1775 } 1776 1777 if (kprobe_post_handler(regs)) 1778 return; 1779 1780 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1781 5, SIGTRAP) == NOTIFY_STOP) { 1782 return; 1783 } 1784 if (debugger_sstep(regs)) 1785 return; 1786 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1787 regs->msr &= ~MSR_DE; 1788 1789 /* Disable instruction completion */ 1790 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1791 /* Clear the instruction completion event */ 1792 mtspr(SPRN_DBSR, DBSR_IC); 1793 1794 if (kprobe_post_handler(regs)) 1795 return; 1796 1797 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1798 5, SIGTRAP) == NOTIFY_STOP) { 1799 return; 1800 } 1801 1802 if (debugger_sstep(regs)) 1803 return; 1804 1805 if (user_mode(regs)) { 1806 current->thread.debug.dbcr0 &= ~DBCR0_IC; 1807 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1808 current->thread.debug.dbcr1)) 1809 regs->msr |= MSR_DE; 1810 else 1811 /* Make sure the IDM bit is off */ 1812 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1813 } 1814 1815 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1816 } else 1817 handle_debug(regs, debug_status); 1818 } 1819 NOKPROBE_SYMBOL(DebugException); 1820 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1821 1822 #if !defined(CONFIG_TAU_INT) 1823 void TAUException(struct pt_regs *regs) 1824 { 1825 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1826 regs->nip, regs->msr, regs->trap, print_tainted()); 1827 } 1828 #endif /* CONFIG_INT_TAU */ 1829 1830 #ifdef CONFIG_ALTIVEC 1831 void altivec_assist_exception(struct pt_regs *regs) 1832 { 1833 int err; 1834 1835 if (!user_mode(regs)) { 1836 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1837 " at %lx\n", regs->nip); 1838 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1839 } 1840 1841 flush_altivec_to_thread(current); 1842 1843 PPC_WARN_EMULATED(altivec, regs); 1844 err = emulate_altivec(regs); 1845 if (err == 0) { 1846 regs->nip += 4; /* skip emulated instruction */ 1847 emulate_single_step(regs); 1848 return; 1849 } 1850 1851 if (err == -EFAULT) { 1852 /* got an error reading the instruction */ 1853 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1854 } else { 1855 /* didn't recognize the instruction */ 1856 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1857 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 1858 "in %s at %lx\n", current->comm, regs->nip); 1859 current->thread.vr_state.vscr.u[3] |= 0x10000; 1860 } 1861 } 1862 #endif /* CONFIG_ALTIVEC */ 1863 1864 #ifdef CONFIG_FSL_BOOKE 1865 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1866 unsigned long error_code) 1867 { 1868 /* We treat cache locking instructions from the user 1869 * as priv ops, in the future we could try to do 1870 * something smarter 1871 */ 1872 if (error_code & (ESR_DLK|ESR_ILK)) 1873 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1874 return; 1875 } 1876 #endif /* CONFIG_FSL_BOOKE */ 1877 1878 #ifdef CONFIG_SPE 1879 void SPEFloatingPointException(struct pt_regs *regs) 1880 { 1881 extern int do_spe_mathemu(struct pt_regs *regs); 1882 unsigned long spefscr; 1883 int fpexc_mode; 1884 int code = 0; 1885 int err; 1886 1887 flush_spe_to_thread(current); 1888 1889 spefscr = current->thread.spefscr; 1890 fpexc_mode = current->thread.fpexc_mode; 1891 1892 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1893 code = FPE_FLTOVF; 1894 } 1895 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1896 code = FPE_FLTUND; 1897 } 1898 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1899 code = FPE_FLTDIV; 1900 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1901 code = FPE_FLTINV; 1902 } 1903 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1904 code = FPE_FLTRES; 1905 1906 err = do_spe_mathemu(regs); 1907 if (err == 0) { 1908 regs->nip += 4; /* skip emulated instruction */ 1909 emulate_single_step(regs); 1910 return; 1911 } 1912 1913 if (err == -EFAULT) { 1914 /* got an error reading the instruction */ 1915 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1916 } else if (err == -EINVAL) { 1917 /* didn't recognize the instruction */ 1918 printk(KERN_ERR "unrecognized spe instruction " 1919 "in %s at %lx\n", current->comm, regs->nip); 1920 } else { 1921 _exception(SIGFPE, regs, code, regs->nip); 1922 } 1923 1924 return; 1925 } 1926 1927 void SPEFloatingPointRoundException(struct pt_regs *regs) 1928 { 1929 extern int speround_handler(struct pt_regs *regs); 1930 int err; 1931 1932 preempt_disable(); 1933 if (regs->msr & MSR_SPE) 1934 giveup_spe(current); 1935 preempt_enable(); 1936 1937 regs->nip -= 4; 1938 err = speround_handler(regs); 1939 if (err == 0) { 1940 regs->nip += 4; /* skip emulated instruction */ 1941 emulate_single_step(regs); 1942 return; 1943 } 1944 1945 if (err == -EFAULT) { 1946 /* got an error reading the instruction */ 1947 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1948 } else if (err == -EINVAL) { 1949 /* didn't recognize the instruction */ 1950 printk(KERN_ERR "unrecognized spe instruction " 1951 "in %s at %lx\n", current->comm, regs->nip); 1952 } else { 1953 _exception(SIGFPE, regs, 0, regs->nip); 1954 return; 1955 } 1956 } 1957 #endif 1958 1959 /* 1960 * We enter here if we get an unrecoverable exception, that is, one 1961 * that happened at a point where the RI (recoverable interrupt) bit 1962 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1963 * we therefore lost state by taking this exception. 1964 */ 1965 void unrecoverable_exception(struct pt_regs *regs) 1966 { 1967 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1968 regs->trap, regs->nip); 1969 die("Unrecoverable exception", regs, SIGABRT); 1970 } 1971 1972 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 1973 /* 1974 * Default handler for a Watchdog exception, 1975 * spins until a reboot occurs 1976 */ 1977 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1978 { 1979 /* Generic WatchdogHandler, implement your own */ 1980 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1981 return; 1982 } 1983 1984 void WatchdogException(struct pt_regs *regs) 1985 { 1986 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1987 WatchdogHandler(regs); 1988 } 1989 #endif 1990 1991 /* 1992 * We enter here if we discover during exception entry that we are 1993 * running in supervisor mode with a userspace value in the stack pointer. 1994 */ 1995 void kernel_bad_stack(struct pt_regs *regs) 1996 { 1997 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1998 regs->gpr[1], regs->nip); 1999 die("Bad kernel stack pointer", regs, SIGABRT); 2000 } 2001 2002 void __init trap_init(void) 2003 { 2004 } 2005 2006 2007 #ifdef CONFIG_PPC_EMULATED_STATS 2008 2009 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2010 2011 struct ppc_emulated ppc_emulated = { 2012 #ifdef CONFIG_ALTIVEC 2013 WARN_EMULATED_SETUP(altivec), 2014 #endif 2015 WARN_EMULATED_SETUP(dcba), 2016 WARN_EMULATED_SETUP(dcbz), 2017 WARN_EMULATED_SETUP(fp_pair), 2018 WARN_EMULATED_SETUP(isel), 2019 WARN_EMULATED_SETUP(mcrxr), 2020 WARN_EMULATED_SETUP(mfpvr), 2021 WARN_EMULATED_SETUP(multiple), 2022 WARN_EMULATED_SETUP(popcntb), 2023 WARN_EMULATED_SETUP(spe), 2024 WARN_EMULATED_SETUP(string), 2025 WARN_EMULATED_SETUP(sync), 2026 WARN_EMULATED_SETUP(unaligned), 2027 #ifdef CONFIG_MATH_EMULATION 2028 WARN_EMULATED_SETUP(math), 2029 #endif 2030 #ifdef CONFIG_VSX 2031 WARN_EMULATED_SETUP(vsx), 2032 #endif 2033 #ifdef CONFIG_PPC64 2034 WARN_EMULATED_SETUP(mfdscr), 2035 WARN_EMULATED_SETUP(mtdscr), 2036 WARN_EMULATED_SETUP(lq_stq), 2037 #endif 2038 }; 2039 2040 u32 ppc_warn_emulated; 2041 2042 void ppc_warn_emulated_print(const char *type) 2043 { 2044 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2045 type); 2046 } 2047 2048 static int __init ppc_warn_emulated_init(void) 2049 { 2050 struct dentry *dir, *d; 2051 unsigned int i; 2052 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2053 2054 if (!powerpc_debugfs_root) 2055 return -ENODEV; 2056 2057 dir = debugfs_create_dir("emulated_instructions", 2058 powerpc_debugfs_root); 2059 if (!dir) 2060 return -ENOMEM; 2061 2062 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 2063 &ppc_warn_emulated); 2064 if (!d) 2065 goto fail; 2066 2067 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 2068 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 2069 (u32 *)&entries[i].val.counter); 2070 if (!d) 2071 goto fail; 2072 } 2073 2074 return 0; 2075 2076 fail: 2077 debugfs_remove_recursive(dir); 2078 return -ENOMEM; 2079 } 2080 2081 device_initcall(ppc_warn_emulated_init); 2082 2083 #endif /* CONFIG_PPC_EMULATED_STATS */ 2084