1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/sched/debug.h> 21 #include <linux/kernel.h> 22 #include <linux/mm.h> 23 #include <linux/pkeys.h> 24 #include <linux/stddef.h> 25 #include <linux/unistd.h> 26 #include <linux/ptrace.h> 27 #include <linux/user.h> 28 #include <linux/interrupt.h> 29 #include <linux/init.h> 30 #include <linux/extable.h> 31 #include <linux/module.h> /* print_modules */ 32 #include <linux/prctl.h> 33 #include <linux/delay.h> 34 #include <linux/kprobes.h> 35 #include <linux/kexec.h> 36 #include <linux/backlight.h> 37 #include <linux/bug.h> 38 #include <linux/kdebug.h> 39 #include <linux/ratelimit.h> 40 #include <linux/context_tracking.h> 41 #include <linux/smp.h> 42 #include <linux/console.h> 43 #include <linux/kmsg_dump.h> 44 45 #include <asm/emulated_ops.h> 46 #include <asm/pgtable.h> 47 #include <linux/uaccess.h> 48 #include <asm/debugfs.h> 49 #include <asm/io.h> 50 #include <asm/machdep.h> 51 #include <asm/rtas.h> 52 #include <asm/pmc.h> 53 #include <asm/reg.h> 54 #ifdef CONFIG_PMAC_BACKLIGHT 55 #include <asm/backlight.h> 56 #endif 57 #ifdef CONFIG_PPC64 58 #include <asm/firmware.h> 59 #include <asm/processor.h> 60 #include <asm/tm.h> 61 #endif 62 #include <asm/kexec.h> 63 #include <asm/ppc-opcode.h> 64 #include <asm/rio.h> 65 #include <asm/fadump.h> 66 #include <asm/switch_to.h> 67 #include <asm/tm.h> 68 #include <asm/debug.h> 69 #include <asm/asm-prototypes.h> 70 #include <asm/hmi.h> 71 #include <sysdev/fsl_pci.h> 72 #include <asm/kprobes.h> 73 #include <asm/stacktrace.h> 74 75 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 76 int (*__debugger)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 80 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 81 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 82 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 83 84 EXPORT_SYMBOL(__debugger); 85 EXPORT_SYMBOL(__debugger_ipi); 86 EXPORT_SYMBOL(__debugger_bpt); 87 EXPORT_SYMBOL(__debugger_sstep); 88 EXPORT_SYMBOL(__debugger_iabr_match); 89 EXPORT_SYMBOL(__debugger_break_match); 90 EXPORT_SYMBOL(__debugger_fault_handler); 91 #endif 92 93 /* Transactional Memory trap debug */ 94 #ifdef TM_DEBUG_SW 95 #define TM_DEBUG(x...) printk(KERN_INFO x) 96 #else 97 #define TM_DEBUG(x...) do { } while(0) 98 #endif 99 100 static const char *signame(int signr) 101 { 102 switch (signr) { 103 case SIGBUS: return "bus error"; 104 case SIGFPE: return "floating point exception"; 105 case SIGILL: return "illegal instruction"; 106 case SIGSEGV: return "segfault"; 107 case SIGTRAP: return "unhandled trap"; 108 } 109 110 return "unknown signal"; 111 } 112 113 /* 114 * Trap & Exception support 115 */ 116 117 #ifdef CONFIG_PMAC_BACKLIGHT 118 static void pmac_backlight_unblank(void) 119 { 120 mutex_lock(&pmac_backlight_mutex); 121 if (pmac_backlight) { 122 struct backlight_properties *props; 123 124 props = &pmac_backlight->props; 125 props->brightness = props->max_brightness; 126 props->power = FB_BLANK_UNBLANK; 127 backlight_update_status(pmac_backlight); 128 } 129 mutex_unlock(&pmac_backlight_mutex); 130 } 131 #else 132 static inline void pmac_backlight_unblank(void) { } 133 #endif 134 135 /* 136 * If oops/die is expected to crash the machine, return true here. 137 * 138 * This should not be expected to be 100% accurate, there may be 139 * notifiers registered or other unexpected conditions that may bring 140 * down the kernel. Or if the current process in the kernel is holding 141 * locks or has other critical state, the kernel may become effectively 142 * unusable anyway. 143 */ 144 bool die_will_crash(void) 145 { 146 if (should_fadump_crash()) 147 return true; 148 if (kexec_should_crash(current)) 149 return true; 150 if (in_interrupt() || panic_on_oops || 151 !current->pid || is_global_init(current)) 152 return true; 153 154 return false; 155 } 156 157 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 158 static int die_owner = -1; 159 static unsigned int die_nest_count; 160 static int die_counter; 161 162 extern void panic_flush_kmsg_start(void) 163 { 164 /* 165 * These are mostly taken from kernel/panic.c, but tries to do 166 * relatively minimal work. Don't use delay functions (TB may 167 * be broken), don't crash dump (need to set a firmware log), 168 * don't run notifiers. We do want to get some information to 169 * Linux console. 170 */ 171 console_verbose(); 172 bust_spinlocks(1); 173 } 174 175 extern void panic_flush_kmsg_end(void) 176 { 177 printk_safe_flush_on_panic(); 178 kmsg_dump(KMSG_DUMP_PANIC); 179 bust_spinlocks(0); 180 debug_locks_off(); 181 console_flush_on_panic(); 182 } 183 184 static unsigned long oops_begin(struct pt_regs *regs) 185 { 186 int cpu; 187 unsigned long flags; 188 189 oops_enter(); 190 191 /* racy, but better than risking deadlock. */ 192 raw_local_irq_save(flags); 193 cpu = smp_processor_id(); 194 if (!arch_spin_trylock(&die_lock)) { 195 if (cpu == die_owner) 196 /* nested oops. should stop eventually */; 197 else 198 arch_spin_lock(&die_lock); 199 } 200 die_nest_count++; 201 die_owner = cpu; 202 console_verbose(); 203 bust_spinlocks(1); 204 if (machine_is(powermac)) 205 pmac_backlight_unblank(); 206 return flags; 207 } 208 NOKPROBE_SYMBOL(oops_begin); 209 210 static void oops_end(unsigned long flags, struct pt_regs *regs, 211 int signr) 212 { 213 bust_spinlocks(0); 214 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 215 die_nest_count--; 216 oops_exit(); 217 printk("\n"); 218 if (!die_nest_count) { 219 /* Nest count reaches zero, release the lock. */ 220 die_owner = -1; 221 arch_spin_unlock(&die_lock); 222 } 223 raw_local_irq_restore(flags); 224 225 /* 226 * system_reset_excption handles debugger, crash dump, panic, for 0x100 227 */ 228 if (TRAP(regs) == 0x100) 229 return; 230 231 crash_fadump(regs, "die oops"); 232 233 if (kexec_should_crash(current)) 234 crash_kexec(regs); 235 236 if (!signr) 237 return; 238 239 /* 240 * While our oops output is serialised by a spinlock, output 241 * from panic() called below can race and corrupt it. If we 242 * know we are going to panic, delay for 1 second so we have a 243 * chance to get clean backtraces from all CPUs that are oopsing. 244 */ 245 if (in_interrupt() || panic_on_oops || !current->pid || 246 is_global_init(current)) { 247 mdelay(MSEC_PER_SEC); 248 } 249 250 if (panic_on_oops) 251 panic("Fatal exception"); 252 do_exit(signr); 253 } 254 NOKPROBE_SYMBOL(oops_end); 255 256 static int __die(const char *str, struct pt_regs *regs, long err) 257 { 258 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 259 260 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n", 261 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 262 PAGE_SIZE / 1024, 263 early_radix_enabled() ? " MMU=Radix" : "", 264 early_mmu_has_feature(MMU_FTR_HPTE_TABLE) ? " MMU=Hash" : "", 265 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 266 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 267 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 268 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 269 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 270 ppc_md.name ? ppc_md.name : ""); 271 272 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 273 return 1; 274 275 print_modules(); 276 show_regs(regs); 277 278 return 0; 279 } 280 NOKPROBE_SYMBOL(__die); 281 282 void die(const char *str, struct pt_regs *regs, long err) 283 { 284 unsigned long flags; 285 286 /* 287 * system_reset_excption handles debugger, crash dump, panic, for 0x100 288 */ 289 if (TRAP(regs) != 0x100) { 290 if (debugger(regs)) 291 return; 292 } 293 294 flags = oops_begin(regs); 295 if (__die(str, regs, err)) 296 err = 0; 297 oops_end(flags, regs, err); 298 } 299 NOKPROBE_SYMBOL(die); 300 301 void user_single_step_report(struct pt_regs *regs) 302 { 303 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip, current); 304 } 305 306 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 307 unsigned long addr) 308 { 309 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 310 DEFAULT_RATELIMIT_BURST); 311 312 if (!show_unhandled_signals) 313 return; 314 315 if (!unhandled_signal(current, signr)) 316 return; 317 318 if (!__ratelimit(&rs)) 319 return; 320 321 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 322 current->comm, current->pid, signame(signr), signr, 323 addr, regs->nip, regs->link, code); 324 325 print_vma_addr(KERN_CONT " in ", regs->nip); 326 327 pr_cont("\n"); 328 329 show_user_instructions(regs); 330 } 331 332 static bool exception_common(int signr, struct pt_regs *regs, int code, 333 unsigned long addr) 334 { 335 if (!user_mode(regs)) { 336 die("Exception in kernel mode", regs, signr); 337 return false; 338 } 339 340 show_signal_msg(signr, regs, code, addr); 341 342 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 343 local_irq_enable(); 344 345 current->thread.trap_nr = code; 346 347 /* 348 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need 349 * to capture the content, if the task gets killed. 350 */ 351 thread_pkey_regs_save(¤t->thread); 352 353 return true; 354 } 355 356 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 357 { 358 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 359 return; 360 361 force_sig_pkuerr((void __user *) addr, key); 362 } 363 364 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 365 { 366 if (!exception_common(signr, regs, code, addr)) 367 return; 368 369 force_sig_fault(signr, code, (void __user *)addr, current); 370 } 371 372 void system_reset_exception(struct pt_regs *regs) 373 { 374 /* 375 * Avoid crashes in case of nested NMI exceptions. Recoverability 376 * is determined by RI and in_nmi 377 */ 378 bool nested = in_nmi(); 379 if (!nested) 380 nmi_enter(); 381 382 __this_cpu_inc(irq_stat.sreset_irqs); 383 384 /* See if any machine dependent calls */ 385 if (ppc_md.system_reset_exception) { 386 if (ppc_md.system_reset_exception(regs)) 387 goto out; 388 } 389 390 if (debugger(regs)) 391 goto out; 392 393 /* 394 * A system reset is a request to dump, so we always send 395 * it through the crashdump code (if fadump or kdump are 396 * registered). 397 */ 398 crash_fadump(regs, "System Reset"); 399 400 crash_kexec(regs); 401 402 /* 403 * We aren't the primary crash CPU. We need to send it 404 * to a holding pattern to avoid it ending up in the panic 405 * code. 406 */ 407 crash_kexec_secondary(regs); 408 409 /* 410 * No debugger or crash dump registered, print logs then 411 * panic. 412 */ 413 die("System Reset", regs, SIGABRT); 414 415 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 416 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 417 nmi_panic(regs, "System Reset"); 418 419 out: 420 #ifdef CONFIG_PPC_BOOK3S_64 421 BUG_ON(get_paca()->in_nmi == 0); 422 if (get_paca()->in_nmi > 1) 423 nmi_panic(regs, "Unrecoverable nested System Reset"); 424 #endif 425 /* Must die if the interrupt is not recoverable */ 426 if (!(regs->msr & MSR_RI)) 427 nmi_panic(regs, "Unrecoverable System Reset"); 428 429 if (!nested) 430 nmi_exit(); 431 432 /* What should we do here? We could issue a shutdown or hard reset. */ 433 } 434 435 /* 436 * I/O accesses can cause machine checks on powermacs. 437 * Check if the NIP corresponds to the address of a sync 438 * instruction for which there is an entry in the exception 439 * table. 440 * Note that the 601 only takes a machine check on TEA 441 * (transfer error ack) signal assertion, and does not 442 * set any of the top 16 bits of SRR1. 443 * -- paulus. 444 */ 445 static inline int check_io_access(struct pt_regs *regs) 446 { 447 #ifdef CONFIG_PPC32 448 unsigned long msr = regs->msr; 449 const struct exception_table_entry *entry; 450 unsigned int *nip = (unsigned int *)regs->nip; 451 452 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 453 && (entry = search_exception_tables(regs->nip)) != NULL) { 454 /* 455 * Check that it's a sync instruction, or somewhere 456 * in the twi; isync; nop sequence that inb/inw/inl uses. 457 * As the address is in the exception table 458 * we should be able to read the instr there. 459 * For the debug message, we look at the preceding 460 * load or store. 461 */ 462 if (*nip == PPC_INST_NOP) 463 nip -= 2; 464 else if (*nip == PPC_INST_ISYNC) 465 --nip; 466 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 467 unsigned int rb; 468 469 --nip; 470 rb = (*nip >> 11) & 0x1f; 471 printk(KERN_DEBUG "%s bad port %lx at %p\n", 472 (*nip & 0x100)? "OUT to": "IN from", 473 regs->gpr[rb] - _IO_BASE, nip); 474 regs->msr |= MSR_RI; 475 regs->nip = extable_fixup(entry); 476 return 1; 477 } 478 } 479 #endif /* CONFIG_PPC32 */ 480 return 0; 481 } 482 483 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 484 /* On 4xx, the reason for the machine check or program exception 485 is in the ESR. */ 486 #define get_reason(regs) ((regs)->dsisr) 487 #define REASON_FP ESR_FP 488 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 489 #define REASON_PRIVILEGED ESR_PPR 490 #define REASON_TRAP ESR_PTR 491 492 /* single-step stuff */ 493 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 494 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 495 #define clear_br_trace(regs) do {} while(0) 496 #else 497 /* On non-4xx, the reason for the machine check or program 498 exception is in the MSR. */ 499 #define get_reason(regs) ((regs)->msr) 500 #define REASON_TM SRR1_PROGTM 501 #define REASON_FP SRR1_PROGFPE 502 #define REASON_ILLEGAL SRR1_PROGILL 503 #define REASON_PRIVILEGED SRR1_PROGPRIV 504 #define REASON_TRAP SRR1_PROGTRAP 505 506 #define single_stepping(regs) ((regs)->msr & MSR_SE) 507 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 508 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) 509 #endif 510 511 #if defined(CONFIG_E500) 512 int machine_check_e500mc(struct pt_regs *regs) 513 { 514 unsigned long mcsr = mfspr(SPRN_MCSR); 515 unsigned long pvr = mfspr(SPRN_PVR); 516 unsigned long reason = mcsr; 517 int recoverable = 1; 518 519 if (reason & MCSR_LD) { 520 recoverable = fsl_rio_mcheck_exception(regs); 521 if (recoverable == 1) 522 goto silent_out; 523 } 524 525 printk("Machine check in kernel mode.\n"); 526 printk("Caused by (from MCSR=%lx): ", reason); 527 528 if (reason & MCSR_MCP) 529 pr_cont("Machine Check Signal\n"); 530 531 if (reason & MCSR_ICPERR) { 532 pr_cont("Instruction Cache Parity Error\n"); 533 534 /* 535 * This is recoverable by invalidating the i-cache. 536 */ 537 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 538 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 539 ; 540 541 /* 542 * This will generally be accompanied by an instruction 543 * fetch error report -- only treat MCSR_IF as fatal 544 * if it wasn't due to an L1 parity error. 545 */ 546 reason &= ~MCSR_IF; 547 } 548 549 if (reason & MCSR_DCPERR_MC) { 550 pr_cont("Data Cache Parity Error\n"); 551 552 /* 553 * In write shadow mode we auto-recover from the error, but it 554 * may still get logged and cause a machine check. We should 555 * only treat the non-write shadow case as non-recoverable. 556 */ 557 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 558 * is not implemented but L1 data cache always runs in write 559 * shadow mode. Hence on data cache parity errors HW will 560 * automatically invalidate the L1 Data Cache. 561 */ 562 if (PVR_VER(pvr) != PVR_VER_E6500) { 563 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 564 recoverable = 0; 565 } 566 } 567 568 if (reason & MCSR_L2MMU_MHIT) { 569 pr_cont("Hit on multiple TLB entries\n"); 570 recoverable = 0; 571 } 572 573 if (reason & MCSR_NMI) 574 pr_cont("Non-maskable interrupt\n"); 575 576 if (reason & MCSR_IF) { 577 pr_cont("Instruction Fetch Error Report\n"); 578 recoverable = 0; 579 } 580 581 if (reason & MCSR_LD) { 582 pr_cont("Load Error Report\n"); 583 recoverable = 0; 584 } 585 586 if (reason & MCSR_ST) { 587 pr_cont("Store Error Report\n"); 588 recoverable = 0; 589 } 590 591 if (reason & MCSR_LDG) { 592 pr_cont("Guarded Load Error Report\n"); 593 recoverable = 0; 594 } 595 596 if (reason & MCSR_TLBSYNC) 597 pr_cont("Simultaneous tlbsync operations\n"); 598 599 if (reason & MCSR_BSL2_ERR) { 600 pr_cont("Level 2 Cache Error\n"); 601 recoverable = 0; 602 } 603 604 if (reason & MCSR_MAV) { 605 u64 addr; 606 607 addr = mfspr(SPRN_MCAR); 608 addr |= (u64)mfspr(SPRN_MCARU) << 32; 609 610 pr_cont("Machine Check %s Address: %#llx\n", 611 reason & MCSR_MEA ? "Effective" : "Physical", addr); 612 } 613 614 silent_out: 615 mtspr(SPRN_MCSR, mcsr); 616 return mfspr(SPRN_MCSR) == 0 && recoverable; 617 } 618 619 int machine_check_e500(struct pt_regs *regs) 620 { 621 unsigned long reason = mfspr(SPRN_MCSR); 622 623 if (reason & MCSR_BUS_RBERR) { 624 if (fsl_rio_mcheck_exception(regs)) 625 return 1; 626 if (fsl_pci_mcheck_exception(regs)) 627 return 1; 628 } 629 630 printk("Machine check in kernel mode.\n"); 631 printk("Caused by (from MCSR=%lx): ", reason); 632 633 if (reason & MCSR_MCP) 634 pr_cont("Machine Check Signal\n"); 635 if (reason & MCSR_ICPERR) 636 pr_cont("Instruction Cache Parity Error\n"); 637 if (reason & MCSR_DCP_PERR) 638 pr_cont("Data Cache Push Parity Error\n"); 639 if (reason & MCSR_DCPERR) 640 pr_cont("Data Cache Parity Error\n"); 641 if (reason & MCSR_BUS_IAERR) 642 pr_cont("Bus - Instruction Address Error\n"); 643 if (reason & MCSR_BUS_RAERR) 644 pr_cont("Bus - Read Address Error\n"); 645 if (reason & MCSR_BUS_WAERR) 646 pr_cont("Bus - Write Address Error\n"); 647 if (reason & MCSR_BUS_IBERR) 648 pr_cont("Bus - Instruction Data Error\n"); 649 if (reason & MCSR_BUS_RBERR) 650 pr_cont("Bus - Read Data Bus Error\n"); 651 if (reason & MCSR_BUS_WBERR) 652 pr_cont("Bus - Write Data Bus Error\n"); 653 if (reason & MCSR_BUS_IPERR) 654 pr_cont("Bus - Instruction Parity Error\n"); 655 if (reason & MCSR_BUS_RPERR) 656 pr_cont("Bus - Read Parity Error\n"); 657 658 return 0; 659 } 660 661 int machine_check_generic(struct pt_regs *regs) 662 { 663 return 0; 664 } 665 #elif defined(CONFIG_E200) 666 int machine_check_e200(struct pt_regs *regs) 667 { 668 unsigned long reason = mfspr(SPRN_MCSR); 669 670 printk("Machine check in kernel mode.\n"); 671 printk("Caused by (from MCSR=%lx): ", reason); 672 673 if (reason & MCSR_MCP) 674 pr_cont("Machine Check Signal\n"); 675 if (reason & MCSR_CP_PERR) 676 pr_cont("Cache Push Parity Error\n"); 677 if (reason & MCSR_CPERR) 678 pr_cont("Cache Parity Error\n"); 679 if (reason & MCSR_EXCP_ERR) 680 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 681 if (reason & MCSR_BUS_IRERR) 682 pr_cont("Bus - Read Bus Error on instruction fetch\n"); 683 if (reason & MCSR_BUS_DRERR) 684 pr_cont("Bus - Read Bus Error on data load\n"); 685 if (reason & MCSR_BUS_WRERR) 686 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n"); 687 688 return 0; 689 } 690 #elif defined(CONFIG_PPC32) 691 int machine_check_generic(struct pt_regs *regs) 692 { 693 unsigned long reason = regs->msr; 694 695 printk("Machine check in kernel mode.\n"); 696 printk("Caused by (from SRR1=%lx): ", reason); 697 switch (reason & 0x601F0000) { 698 case 0x80000: 699 pr_cont("Machine check signal\n"); 700 break; 701 case 0: /* for 601 */ 702 case 0x40000: 703 case 0x140000: /* 7450 MSS error and TEA */ 704 pr_cont("Transfer error ack signal\n"); 705 break; 706 case 0x20000: 707 pr_cont("Data parity error signal\n"); 708 break; 709 case 0x10000: 710 pr_cont("Address parity error signal\n"); 711 break; 712 case 0x20000000: 713 pr_cont("L1 Data Cache error\n"); 714 break; 715 case 0x40000000: 716 pr_cont("L1 Instruction Cache error\n"); 717 break; 718 case 0x00100000: 719 pr_cont("L2 data cache parity error\n"); 720 break; 721 default: 722 pr_cont("Unknown values in msr\n"); 723 } 724 return 0; 725 } 726 #endif /* everything else */ 727 728 void machine_check_exception(struct pt_regs *regs) 729 { 730 int recover = 0; 731 bool nested = in_nmi(); 732 if (!nested) 733 nmi_enter(); 734 735 __this_cpu_inc(irq_stat.mce_exceptions); 736 737 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 738 739 /* See if any machine dependent calls. In theory, we would want 740 * to call the CPU first, and call the ppc_md. one if the CPU 741 * one returns a positive number. However there is existing code 742 * that assumes the board gets a first chance, so let's keep it 743 * that way for now and fix things later. --BenH. 744 */ 745 if (ppc_md.machine_check_exception) 746 recover = ppc_md.machine_check_exception(regs); 747 else if (cur_cpu_spec->machine_check) 748 recover = cur_cpu_spec->machine_check(regs); 749 750 if (recover > 0) 751 goto bail; 752 753 if (debugger_fault_handler(regs)) 754 goto bail; 755 756 if (check_io_access(regs)) 757 goto bail; 758 759 /* Must die if the interrupt is not recoverable */ 760 if (!(regs->msr & MSR_RI)) 761 nmi_panic(regs, "Unrecoverable Machine check"); 762 763 if (!nested) 764 nmi_exit(); 765 766 die("Machine check", regs, SIGBUS); 767 768 return; 769 770 bail: 771 if (!nested) 772 nmi_exit(); 773 } 774 775 void SMIException(struct pt_regs *regs) 776 { 777 die("System Management Interrupt", regs, SIGABRT); 778 } 779 780 #ifdef CONFIG_VSX 781 static void p9_hmi_special_emu(struct pt_regs *regs) 782 { 783 unsigned int ra, rb, t, i, sel, instr, rc; 784 const void __user *addr; 785 u8 vbuf[16], *vdst; 786 unsigned long ea, msr, msr_mask; 787 bool swap; 788 789 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 790 return; 791 792 /* 793 * lxvb16x opcode: 0x7c0006d8 794 * lxvd2x opcode: 0x7c000698 795 * lxvh8x opcode: 0x7c000658 796 * lxvw4x opcode: 0x7c000618 797 */ 798 if ((instr & 0xfc00073e) != 0x7c000618) { 799 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 800 " instr=%08x\n", 801 smp_processor_id(), current->comm, current->pid, 802 regs->nip, instr); 803 return; 804 } 805 806 /* Grab vector registers into the task struct */ 807 msr = regs->msr; /* Grab msr before we flush the bits */ 808 flush_vsx_to_thread(current); 809 enable_kernel_altivec(); 810 811 /* 812 * Is userspace running with a different endian (this is rare but 813 * not impossible) 814 */ 815 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 816 817 /* Decode the instruction */ 818 ra = (instr >> 16) & 0x1f; 819 rb = (instr >> 11) & 0x1f; 820 t = (instr >> 21) & 0x1f; 821 if (instr & 1) 822 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 823 else 824 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 825 826 /* Grab the vector address */ 827 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 828 if (is_32bit_task()) 829 ea &= 0xfffffffful; 830 addr = (__force const void __user *)ea; 831 832 /* Check it */ 833 if (!access_ok(addr, 16)) { 834 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 835 " instr=%08x addr=%016lx\n", 836 smp_processor_id(), current->comm, current->pid, 837 regs->nip, instr, (unsigned long)addr); 838 return; 839 } 840 841 /* Read the vector */ 842 rc = 0; 843 if ((unsigned long)addr & 0xfUL) 844 /* unaligned case */ 845 rc = __copy_from_user_inatomic(vbuf, addr, 16); 846 else 847 __get_user_atomic_128_aligned(vbuf, addr, rc); 848 if (rc) { 849 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 850 " instr=%08x addr=%016lx\n", 851 smp_processor_id(), current->comm, current->pid, 852 regs->nip, instr, (unsigned long)addr); 853 return; 854 } 855 856 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 857 " instr=%08x addr=%016lx\n", 858 smp_processor_id(), current->comm, current->pid, regs->nip, 859 instr, (unsigned long) addr); 860 861 /* Grab instruction "selector" */ 862 sel = (instr >> 6) & 3; 863 864 /* 865 * Check to make sure the facility is actually enabled. This 866 * could happen if we get a false positive hit. 867 * 868 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 869 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 870 */ 871 msr_mask = MSR_VSX; 872 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 873 msr_mask = MSR_VEC; 874 if (!(msr & msr_mask)) { 875 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 876 " instr=%08x msr:%016lx\n", 877 smp_processor_id(), current->comm, current->pid, 878 regs->nip, instr, msr); 879 return; 880 } 881 882 /* Do logging here before we modify sel based on endian */ 883 switch (sel) { 884 case 0: /* lxvw4x */ 885 PPC_WARN_EMULATED(lxvw4x, regs); 886 break; 887 case 1: /* lxvh8x */ 888 PPC_WARN_EMULATED(lxvh8x, regs); 889 break; 890 case 2: /* lxvd2x */ 891 PPC_WARN_EMULATED(lxvd2x, regs); 892 break; 893 case 3: /* lxvb16x */ 894 PPC_WARN_EMULATED(lxvb16x, regs); 895 break; 896 } 897 898 #ifdef __LITTLE_ENDIAN__ 899 /* 900 * An LE kernel stores the vector in the task struct as an LE 901 * byte array (effectively swapping both the components and 902 * the content of the components). Those instructions expect 903 * the components to remain in ascending address order, so we 904 * swap them back. 905 * 906 * If we are running a BE user space, the expectation is that 907 * of a simple memcpy, so forcing the emulation to look like 908 * a lxvb16x should do the trick. 909 */ 910 if (swap) 911 sel = 3; 912 913 switch (sel) { 914 case 0: /* lxvw4x */ 915 for (i = 0; i < 4; i++) 916 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 917 break; 918 case 1: /* lxvh8x */ 919 for (i = 0; i < 8; i++) 920 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 921 break; 922 case 2: /* lxvd2x */ 923 for (i = 0; i < 2; i++) 924 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 925 break; 926 case 3: /* lxvb16x */ 927 for (i = 0; i < 16; i++) 928 vdst[i] = vbuf[15-i]; 929 break; 930 } 931 #else /* __LITTLE_ENDIAN__ */ 932 /* On a big endian kernel, a BE userspace only needs a memcpy */ 933 if (!swap) 934 sel = 3; 935 936 /* Otherwise, we need to swap the content of the components */ 937 switch (sel) { 938 case 0: /* lxvw4x */ 939 for (i = 0; i < 4; i++) 940 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 941 break; 942 case 1: /* lxvh8x */ 943 for (i = 0; i < 8; i++) 944 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 945 break; 946 case 2: /* lxvd2x */ 947 for (i = 0; i < 2; i++) 948 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 949 break; 950 case 3: /* lxvb16x */ 951 memcpy(vdst, vbuf, 16); 952 break; 953 } 954 #endif /* !__LITTLE_ENDIAN__ */ 955 956 /* Go to next instruction */ 957 regs->nip += 4; 958 } 959 #endif /* CONFIG_VSX */ 960 961 void handle_hmi_exception(struct pt_regs *regs) 962 { 963 struct pt_regs *old_regs; 964 965 old_regs = set_irq_regs(regs); 966 irq_enter(); 967 968 #ifdef CONFIG_VSX 969 /* Real mode flagged P9 special emu is needed */ 970 if (local_paca->hmi_p9_special_emu) { 971 local_paca->hmi_p9_special_emu = 0; 972 973 /* 974 * We don't want to take page faults while doing the 975 * emulation, we just replay the instruction if necessary. 976 */ 977 pagefault_disable(); 978 p9_hmi_special_emu(regs); 979 pagefault_enable(); 980 } 981 #endif /* CONFIG_VSX */ 982 983 if (ppc_md.handle_hmi_exception) 984 ppc_md.handle_hmi_exception(regs); 985 986 irq_exit(); 987 set_irq_regs(old_regs); 988 } 989 990 void unknown_exception(struct pt_regs *regs) 991 { 992 enum ctx_state prev_state = exception_enter(); 993 994 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 995 regs->nip, regs->msr, regs->trap); 996 997 _exception(SIGTRAP, regs, TRAP_UNK, 0); 998 999 exception_exit(prev_state); 1000 } 1001 1002 void instruction_breakpoint_exception(struct pt_regs *regs) 1003 { 1004 enum ctx_state prev_state = exception_enter(); 1005 1006 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1007 5, SIGTRAP) == NOTIFY_STOP) 1008 goto bail; 1009 if (debugger_iabr_match(regs)) 1010 goto bail; 1011 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1012 1013 bail: 1014 exception_exit(prev_state); 1015 } 1016 1017 void RunModeException(struct pt_regs *regs) 1018 { 1019 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1020 } 1021 1022 void single_step_exception(struct pt_regs *regs) 1023 { 1024 enum ctx_state prev_state = exception_enter(); 1025 1026 clear_single_step(regs); 1027 clear_br_trace(regs); 1028 1029 if (kprobe_post_handler(regs)) 1030 return; 1031 1032 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1033 5, SIGTRAP) == NOTIFY_STOP) 1034 goto bail; 1035 if (debugger_sstep(regs)) 1036 goto bail; 1037 1038 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1039 1040 bail: 1041 exception_exit(prev_state); 1042 } 1043 NOKPROBE_SYMBOL(single_step_exception); 1044 1045 /* 1046 * After we have successfully emulated an instruction, we have to 1047 * check if the instruction was being single-stepped, and if so, 1048 * pretend we got a single-step exception. This was pointed out 1049 * by Kumar Gala. -- paulus 1050 */ 1051 static void emulate_single_step(struct pt_regs *regs) 1052 { 1053 if (single_stepping(regs)) 1054 single_step_exception(regs); 1055 } 1056 1057 static inline int __parse_fpscr(unsigned long fpscr) 1058 { 1059 int ret = FPE_FLTUNK; 1060 1061 /* Invalid operation */ 1062 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1063 ret = FPE_FLTINV; 1064 1065 /* Overflow */ 1066 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1067 ret = FPE_FLTOVF; 1068 1069 /* Underflow */ 1070 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1071 ret = FPE_FLTUND; 1072 1073 /* Divide by zero */ 1074 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1075 ret = FPE_FLTDIV; 1076 1077 /* Inexact result */ 1078 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1079 ret = FPE_FLTRES; 1080 1081 return ret; 1082 } 1083 1084 static void parse_fpe(struct pt_regs *regs) 1085 { 1086 int code = 0; 1087 1088 flush_fp_to_thread(current); 1089 1090 code = __parse_fpscr(current->thread.fp_state.fpscr); 1091 1092 _exception(SIGFPE, regs, code, regs->nip); 1093 } 1094 1095 /* 1096 * Illegal instruction emulation support. Originally written to 1097 * provide the PVR to user applications using the mfspr rd, PVR. 1098 * Return non-zero if we can't emulate, or -EFAULT if the associated 1099 * memory access caused an access fault. Return zero on success. 1100 * 1101 * There are a couple of ways to do this, either "decode" the instruction 1102 * or directly match lots of bits. In this case, matching lots of 1103 * bits is faster and easier. 1104 * 1105 */ 1106 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1107 { 1108 u8 rT = (instword >> 21) & 0x1f; 1109 u8 rA = (instword >> 16) & 0x1f; 1110 u8 NB_RB = (instword >> 11) & 0x1f; 1111 u32 num_bytes; 1112 unsigned long EA; 1113 int pos = 0; 1114 1115 /* Early out if we are an invalid form of lswx */ 1116 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1117 if ((rT == rA) || (rT == NB_RB)) 1118 return -EINVAL; 1119 1120 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1121 1122 switch (instword & PPC_INST_STRING_MASK) { 1123 case PPC_INST_LSWX: 1124 case PPC_INST_STSWX: 1125 EA += NB_RB; 1126 num_bytes = regs->xer & 0x7f; 1127 break; 1128 case PPC_INST_LSWI: 1129 case PPC_INST_STSWI: 1130 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1131 break; 1132 default: 1133 return -EINVAL; 1134 } 1135 1136 while (num_bytes != 0) 1137 { 1138 u8 val; 1139 u32 shift = 8 * (3 - (pos & 0x3)); 1140 1141 /* if process is 32-bit, clear upper 32 bits of EA */ 1142 if ((regs->msr & MSR_64BIT) == 0) 1143 EA &= 0xFFFFFFFF; 1144 1145 switch ((instword & PPC_INST_STRING_MASK)) { 1146 case PPC_INST_LSWX: 1147 case PPC_INST_LSWI: 1148 if (get_user(val, (u8 __user *)EA)) 1149 return -EFAULT; 1150 /* first time updating this reg, 1151 * zero it out */ 1152 if (pos == 0) 1153 regs->gpr[rT] = 0; 1154 regs->gpr[rT] |= val << shift; 1155 break; 1156 case PPC_INST_STSWI: 1157 case PPC_INST_STSWX: 1158 val = regs->gpr[rT] >> shift; 1159 if (put_user(val, (u8 __user *)EA)) 1160 return -EFAULT; 1161 break; 1162 } 1163 /* move EA to next address */ 1164 EA += 1; 1165 num_bytes--; 1166 1167 /* manage our position within the register */ 1168 if (++pos == 4) { 1169 pos = 0; 1170 if (++rT == 32) 1171 rT = 0; 1172 } 1173 } 1174 1175 return 0; 1176 } 1177 1178 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1179 { 1180 u32 ra,rs; 1181 unsigned long tmp; 1182 1183 ra = (instword >> 16) & 0x1f; 1184 rs = (instword >> 21) & 0x1f; 1185 1186 tmp = regs->gpr[rs]; 1187 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1188 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1189 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1190 regs->gpr[ra] = tmp; 1191 1192 return 0; 1193 } 1194 1195 static int emulate_isel(struct pt_regs *regs, u32 instword) 1196 { 1197 u8 rT = (instword >> 21) & 0x1f; 1198 u8 rA = (instword >> 16) & 0x1f; 1199 u8 rB = (instword >> 11) & 0x1f; 1200 u8 BC = (instword >> 6) & 0x1f; 1201 u8 bit; 1202 unsigned long tmp; 1203 1204 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1205 bit = (regs->ccr >> (31 - BC)) & 0x1; 1206 1207 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1208 1209 return 0; 1210 } 1211 1212 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1213 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1214 { 1215 /* If we're emulating a load/store in an active transaction, we cannot 1216 * emulate it as the kernel operates in transaction suspended context. 1217 * We need to abort the transaction. This creates a persistent TM 1218 * abort so tell the user what caused it with a new code. 1219 */ 1220 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1221 tm_enable(); 1222 tm_abort(cause); 1223 return true; 1224 } 1225 return false; 1226 } 1227 #else 1228 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1229 { 1230 return false; 1231 } 1232 #endif 1233 1234 static int emulate_instruction(struct pt_regs *regs) 1235 { 1236 u32 instword; 1237 u32 rd; 1238 1239 if (!user_mode(regs)) 1240 return -EINVAL; 1241 CHECK_FULL_REGS(regs); 1242 1243 if (get_user(instword, (u32 __user *)(regs->nip))) 1244 return -EFAULT; 1245 1246 /* Emulate the mfspr rD, PVR. */ 1247 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1248 PPC_WARN_EMULATED(mfpvr, regs); 1249 rd = (instword >> 21) & 0x1f; 1250 regs->gpr[rd] = mfspr(SPRN_PVR); 1251 return 0; 1252 } 1253 1254 /* Emulating the dcba insn is just a no-op. */ 1255 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1256 PPC_WARN_EMULATED(dcba, regs); 1257 return 0; 1258 } 1259 1260 /* Emulate the mcrxr insn. */ 1261 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1262 int shift = (instword >> 21) & 0x1c; 1263 unsigned long msk = 0xf0000000UL >> shift; 1264 1265 PPC_WARN_EMULATED(mcrxr, regs); 1266 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1267 regs->xer &= ~0xf0000000UL; 1268 return 0; 1269 } 1270 1271 /* Emulate load/store string insn. */ 1272 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1273 if (tm_abort_check(regs, 1274 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1275 return -EINVAL; 1276 PPC_WARN_EMULATED(string, regs); 1277 return emulate_string_inst(regs, instword); 1278 } 1279 1280 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1281 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1282 PPC_WARN_EMULATED(popcntb, regs); 1283 return emulate_popcntb_inst(regs, instword); 1284 } 1285 1286 /* Emulate isel (Integer Select) instruction */ 1287 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1288 PPC_WARN_EMULATED(isel, regs); 1289 return emulate_isel(regs, instword); 1290 } 1291 1292 /* Emulate sync instruction variants */ 1293 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1294 PPC_WARN_EMULATED(sync, regs); 1295 asm volatile("sync"); 1296 return 0; 1297 } 1298 1299 #ifdef CONFIG_PPC64 1300 /* Emulate the mfspr rD, DSCR. */ 1301 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1302 PPC_INST_MFSPR_DSCR_USER) || 1303 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1304 PPC_INST_MFSPR_DSCR)) && 1305 cpu_has_feature(CPU_FTR_DSCR)) { 1306 PPC_WARN_EMULATED(mfdscr, regs); 1307 rd = (instword >> 21) & 0x1f; 1308 regs->gpr[rd] = mfspr(SPRN_DSCR); 1309 return 0; 1310 } 1311 /* Emulate the mtspr DSCR, rD. */ 1312 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1313 PPC_INST_MTSPR_DSCR_USER) || 1314 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1315 PPC_INST_MTSPR_DSCR)) && 1316 cpu_has_feature(CPU_FTR_DSCR)) { 1317 PPC_WARN_EMULATED(mtdscr, regs); 1318 rd = (instword >> 21) & 0x1f; 1319 current->thread.dscr = regs->gpr[rd]; 1320 current->thread.dscr_inherit = 1; 1321 mtspr(SPRN_DSCR, current->thread.dscr); 1322 return 0; 1323 } 1324 #endif 1325 1326 return -EINVAL; 1327 } 1328 1329 int is_valid_bugaddr(unsigned long addr) 1330 { 1331 return is_kernel_addr(addr); 1332 } 1333 1334 #ifdef CONFIG_MATH_EMULATION 1335 static int emulate_math(struct pt_regs *regs) 1336 { 1337 int ret; 1338 extern int do_mathemu(struct pt_regs *regs); 1339 1340 ret = do_mathemu(regs); 1341 if (ret >= 0) 1342 PPC_WARN_EMULATED(math, regs); 1343 1344 switch (ret) { 1345 case 0: 1346 emulate_single_step(regs); 1347 return 0; 1348 case 1: { 1349 int code = 0; 1350 code = __parse_fpscr(current->thread.fp_state.fpscr); 1351 _exception(SIGFPE, regs, code, regs->nip); 1352 return 0; 1353 } 1354 case -EFAULT: 1355 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1356 return 0; 1357 } 1358 1359 return -1; 1360 } 1361 #else 1362 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1363 #endif 1364 1365 void program_check_exception(struct pt_regs *regs) 1366 { 1367 enum ctx_state prev_state = exception_enter(); 1368 unsigned int reason = get_reason(regs); 1369 1370 /* We can now get here via a FP Unavailable exception if the core 1371 * has no FPU, in that case the reason flags will be 0 */ 1372 1373 if (reason & REASON_FP) { 1374 /* IEEE FP exception */ 1375 parse_fpe(regs); 1376 goto bail; 1377 } 1378 if (reason & REASON_TRAP) { 1379 unsigned long bugaddr; 1380 /* Debugger is first in line to stop recursive faults in 1381 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1382 if (debugger_bpt(regs)) 1383 goto bail; 1384 1385 if (kprobe_handler(regs)) 1386 goto bail; 1387 1388 /* trap exception */ 1389 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1390 == NOTIFY_STOP) 1391 goto bail; 1392 1393 bugaddr = regs->nip; 1394 /* 1395 * Fixup bugaddr for BUG_ON() in real mode 1396 */ 1397 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1398 bugaddr += PAGE_OFFSET; 1399 1400 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1401 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1402 regs->nip += 4; 1403 goto bail; 1404 } 1405 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1406 goto bail; 1407 } 1408 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1409 if (reason & REASON_TM) { 1410 /* This is a TM "Bad Thing Exception" program check. 1411 * This occurs when: 1412 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1413 * transition in TM states. 1414 * - A trechkpt is attempted when transactional. 1415 * - A treclaim is attempted when non transactional. 1416 * - A tend is illegally attempted. 1417 * - writing a TM SPR when transactional. 1418 * 1419 * If usermode caused this, it's done something illegal and 1420 * gets a SIGILL slap on the wrist. We call it an illegal 1421 * operand to distinguish from the instruction just being bad 1422 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1423 * illegal /placement/ of a valid instruction. 1424 */ 1425 if (user_mode(regs)) { 1426 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1427 goto bail; 1428 } else { 1429 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1430 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1431 regs->nip, regs->msr, get_paca()->tm_scratch); 1432 die("Unrecoverable exception", regs, SIGABRT); 1433 } 1434 } 1435 #endif 1436 1437 /* 1438 * If we took the program check in the kernel skip down to sending a 1439 * SIGILL. The subsequent cases all relate to emulating instructions 1440 * which we should only do for userspace. We also do not want to enable 1441 * interrupts for kernel faults because that might lead to further 1442 * faults, and loose the context of the original exception. 1443 */ 1444 if (!user_mode(regs)) 1445 goto sigill; 1446 1447 /* We restore the interrupt state now */ 1448 if (!arch_irq_disabled_regs(regs)) 1449 local_irq_enable(); 1450 1451 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1452 * but there seems to be a hardware bug on the 405GP (RevD) 1453 * that means ESR is sometimes set incorrectly - either to 1454 * ESR_DST (!?) or 0. In the process of chasing this with the 1455 * hardware people - not sure if it can happen on any illegal 1456 * instruction or only on FP instructions, whether there is a 1457 * pattern to occurrences etc. -dgibson 31/Mar/2003 1458 */ 1459 if (!emulate_math(regs)) 1460 goto bail; 1461 1462 /* Try to emulate it if we should. */ 1463 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1464 switch (emulate_instruction(regs)) { 1465 case 0: 1466 regs->nip += 4; 1467 emulate_single_step(regs); 1468 goto bail; 1469 case -EFAULT: 1470 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1471 goto bail; 1472 } 1473 } 1474 1475 sigill: 1476 if (reason & REASON_PRIVILEGED) 1477 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1478 else 1479 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1480 1481 bail: 1482 exception_exit(prev_state); 1483 } 1484 NOKPROBE_SYMBOL(program_check_exception); 1485 1486 /* 1487 * This occurs when running in hypervisor mode on POWER6 or later 1488 * and an illegal instruction is encountered. 1489 */ 1490 void emulation_assist_interrupt(struct pt_regs *regs) 1491 { 1492 regs->msr |= REASON_ILLEGAL; 1493 program_check_exception(regs); 1494 } 1495 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1496 1497 void alignment_exception(struct pt_regs *regs) 1498 { 1499 enum ctx_state prev_state = exception_enter(); 1500 int sig, code, fixed = 0; 1501 1502 /* We restore the interrupt state now */ 1503 if (!arch_irq_disabled_regs(regs)) 1504 local_irq_enable(); 1505 1506 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1507 goto bail; 1508 1509 /* we don't implement logging of alignment exceptions */ 1510 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1511 fixed = fix_alignment(regs); 1512 1513 if (fixed == 1) { 1514 regs->nip += 4; /* skip over emulated instruction */ 1515 emulate_single_step(regs); 1516 goto bail; 1517 } 1518 1519 /* Operand address was bad */ 1520 if (fixed == -EFAULT) { 1521 sig = SIGSEGV; 1522 code = SEGV_ACCERR; 1523 } else { 1524 sig = SIGBUS; 1525 code = BUS_ADRALN; 1526 } 1527 if (user_mode(regs)) 1528 _exception(sig, regs, code, regs->dar); 1529 else 1530 bad_page_fault(regs, regs->dar, sig); 1531 1532 bail: 1533 exception_exit(prev_state); 1534 } 1535 1536 void StackOverflow(struct pt_regs *regs) 1537 { 1538 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n", 1539 current->comm, task_pid_nr(current), regs->gpr[1]); 1540 debugger(regs); 1541 show_regs(regs); 1542 panic("kernel stack overflow"); 1543 } 1544 1545 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1546 { 1547 enum ctx_state prev_state = exception_enter(); 1548 1549 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1550 "%lx at %lx\n", regs->trap, regs->nip); 1551 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1552 1553 exception_exit(prev_state); 1554 } 1555 1556 void altivec_unavailable_exception(struct pt_regs *regs) 1557 { 1558 enum ctx_state prev_state = exception_enter(); 1559 1560 if (user_mode(regs)) { 1561 /* A user program has executed an altivec instruction, 1562 but this kernel doesn't support altivec. */ 1563 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1564 goto bail; 1565 } 1566 1567 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1568 "%lx at %lx\n", regs->trap, regs->nip); 1569 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1570 1571 bail: 1572 exception_exit(prev_state); 1573 } 1574 1575 void vsx_unavailable_exception(struct pt_regs *regs) 1576 { 1577 if (user_mode(regs)) { 1578 /* A user program has executed an vsx instruction, 1579 but this kernel doesn't support vsx. */ 1580 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1581 return; 1582 } 1583 1584 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1585 "%lx at %lx\n", regs->trap, regs->nip); 1586 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1587 } 1588 1589 #ifdef CONFIG_PPC64 1590 static void tm_unavailable(struct pt_regs *regs) 1591 { 1592 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1593 if (user_mode(regs)) { 1594 current->thread.load_tm++; 1595 regs->msr |= MSR_TM; 1596 tm_enable(); 1597 tm_restore_sprs(¤t->thread); 1598 return; 1599 } 1600 #endif 1601 pr_emerg("Unrecoverable TM Unavailable Exception " 1602 "%lx at %lx\n", regs->trap, regs->nip); 1603 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1604 } 1605 1606 void facility_unavailable_exception(struct pt_regs *regs) 1607 { 1608 static char *facility_strings[] = { 1609 [FSCR_FP_LG] = "FPU", 1610 [FSCR_VECVSX_LG] = "VMX/VSX", 1611 [FSCR_DSCR_LG] = "DSCR", 1612 [FSCR_PM_LG] = "PMU SPRs", 1613 [FSCR_BHRB_LG] = "BHRB", 1614 [FSCR_TM_LG] = "TM", 1615 [FSCR_EBB_LG] = "EBB", 1616 [FSCR_TAR_LG] = "TAR", 1617 [FSCR_MSGP_LG] = "MSGP", 1618 [FSCR_SCV_LG] = "SCV", 1619 }; 1620 char *facility = "unknown"; 1621 u64 value; 1622 u32 instword, rd; 1623 u8 status; 1624 bool hv; 1625 1626 hv = (TRAP(regs) == 0xf80); 1627 if (hv) 1628 value = mfspr(SPRN_HFSCR); 1629 else 1630 value = mfspr(SPRN_FSCR); 1631 1632 status = value >> 56; 1633 if ((hv || status >= 2) && 1634 (status < ARRAY_SIZE(facility_strings)) && 1635 facility_strings[status]) 1636 facility = facility_strings[status]; 1637 1638 /* We should not have taken this interrupt in kernel */ 1639 if (!user_mode(regs)) { 1640 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1641 facility, status, regs->nip); 1642 die("Unexpected facility unavailable exception", regs, SIGABRT); 1643 } 1644 1645 /* We restore the interrupt state now */ 1646 if (!arch_irq_disabled_regs(regs)) 1647 local_irq_enable(); 1648 1649 if (status == FSCR_DSCR_LG) { 1650 /* 1651 * User is accessing the DSCR register using the problem 1652 * state only SPR number (0x03) either through a mfspr or 1653 * a mtspr instruction. If it is a write attempt through 1654 * a mtspr, then we set the inherit bit. This also allows 1655 * the user to write or read the register directly in the 1656 * future by setting via the FSCR DSCR bit. But in case it 1657 * is a read DSCR attempt through a mfspr instruction, we 1658 * just emulate the instruction instead. This code path will 1659 * always emulate all the mfspr instructions till the user 1660 * has attempted at least one mtspr instruction. This way it 1661 * preserves the same behaviour when the user is accessing 1662 * the DSCR through privilege level only SPR number (0x11) 1663 * which is emulated through illegal instruction exception. 1664 * We always leave HFSCR DSCR set. 1665 */ 1666 if (get_user(instword, (u32 __user *)(regs->nip))) { 1667 pr_err("Failed to fetch the user instruction\n"); 1668 return; 1669 } 1670 1671 /* Write into DSCR (mtspr 0x03, RS) */ 1672 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1673 == PPC_INST_MTSPR_DSCR_USER) { 1674 rd = (instword >> 21) & 0x1f; 1675 current->thread.dscr = regs->gpr[rd]; 1676 current->thread.dscr_inherit = 1; 1677 current->thread.fscr |= FSCR_DSCR; 1678 mtspr(SPRN_FSCR, current->thread.fscr); 1679 } 1680 1681 /* Read from DSCR (mfspr RT, 0x03) */ 1682 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1683 == PPC_INST_MFSPR_DSCR_USER) { 1684 if (emulate_instruction(regs)) { 1685 pr_err("DSCR based mfspr emulation failed\n"); 1686 return; 1687 } 1688 regs->nip += 4; 1689 emulate_single_step(regs); 1690 } 1691 return; 1692 } 1693 1694 if (status == FSCR_TM_LG) { 1695 /* 1696 * If we're here then the hardware is TM aware because it 1697 * generated an exception with FSRM_TM set. 1698 * 1699 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1700 * told us not to do TM, or the kernel is not built with TM 1701 * support. 1702 * 1703 * If both of those things are true, then userspace can spam the 1704 * console by triggering the printk() below just by continually 1705 * doing tbegin (or any TM instruction). So in that case just 1706 * send the process a SIGILL immediately. 1707 */ 1708 if (!cpu_has_feature(CPU_FTR_TM)) 1709 goto out; 1710 1711 tm_unavailable(regs); 1712 return; 1713 } 1714 1715 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1716 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1717 1718 out: 1719 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1720 } 1721 #endif 1722 1723 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1724 1725 void fp_unavailable_tm(struct pt_regs *regs) 1726 { 1727 /* Note: This does not handle any kind of FP laziness. */ 1728 1729 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1730 regs->nip, regs->msr); 1731 1732 /* We can only have got here if the task started using FP after 1733 * beginning the transaction. So, the transactional regs are just a 1734 * copy of the checkpointed ones. But, we still need to recheckpoint 1735 * as we're enabling FP for the process; it will return, abort the 1736 * transaction, and probably retry but now with FP enabled. So the 1737 * checkpointed FP registers need to be loaded. 1738 */ 1739 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1740 1741 /* 1742 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1743 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1744 * 1745 * At this point, ck{fp,vr}_state contains the exact values we want to 1746 * recheckpoint. 1747 */ 1748 1749 /* Enable FP for the task: */ 1750 current->thread.load_fp = 1; 1751 1752 /* 1753 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1754 */ 1755 tm_recheckpoint(¤t->thread); 1756 } 1757 1758 void altivec_unavailable_tm(struct pt_regs *regs) 1759 { 1760 /* See the comments in fp_unavailable_tm(). This function operates 1761 * the same way. 1762 */ 1763 1764 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1765 "MSR=%lx\n", 1766 regs->nip, regs->msr); 1767 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1768 current->thread.load_vec = 1; 1769 tm_recheckpoint(¤t->thread); 1770 current->thread.used_vr = 1; 1771 } 1772 1773 void vsx_unavailable_tm(struct pt_regs *regs) 1774 { 1775 /* See the comments in fp_unavailable_tm(). This works similarly, 1776 * though we're loading both FP and VEC registers in here. 1777 * 1778 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1779 * regs. Either way, set MSR_VSX. 1780 */ 1781 1782 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1783 "MSR=%lx\n", 1784 regs->nip, regs->msr); 1785 1786 current->thread.used_vsr = 1; 1787 1788 /* This reclaims FP and/or VR regs if they're already enabled */ 1789 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1790 1791 current->thread.load_vec = 1; 1792 current->thread.load_fp = 1; 1793 1794 tm_recheckpoint(¤t->thread); 1795 } 1796 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1797 1798 void performance_monitor_exception(struct pt_regs *regs) 1799 { 1800 __this_cpu_inc(irq_stat.pmu_irqs); 1801 1802 perf_irq(regs); 1803 } 1804 1805 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1806 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1807 { 1808 int changed = 0; 1809 /* 1810 * Determine the cause of the debug event, clear the 1811 * event flags and send a trap to the handler. Torez 1812 */ 1813 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1814 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1815 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1816 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1817 #endif 1818 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1819 5); 1820 changed |= 0x01; 1821 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1822 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1823 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1824 6); 1825 changed |= 0x01; 1826 } else if (debug_status & DBSR_IAC1) { 1827 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1828 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1829 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1830 1); 1831 changed |= 0x01; 1832 } else if (debug_status & DBSR_IAC2) { 1833 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1834 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1835 2); 1836 changed |= 0x01; 1837 } else if (debug_status & DBSR_IAC3) { 1838 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1839 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1840 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1841 3); 1842 changed |= 0x01; 1843 } else if (debug_status & DBSR_IAC4) { 1844 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1845 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1846 4); 1847 changed |= 0x01; 1848 } 1849 /* 1850 * At the point this routine was called, the MSR(DE) was turned off. 1851 * Check all other debug flags and see if that bit needs to be turned 1852 * back on or not. 1853 */ 1854 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1855 current->thread.debug.dbcr1)) 1856 regs->msr |= MSR_DE; 1857 else 1858 /* Make sure the IDM flag is off */ 1859 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1860 1861 if (changed & 0x01) 1862 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1863 } 1864 1865 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1866 { 1867 current->thread.debug.dbsr = debug_status; 1868 1869 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1870 * on server, it stops on the target of the branch. In order to simulate 1871 * the server behaviour, we thus restart right away with a single step 1872 * instead of stopping here when hitting a BT 1873 */ 1874 if (debug_status & DBSR_BT) { 1875 regs->msr &= ~MSR_DE; 1876 1877 /* Disable BT */ 1878 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1879 /* Clear the BT event */ 1880 mtspr(SPRN_DBSR, DBSR_BT); 1881 1882 /* Do the single step trick only when coming from userspace */ 1883 if (user_mode(regs)) { 1884 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1885 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1886 regs->msr |= MSR_DE; 1887 return; 1888 } 1889 1890 if (kprobe_post_handler(regs)) 1891 return; 1892 1893 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1894 5, SIGTRAP) == NOTIFY_STOP) { 1895 return; 1896 } 1897 if (debugger_sstep(regs)) 1898 return; 1899 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1900 regs->msr &= ~MSR_DE; 1901 1902 /* Disable instruction completion */ 1903 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1904 /* Clear the instruction completion event */ 1905 mtspr(SPRN_DBSR, DBSR_IC); 1906 1907 if (kprobe_post_handler(regs)) 1908 return; 1909 1910 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1911 5, SIGTRAP) == NOTIFY_STOP) { 1912 return; 1913 } 1914 1915 if (debugger_sstep(regs)) 1916 return; 1917 1918 if (user_mode(regs)) { 1919 current->thread.debug.dbcr0 &= ~DBCR0_IC; 1920 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1921 current->thread.debug.dbcr1)) 1922 regs->msr |= MSR_DE; 1923 else 1924 /* Make sure the IDM bit is off */ 1925 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1926 } 1927 1928 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1929 } else 1930 handle_debug(regs, debug_status); 1931 } 1932 NOKPROBE_SYMBOL(DebugException); 1933 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1934 1935 #if !defined(CONFIG_TAU_INT) 1936 void TAUException(struct pt_regs *regs) 1937 { 1938 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1939 regs->nip, regs->msr, regs->trap, print_tainted()); 1940 } 1941 #endif /* CONFIG_INT_TAU */ 1942 1943 #ifdef CONFIG_ALTIVEC 1944 void altivec_assist_exception(struct pt_regs *regs) 1945 { 1946 int err; 1947 1948 if (!user_mode(regs)) { 1949 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1950 " at %lx\n", regs->nip); 1951 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1952 } 1953 1954 flush_altivec_to_thread(current); 1955 1956 PPC_WARN_EMULATED(altivec, regs); 1957 err = emulate_altivec(regs); 1958 if (err == 0) { 1959 regs->nip += 4; /* skip emulated instruction */ 1960 emulate_single_step(regs); 1961 return; 1962 } 1963 1964 if (err == -EFAULT) { 1965 /* got an error reading the instruction */ 1966 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1967 } else { 1968 /* didn't recognize the instruction */ 1969 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1970 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 1971 "in %s at %lx\n", current->comm, regs->nip); 1972 current->thread.vr_state.vscr.u[3] |= 0x10000; 1973 } 1974 } 1975 #endif /* CONFIG_ALTIVEC */ 1976 1977 #ifdef CONFIG_FSL_BOOKE 1978 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1979 unsigned long error_code) 1980 { 1981 /* We treat cache locking instructions from the user 1982 * as priv ops, in the future we could try to do 1983 * something smarter 1984 */ 1985 if (error_code & (ESR_DLK|ESR_ILK)) 1986 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1987 return; 1988 } 1989 #endif /* CONFIG_FSL_BOOKE */ 1990 1991 #ifdef CONFIG_SPE 1992 void SPEFloatingPointException(struct pt_regs *regs) 1993 { 1994 extern int do_spe_mathemu(struct pt_regs *regs); 1995 unsigned long spefscr; 1996 int fpexc_mode; 1997 int code = FPE_FLTUNK; 1998 int err; 1999 2000 flush_spe_to_thread(current); 2001 2002 spefscr = current->thread.spefscr; 2003 fpexc_mode = current->thread.fpexc_mode; 2004 2005 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2006 code = FPE_FLTOVF; 2007 } 2008 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2009 code = FPE_FLTUND; 2010 } 2011 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2012 code = FPE_FLTDIV; 2013 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2014 code = FPE_FLTINV; 2015 } 2016 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2017 code = FPE_FLTRES; 2018 2019 err = do_spe_mathemu(regs); 2020 if (err == 0) { 2021 regs->nip += 4; /* skip emulated instruction */ 2022 emulate_single_step(regs); 2023 return; 2024 } 2025 2026 if (err == -EFAULT) { 2027 /* got an error reading the instruction */ 2028 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2029 } else if (err == -EINVAL) { 2030 /* didn't recognize the instruction */ 2031 printk(KERN_ERR "unrecognized spe instruction " 2032 "in %s at %lx\n", current->comm, regs->nip); 2033 } else { 2034 _exception(SIGFPE, regs, code, regs->nip); 2035 } 2036 2037 return; 2038 } 2039 2040 void SPEFloatingPointRoundException(struct pt_regs *regs) 2041 { 2042 extern int speround_handler(struct pt_regs *regs); 2043 int err; 2044 2045 preempt_disable(); 2046 if (regs->msr & MSR_SPE) 2047 giveup_spe(current); 2048 preempt_enable(); 2049 2050 regs->nip -= 4; 2051 err = speround_handler(regs); 2052 if (err == 0) { 2053 regs->nip += 4; /* skip emulated instruction */ 2054 emulate_single_step(regs); 2055 return; 2056 } 2057 2058 if (err == -EFAULT) { 2059 /* got an error reading the instruction */ 2060 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2061 } else if (err == -EINVAL) { 2062 /* didn't recognize the instruction */ 2063 printk(KERN_ERR "unrecognized spe instruction " 2064 "in %s at %lx\n", current->comm, regs->nip); 2065 } else { 2066 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2067 return; 2068 } 2069 } 2070 #endif 2071 2072 /* 2073 * We enter here if we get an unrecoverable exception, that is, one 2074 * that happened at a point where the RI (recoverable interrupt) bit 2075 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2076 * we therefore lost state by taking this exception. 2077 */ 2078 void unrecoverable_exception(struct pt_regs *regs) 2079 { 2080 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2081 regs->trap, regs->nip, regs->msr); 2082 die("Unrecoverable exception", regs, SIGABRT); 2083 } 2084 NOKPROBE_SYMBOL(unrecoverable_exception); 2085 2086 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2087 /* 2088 * Default handler for a Watchdog exception, 2089 * spins until a reboot occurs 2090 */ 2091 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2092 { 2093 /* Generic WatchdogHandler, implement your own */ 2094 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2095 return; 2096 } 2097 2098 void WatchdogException(struct pt_regs *regs) 2099 { 2100 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2101 WatchdogHandler(regs); 2102 } 2103 #endif 2104 2105 /* 2106 * We enter here if we discover during exception entry that we are 2107 * running in supervisor mode with a userspace value in the stack pointer. 2108 */ 2109 void kernel_bad_stack(struct pt_regs *regs) 2110 { 2111 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2112 regs->gpr[1], regs->nip); 2113 die("Bad kernel stack pointer", regs, SIGABRT); 2114 } 2115 NOKPROBE_SYMBOL(kernel_bad_stack); 2116 2117 void __init trap_init(void) 2118 { 2119 } 2120 2121 2122 #ifdef CONFIG_PPC_EMULATED_STATS 2123 2124 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2125 2126 struct ppc_emulated ppc_emulated = { 2127 #ifdef CONFIG_ALTIVEC 2128 WARN_EMULATED_SETUP(altivec), 2129 #endif 2130 WARN_EMULATED_SETUP(dcba), 2131 WARN_EMULATED_SETUP(dcbz), 2132 WARN_EMULATED_SETUP(fp_pair), 2133 WARN_EMULATED_SETUP(isel), 2134 WARN_EMULATED_SETUP(mcrxr), 2135 WARN_EMULATED_SETUP(mfpvr), 2136 WARN_EMULATED_SETUP(multiple), 2137 WARN_EMULATED_SETUP(popcntb), 2138 WARN_EMULATED_SETUP(spe), 2139 WARN_EMULATED_SETUP(string), 2140 WARN_EMULATED_SETUP(sync), 2141 WARN_EMULATED_SETUP(unaligned), 2142 #ifdef CONFIG_MATH_EMULATION 2143 WARN_EMULATED_SETUP(math), 2144 #endif 2145 #ifdef CONFIG_VSX 2146 WARN_EMULATED_SETUP(vsx), 2147 #endif 2148 #ifdef CONFIG_PPC64 2149 WARN_EMULATED_SETUP(mfdscr), 2150 WARN_EMULATED_SETUP(mtdscr), 2151 WARN_EMULATED_SETUP(lq_stq), 2152 WARN_EMULATED_SETUP(lxvw4x), 2153 WARN_EMULATED_SETUP(lxvh8x), 2154 WARN_EMULATED_SETUP(lxvd2x), 2155 WARN_EMULATED_SETUP(lxvb16x), 2156 #endif 2157 }; 2158 2159 u32 ppc_warn_emulated; 2160 2161 void ppc_warn_emulated_print(const char *type) 2162 { 2163 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2164 type); 2165 } 2166 2167 static int __init ppc_warn_emulated_init(void) 2168 { 2169 struct dentry *dir, *d; 2170 unsigned int i; 2171 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2172 2173 if (!powerpc_debugfs_root) 2174 return -ENODEV; 2175 2176 dir = debugfs_create_dir("emulated_instructions", 2177 powerpc_debugfs_root); 2178 if (!dir) 2179 return -ENOMEM; 2180 2181 d = debugfs_create_u32("do_warn", 0644, dir, 2182 &ppc_warn_emulated); 2183 if (!d) 2184 goto fail; 2185 2186 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 2187 d = debugfs_create_u32(entries[i].name, 0644, dir, 2188 (u32 *)&entries[i].val.counter); 2189 if (!d) 2190 goto fail; 2191 } 2192 2193 return 0; 2194 2195 fail: 2196 debugfs_remove_recursive(dir); 2197 return -ENOMEM; 2198 } 2199 2200 device_initcall(ppc_warn_emulated_init); 2201 2202 #endif /* CONFIG_PPC_EMULATED_STATS */ 2203